Power supply miniaturized module test fixture

Abstract

The utility model discloses a power supply miniaturized module test fixture which comprises a PCB and a test seat, the PCB is provided with an XECDC-1 test circuit and an XECDC-2 test circuit, the test seat is installed on the PCB, the test seat is provided with a first groove and a second groove which are used for placing a first power supply module and a second power supply module, and the first groove and the second groove are communicated with each other. The XECDC-2 test circuit is used for testing undervoltage, overvoltage, reverse connection, output clamping and load overcurrent of the second power module, the XECDC-1 test circuit is used for testing voltage output control of the first power module, and the test seat is connected with a corresponding bonding pad on the PCB through an elastic telescopic test probe. According to the utility model, the stability is improved, the service life of the clamp is prolonged, the size is reduced by 30%, the test interface layout is reasonable, the test is convenient, the detection efficiency is improved, the contact efficiency of the probe and the pin is improved by 50%, the continuous test time of the clamp is prolonged from 20 minutes to more than 2 hours, and the stability of the clamp is greatly improved.

Description

Technical Field

[0001] The utility model relates to a test fixture for a power supply miniaturization module, belonging to the technical field of power supply module test fixtures. Background Art

[0002] There is no integrated test fixture for the power supply miniaturization module, resulting in simple post-production testing of products and inaccurate data. Some parameters are shipped through technical review, posing a greater quality risk.

[0003] Previously, the method of manually contacting the product pins with a probe was used for testing, with serious instability, a risk of poor contact and burning of the product, and low testing efficiency at the same time; the test probe is a consumable part that needs to be replaced after long-term use and wear. The current method is inconvenient for maintenance and replacement, wasting labor costs.

[0004] The power resistors and MOS transistors have insufficient heat dissipation, easily leading to overheating of the power resistors and MOS transistors. The component layout is inappropriate, and the overheating of the resistors poses a safety hazard, and seriously delays the product testing time, and the product cannot be continuously tested for more than 20 minutes. Summary of the Invention

[0005] The technical problem to be solved by the utility model is to provide a test fixture for a power supply miniaturization module to solve the problems existing in the above-mentioned prior art.

[0006] The technical solution adopted by the utility model is as follows: a test fixture for a power supply miniaturization module includes a PCB board and a test seat. The PCB board is provided with an XECDC-1 test circuit and an XECDC-2 test circuit. The test seat is installed on the PCB board. The test seat is provided with a groove one and a groove two for placing a power supply module one and a power supply module two. The XECDC-2 test circuit is used for testing undervoltage, overvoltage, reverse connection, output clamping and load overcurrent of the power supply module two. The XECDC-1 test circuit is used for testing the voltage output control of the power supply module one.

[0007] Further, the above test seat is connected to the corresponding pads on the PCB board through elastic telescopic test probes.

[0008] Further, the above test seat includes a base and a lid. The lid is covered on the base through two groups of magnets.

[0009] Further, the above XECDC-1 test circuit includes a capacitor C1, switches K1, K2, K3, and K4. One end of the capacitor C1 is grounded, and the other end is connected to the power-on control terminal, one ends of the switches K1 and K2. The other end of the switch K1 is connected to the CNTL1 terminal of the first power supply module. The other end of the switch K2 is connected to one end of the switch K3 and the CNTL2 terminal of the first power supply module. The other end of the switch K3 is connected to one end of the switch K4 and the CNTL3 terminal of the first power supply module. The other end of the switch K4 is connected to the IN terminal. Two VCC terminals of the first power supply module are connected to the IN terminal. Two GND terminals of the first power supply module are grounded. The SCNTL terminal of the first power supply module is connected to the ON / OFF terminal.

[0010] Further, the above XECDC-2 test circuit includes a MOS transistor V1, a MOS transistor V2, and a power resistor R8. The drain of the MOS transistor V1 is connected to one ends of a capacitor C2, a capacitor C3, a resistor R11, the IN terminal, and the VIN terminal of the second power supply module. The other end of the R11 is connected to one end of a resistor R13 and the OV terminal of the second power supply module. The other ends of the resistor R13, the capacitor C2, and the capacitor C3 are grounded. The gate of the MOS transistor V1 is connected to the GT1 terminal of the second power supply module. The source of the MOS transistor V1 is connected to the source of the MOS transistor V2. The gate of the MOS transistor V2 is connected to the GT2 terminal of the second power supply module. The drain of the MOS transistor V2 is connected to one end of a resistor R7 and the ISEN terminal of the second power supply module. The other end of the resistor R7 is connected to one end of a resistor R5. The other end of the resistor R5 is connected to the VOUT terminal of the second power supply module, one ends of a capacitor C4 and the power resistor R8. The other ends of the capacitor C4 and the power resistor R8 are grounded. A resistor R6 is connected between the PGND terminal and the EO terminal of the second power supply module. The OE terminal of the second power supply module is connected to the grounded terminal through a resistor R12. The FAULT TIME terminal, the SURGE CURENT terminal, the PLIERS LOCI terminal, and the UV terminal of the second power supply module are respectively connected to one ends of a capacitor C6, a capacitor C5, a resistor R6, and a resistor R10. The other ends of the capacitor C6, the capacitor C5, the resistor R6, and the resistor R10 are grounded. The resistors R5, R7, and R9 are adjustable resistors.

[0011] Further, the above-mentioned power resistor R8 is installed in the upper left corner of the PCB board. A radiator is installed on the power resistor R8. The MOS transistors V1 and V2 are attached to the copper layer near the middle on the right side of the PCB board through a soldering layer, and vias are provided at this location. The switches K1, K2, K3, and K4 are arranged on the front side of the PCB board. The power-on control terminal is a switch arranged on the PCB board to the right of the switch K4. The ON / OFF terminal is arranged on the left side of the switch K1, and this terminal is controlled by a switch. An overcurrent closing terminal controlled by a switch is arranged above this terminal. On the PCB board behind the power-on control terminal, the output ends of the XECDC-1 test circuit and the XECDC-2 test circuit are respectively controlled by two switches for output.

[0012] The XECDC-1 test circuit and the XECDC-2 test circuit are integrated together, and the two circuits are respectively controlled to achieve the test function. The XECDC-2 test circuit realizes the functions of undervoltage, overvoltage, reverse connection, output clamping, and load overcurrent testing by driving two MOSFETs V1 and V2, as well as the 4.7K resistor R9, the 10mΩ resistors R5 and R7. The XECDC-1 test circuit realizes the control of voltage output by controlling the boat switches K1, K2, K3, K4 and the power-on control terminal.

[0013] The two surge suppressors V1 and V2 as passive power devices are N-channel MOSFET devices.

[0014] The beneficial effects of the present utility model: Compared with the prior art, the present utility model integrates the XECDC-1 test circuit and the XECDC-2 test circuit on a single PCB board, improving stability, the service life of the fixture, reducing the size by 30%, having a reasonable layout of test interfaces, being convenient for testing, improving the detection efficiency, and different overvoltage protections can be set by adjusting the resistance value of the resistor R9, and different overcurrent protections can be set by adjusting the resistance values of the resistors R5 and R7. The contact efficiency between the probe and the pin is increased by 50%, and the continuous test time of the fixture is increased from 20 minutes to more than 2 hours, greatly improving the stability of the fixture, effectively solving the problems of unstable fixture, low production efficiency, and inconvenient maintenance in the prior art. Installing a radiator and attaching the MOS transistors to the copper layer of the PCB board through a soldering layer and providing vias can improve the heat dissipation effect and solve the problem of insufficient heat dissipation of the MOS transistors and the power resistor. Description of the Drawings

[0015] Figure 1 It is a top view structure pin diagram of the power module one XECDC-1;

[0016] Figure 2 It is a bottom view structure pin diagram of the power module one XECDC-1;

[0017] Figure 3It is the top view structure pin diagram of the power supply module two XECDC-2;

[0018] Figure 4 It is the bottom view structure pin diagram of the power supply module two XECDC-2;

[0019] Figure 5 It is the test circuit diagram of XECDC-1;

[0020] Figure 6 It is the test circuit diagram of XECDC-2;

[0021] Figure 7 It is the circuit diagram of the power supply module one XECDC-1 (when testing in state 1);

[0022] Figure 8 It is the circuit diagram of the power supply module one XECDC-1 (when testing in state 2);

[0023] Figure 9 It is the circuit diagram of the power supply module two XECDC-2;

[0024] Figure 10 It is the test fixture diagram;

[0025] Figure 11 It is the schematic diagram of the cross-sectional structure of the test socket;

[0026] Figure 12 It is the schematic diagram of the three-dimensional structure of the base;

[0027] Figure 13 It is the schematic diagram of the three-dimensional structure of the box cover;

[0028] Figure 14 It is the layout diagram of the PCB board. Specific implementation manners

[0029] The following further introduces the present utility model in combination with the accompanying drawings and specific embodiments.

[0030] Embodiment 1: As Figure 1-14 shown, a test fixture for a power supply miniaturization module includes a PCB board 1 and a test socket 2. The PCB board 1 is arranged with an XECDC-1 test circuit and an XECDC-2 test circuit. The test socket 2 is installed on the PCB board 1. The test socket 2 is provided with a groove one 3 and a groove two 4 for placing the power supply module one and the power supply module two. The XECDC-2 test circuit is used to test the undervoltage, overvoltage, reverse connection, output clamping and load overcurrent of the power supply module two. The XECDC-1 test circuit is used to test the voltage output control of the power supply module one. By controlling the surge suppressor, chip resistor, inductor, and boat switch, the two circuits are respectively controlled to achieve complex test functions.

[0031] For the reliability of the conductive connection, the above test socket 2 is connected to the corresponding pads on the PCB board 1 through the elastic telescopic test probe 5. The elastic telescopic test probe conducts electricity to connect the pins of the power module and the pads on the PCB board, and the conductive connection is more reliable.

[0032] To facilitate the quick and reliable connection of the power module to the first groove and the second groove, the above test socket 2 includes a base 201 and a cover 202. The cover 202 is covered on the base 201 through two groups of magnets 203. Through the adsorption of the magnets, the loading and unloading are fast and the connection is reliable. There are also notch grooves 204 on both sides of the first groove 3 and the second groove 4 provided on the base 201, which is convenient for taking the power module. A cavity 205 is provided near the bottom of the base 201. The four sides of the cavity 205 are open. A square hole is opened at the bottom of the cavity 205 where the elastic telescopic test probe 5 is located. This structure is convenient for installing the elastic telescopic test probe 5. Two inlaid positioning grooves 206 are provided on the cover 202 opposite to the first groove 3 and the second groove 4, which is convenient for pressing and limiting the first power module and the second power module, so as to improve the electrical connection reliability between the pins of the power module and the elastic telescopic test probe 5. Two diagonal positioning pins 207 are also provided on the cover 202. The positioning pins 207 are inserted into the large holes of the step mounting holes 208 of the base 201 for positioning, which can improve the positioning accuracy and quickly fix and connect under the adsorption of the magnets.

[0033] Pin introduction of power module XECDC-1:

[0034] 1: Control 1; 2: Control 2; 3: Control 3; 4 and 8: GND; 5 and 6: Power input; 7: Shutdown.

[0035] Pin introduction of power module XECDC-2:

[0036] 1: Gate 1; 2: Current detection point; 3: Common source; 4, 6, 7, 12 and 19: PGND; 5: Gate 2; 8: Surge current point; 9, 14, 23: Power output; 10, 13, 21: Power input; 11: Clamping point; 15: Undervoltage point; 16: Shutdown control; 17: Enable output; 18: Fault timing; 20: Fault output; 22: Overvoltage point; 24: Current detection point.

[0037] Gate 1: Gate drive output. Internally connected to the gate drive output terminal (HGATE) of the surge suppressor through a series of 10-ohm resistors. Both the voltage and current amplifiers can control the internal HGATE pin to adjust the output voltage and limit the current flowing through the MOSFET.

[0038] Current Detection Point: Current detection input. Connect this pin to the input of the current sense resistor. Connect a current sense resistor between the current detection point and the power output. During overcurrent, the internal HGATE pin voltage is automatically adjusted to limit the current sense voltage (VSNS) across the current sense resistor to 50 mV (when the output voltage is higher than 2.5 V). The current detector, whose resistance (RSNS) is determined by the following formula:

[0039]

[0040] Where ILIM is the required protection current value. For example: If protection is required to start at 2.5 A, then from the formula RSNS is 20 mΩ (VSNS remains 50 mV). When not in use, this pin is connected to the power output.

[0041] Common Source: Common source input and gate drive return. Connect this pin directly to the source of the external back-to-back N-channel MOSFET. The common source is the positive pole of the ideal diode, and the voltage detected between this pin and the current detection point pin is used to control the source-drain voltage on the N-channel MOSFET (the forward voltage of the ideal diode).

[0042] PGND: Ground pin of the device.

[0043] Gate 2: Diode controller gate drive output. When the load current generates a voltage drop of more than 30 mV across the MOSFET, the Gate 2 pin is pulled high by an internal charge pump current source and clamped at a level 12 V higher than the common source. When the load current is very small, the Gate 2 pin is actively driven to maintain 30 mA across the MOSFET. A fast pull-down circuit will quickly connect the Gate 2 pin to the common source pin, thus turning off the MOSFET. When not in use, this pin is connected to the common source or left open.

[0044] Surge Current Point: Surge current detection point, internally connected in series with 100 ohms to the surge suppressor gate drive output (HGATE).

[0045] Power Output: Output voltage detection input. This pin is responsible for detecting the drain voltage of the external N-channel MOSFET connected to the Gate 2 pin. The voltage difference between the power input and the power output sets the fault timer current. When this voltage drops below 0.7 V, the enable output goes to high impedance.

[0046] Power Input: Power input terminal. Operating voltage range: 4 V - 80 V.

[0047] Clamp Point: Regulator feedback input. Connect this pin to a resistive divider between the output and ground. In the case of overvoltage, control the internal HGATE pin to maintain a voltage of 1.25V at the Clamp Point pin. Connecting this pin to PGND disables the overvoltage clamp function.

[0048] Under Voltage Point: Undervoltage comparator input. When the Under Voltage Point pin drops below its 1.25V threshold, the XECDC-2 will be in the undervoltage protection state. The internal undervoltage dividing resistor RU is 110K, and the undervoltage setting resistor R10 (kept consistent with Figure 6 the XECDC-2 test circuit) can be determined by the following formula:

[0049]

[0050] where VU is the undervoltage value to be set. For example, when the undervoltage protection is 15V, from the formula, R10 is 10K.

[0051] Shutdown Control: Shutdown control pin. Pulling the Shutdown Control pin below 0.5V will turn off the XECDC-2. Pulling this pin above 2.2V or leaving it floating will allow the internal current to reconnect the device, and the device will be in normal operation.

[0052] Enable Output: This is an open-drain output that goes to high impedance when the voltage on the Voltage Output pin is higher than (Vcc - 0.7V), indicating that the external MOSFET is fully conducting. When the output voltage drops below 2.2V, the state of this pin is latched and a reset operation is performed. The internal FET can sink up to 2mA of current and can withstand up to 80V of voltage. Connect this pin to ground when not in use.

[0053] Fault Timing: Fault timer input. Connect a capacitor between this pin and ground to set the time for fault alarm, fault shutdown, and cooling cycle. The start of voltage regulation or current regulation pulls up the voltage of the Fault Timing pin. The current charging this pin in the case of a fault increases with the increase in the voltage difference between the input voltage and output voltage pins. When the Fault Timing terminal reaches 1.25V, the Fault Output terminal is pulled to low level to indicate that a certain fault situation is detected. If this fault situation persists, the transfer device controlled by the internal HGATE will turn off when the Fault Timing reaches the 1.35V threshold. When the fault situation disappears, a cooling cycle will start immediately, and at the same time, the TMR pin will cycle 32 times between 0.15V and 1.35V with a charging and discharging current of 2uA. When the voltage of the TMR pin exceeds 0.15V for the 32nd time, it will be allowed to pull up the internal HGATE pin, so as to reconnect the transfer device when the voltage of the 0V pin is below its threshold voltage.

[0054] Fault Output: Fault output terminal. This is an open-drain output that will be pulled low after the TMR pin reaches the alarm threshold of 1.25V. Ground this pin when not in use.

[0055] Overvoltage Point: Input of the overvoltage comparator. When the overvoltage point is higher than its 1.25V threshold, the fault retry function is disabled. When the overvoltage point drops to its threshold voltage, the internal HGATE pin will be allowed to conduct again when the fault condition is cleared. Ground this pin when not in use. The overvoltage resistance setting is determined by Figure 4 the voltage division of R11 and R13 in the XECDC-2 test circuit in

[0056]

[0057] where Vo is the overvoltage value to be set. For example, to set the overvoltage protection voltage to Vo = 36V and R11 = 1M, then R13 can be obtained from the formula as 36K.

[0058] Test Requirements:

[0059] (1) Input Undervoltage Test: When the input voltage is less than 15V, the circuit has no output voltage;

[0060] (2) Input Overvoltage Test: When the input voltage is greater than 36V, the circuit has no output voltage;

[0061] (3) Input Reverse Connection Test: When the input voltage polarity is reversed, the circuit has no output voltage;

[0062] (4) Output Clamping Test: When the input voltage is greater than 36V, the output power supply maintains the output voltage for about 500ms and then shuts off;

[0063] (5) Load Overcurrent Test: When the load current is greater than 2.5A, the circuit is in short-circuit protection state;

[0064] (6) Power-on Control Test (There is output voltage when pin 16 is floating; there is no output voltage when pin 16 is grounded);

[0065] (7) Test and record the voltages of pin 1 and pin 5 (When the input voltage is 28V, the voltage of the first pin is 38 ± 1V, and the voltage of the 5th pin is 32 ± 1V).

[0066] Further, the above XECDC-1 test circuit includes a capacitor C1, switches K1, K2, K3, and K4. One end of the capacitor C1 is grounded, and the other end is connected to the power-on control terminal, one ends of the switches K1 and K2. The other end of the switch K1 is connected to the CNTL1 terminal of the first power supply module, the other end of the switch K2 is connected to one end of the switch K3 and the CNTL2 terminal of the first power supply module, the other end of the switch K3 is connected to one end of the switch K4 and the CNTL3 terminal of the first power supply module, the other end of the switch K4 is connected to the IN terminal, two VCC terminals of the first power supply module are connected to the IN terminal, two GND terminals of the first power supply module are grounded, and the SCNTL terminal of the first power supply module is connected to the ON / OFF terminal.

[0067] The schematic diagram of XECDC-1 is as Figure 7 When Figure 5 shown. This circuit controls the on / off of V4 and V7 by changing the external connections (Control 1, Control 2, Control 3), so as to realize the inversion of the output of the shutdown control terminal (0V or Vcc). When the "non-power-off" anomaly occurs, that is, the shutdown output does not invert with the external changes and always outputs Vcc (the input voltage is 28V when testing this circuit).

[0068] The test method for the power supply module XECDC-1 is as follows: the terminal voltage between the input IN terminal and the GND terminal is 28V.

[0069] (1) Install switches K2 and K4, and do not install switches K1 and K3. When the power-on control terminal is floating, the output voltage of the ON / OFF terminal is 28V; when the power-on control terminal is grounded, the output voltage of the ON / OFF terminal is 0V.

[0070] (2) Do not install switches K2 and K4, and install switches K1 and K3. When the power-on control terminal is floating, the output voltage of the ON / OFF terminal is 0V; when the power-on control terminal is grounded, the output voltage of the ON / OFF terminal is 28V.

[0071] Since the anomaly of this device is "non-power-off", that is, the output is always 28V and will not invert. Analyze the circuits required for the tests "(1) when K2 and K4 are installed and K1 and K3 are not installed, (2) when K2 and K4 are not installed and K1 and K3 are installed" to find the reasons. Verify whether the theoretical and actual abnormal performances are consistent, so as to conduct mechanism analysis.

[0072] When the situation of (1) occurs, the phenomenon seen when disassembling the shell of XECDC-1 before is that R1 is soldered loosely, that is, it is not connected to the circuit. In Figure 7 if R1 is not connected to the circuit, no matter whether the power-on control terminal is floating or grounded, the base voltage of V7 cannot turn on V7, so the shutdown control will always output high (28V).

[0073] When the situation in (2) occurs, regardless of whether the power-on control terminal is floating or grounded, the shutdown control terminal outputs high (28V).

[0074] Based on the above analysis, it is consistent with the "non-power-off" phenomenon. That is, the abnormality is caused by the virtual soldering of R1 in the product.

[0075] Furthermore, the above XECDC-2 test circuit includes MOS transistor V1, MOS transistor V2, and power resistor R8. The drain of MOS transistor V1 is connected to one end of capacitor C2, capacitor C3, resistor R11, the IN terminal, and the VIN terminal of power module two. The other end of R11 is connected to one end of resistor R13 and the OV terminal of power module two. The other ends of resistor R13, capacitor C2, and capacitor C3 are grounded. The gate of MOS transistor V1 is connected to the GT1 terminal of power module two. The source of MOS transistor V1 is connected to the source of MOS transistor V2. The gate of MOS transistor V2 is connected to the GT2 terminal of power module two. The drain of MOS transistor V2 is connected to one end of resistor R7 and the ISEN terminal of power module two. The other end of resistor R7 is connected to one end of resistor R5. The other end of resistor R5 is connected to the VOUT terminal of power module two, capacitor C4, and one end of power resistor R8. The other ends of capacitor C4 and power resistor R8 are grounded. A resistor R6 is connected between the PGND terminal and the EO terminal of power module two. The OE terminal of power module two is connected to the ground terminal through resistor R12. The FAULT TIME terminal, SURGE CURENT terminal, PLIERS LOCI terminal, and UV terminal of power module two are respectively connected to one end of capacitor C6, capacitor C5, resistor R6, and resistor R10. The other ends of capacitor C6, capacitor C5, resistor R6, and resistor R10 are grounded. A radiator is installed on power resistor R8. Power resistor R8 uses cement load resistors R8-1 and R8-2.

[0076] Furthermore, the above MOS transistor V1 and MOS transistor V2 are attached to the copper layer near the middle on the right side of PCB board 1 through a soldering layer, and a via 7 is set at this place. Switches K1, K2, K3, and K4 are arranged on the front side of PCB board 1. The power-on control terminal is a switch set on PCB board 1 to the right of switch K4. An ON / OFF terminal is arranged to the left of switch K1, and this terminal is controlled by a switch. An overcurrent closing terminal controlled by a switch is arranged above this terminal. The output terminals of the XECDC-1 test circuit and the XECDC-2 test circuit located behind the power-on control terminal are respectively controlled by two switches for output.

[0077] The schematic diagram of XECDC-2 is as Figure 9, its core device is LTC4364HS-2#PBF, and the rest of the devices can be regarded as auxiliary circuits and protection circuits to enable it to work properly. The overvoltage, undervoltage, and clamp point threshold voltages are all 1.25V, and they are all controlled by series resistive voltage division. The N-channel field-effect transistor in the peripheral circuit mainly plays a role of "adjusting balance". In the circuit, Gate 1 and Gate 2 correspond to Pin 1 and Pin 5 of the product. When the input is 28V, the corresponding output voltages of Pin 1 and Pin 5 should be about 38V and 32V.

[0078] The "no boost" anomaly means that the voltages of Gate 1 and Gate 2 are abnormal. From the anomalies found in the previous disassembly and analysis, there are anomalies at R2, R4, V2, and C3. If R4 is poorly connected (loose solder or open circuit), it is equivalent to not supplying power to LTC4364HS-2#PBF, so it is impossible to boost; if V2 is poorly connected (loose solder or open circuit), it is equivalent to an open circuit between Gate 2 and the common source, so it cannot boost or is unstable; R2 is mainly used for undervoltage setting, and an anomaly will only cause the undervoltage protection function to fail; C3 is mainly used for filtering, and an anomaly will not cause the no-boost anomaly.

[0079] In summary, the "no boost" anomaly is mainly caused by poor connection (loose solder or open circuit) of R4 and V2.

[0080] Circuit logic: As Figure 5 shown, XECDC-1 and XECDC-2 switches are used to control the on / off of the DC-1 and DC-2 test circuits respectively. MOS transistor V1 is connected in parallel with C2, C3, and R11, and the backend is respectively connected to Pin 10 of the chip, GND, and Pin 4 of the chip in the corresponding schematic diagram. R5-R6 are connected to Pins 2 and 9 of the chip, and are connected through the internal circuit of the chip to achieve 2.5A overcurrent protection control. R9 is connected to Pin 11 of the chip, and the other end is connected to GND to achieve 36V overvoltage protection control. R10 is connected to Pin 15 of the chip, and the other end is connected to GND to achieve 15V undervoltage protection control. The test base and the pin header are centered and connected to the corresponding pins of the PCB diagram. At the same time, Pins 1 and 5 are arranged in the upper right corner of the fixture and evenly distributed for convenient multimeter testing. For the power-on control part of XECDC-1, a 1000pF capacitor is connected to GND and cooperates with K1-K4 switches to achieve the on / off of the DC-1 current.

[0081] The XECDC-2 drives two N-channel MOSFETs, V1 and V2, which are passive power devices, to conduct current to the load. Important characteristics of the MOSFETs include on-resistance (RDS(ON)), maximum drain-source voltage (V(BR)DSS), threshold voltage, and safe operating area (SOA). The maximum drain-source voltage rating must be higher than the maximum input voltage. If the output is shorted to ground or during overvoltage, the full supply voltage will be applied across V1; if the input is shorted to ground, the voltage held on the output will stress V2.

[0082] For applications where the input voltage (VIN) is higher than 8V, the gate drive voltage for both MOSFETs is guaranteed to be higher than 10V and lower than 16V. This allows the use of standard threshold voltage N-channel MOSFETs; for systems with an input voltage (VIN) lower than 8V, a logic-level MOSFET is required because the gate drive voltage can be as low as 5V; for an input supply of 28V or higher, it is recommended to place a 15V Zener diode between the gate and source of each MOSFET to provide additional protection.

[0083] Layout considerations: To achieve accurate current sensing, a Kelvin connection to the current sense resistor RSNS should be used. Limit the resistance between the current sense point and the MOSFET source to below 10Ω. For 1 ounce copper foil, the minimum trace width is 0.02 inches per ampere to ensure the trace remains at a reasonable temperature. Also, note that 1 ounce copper has a sheet resistance of approximately 530 uΩ per square inch. In high-current applications, small resistances can cause significant errors. Placing the resistive divider close to the pins with short VIN and PGND traces will significantly improve the noise impact.

[0084] Others:

[0085] (1) Different overvoltage protections can be set by adjusting the resistance value of R9 in Figure 6 .

[0086] (2) Different overcurrent protections can be set by adjusting the resistance values of R5 and R7 in Figure 6 .

[0087] In summary, the PCB board 1, the XECDC-1 test circuit, and the XECDC-2 test circuit are made into an integrated test fixture through the SMT soldering process, which improves stability, extends the service life of the fixture, reduces the size by 30%, has a reasonable test interface layout, is convenient for testing, improves the detection efficiency, and can set different overvoltage protections by adjusting the resistance value of resistor R9, and can set different overcurrent protections by adjusting the resistance values of R5 and R7. The contact efficiency between the probe and the pin is increased by 50%, the problem of insufficient heat dissipation of the MOS transistor and the power resistor is solved, and the continuous test time of the fixture is increased from 20 minutes to more than 2 hours, greatly improving the stability of the fixture. It effectively solves the problems of unstable fixture, low production efficiency, and inconvenient maintenance in the prior art.

[0088] Embodiment 2: A test method for a power supply miniaturization module test fixture, which includes a test method for the XECDC-1 test circuit and a test method for the XECDC-2 test circuit;

[0089] Among them, the test method for the XECDC-1 test circuit is as follows: It includes two-state tests. Among them, the first state test is: Switch K2 and switch K4 are closed, and switch K1 and switch K3 are open. When the power supply control terminal is floating, the output voltage of the ON / OFF terminal is 28V; when the power supply control terminal is grounded, the output voltage of the ON / OFF terminal is 0V. The schematic diagram of state 1 is as Figure 7 shown, and the test connection diagram is as Figure 5 shown. This circuit controls the on / off of V4 and V7 through the transformation of the external (control 1, control 2, control 3) circuit, so as to realize the inversion (0V or Vcc) of the output voltage of the shutdown control terminal. When the abnormality of "the shutdown control terminal always outputs 0V" occurs, that is, the shutdown output voltage does not flip with the external transformation and always outputs 0V;

[0090] The second state test is: Switch K2 and switch K4 are open, and switch K1 and switch K3 are closed. When the power supply control terminal is floating, the output voltage of the ON / OFF terminal is 0V; when the power supply control terminal is grounded, the output voltage of the ON / OFF terminal is 28V; The schematic diagram of state 2 is as Figure 8 shown. From Figure 8 the principle analysis of actual operation, when powering on normally, V4 is in the off state, and the collector outputs high (28V); when the "power supply control terminal" is floating, V7 will be turned on, so that the shutdown control terminal outputs low (0V); when the "power supply control terminal" is grounded, the collector voltage of V4 will be pulled down, and the base voltage of V7 will also be pulled down, and V7 will be turned off, so that the shutdown control terminal outputs high (28V)

[0091] The test method for the XECDC-2 test circuit includes the following tests:

[0092] (1) Under-voltage test: When the voltage at pin 15 of Power Module 2 drops below its 1.25V threshold, XECDC-2 will enter the under-voltage protection state. The internal under-voltage voltage-dividing resistor R U is 110K, and the under-voltage setting resistor R10 (which should be consistent with the Figure 6 XECDC-2 test circuit) can be determined by the following formula:

[0093]

[0094] where V U is the under-voltage value to be set. For example, when setting 15V under-voltage protection, according to the formula, R10 is 10K.

[0095] (2) Over-voltage test: When the voltage at pin 22 of Power Module 2 is higher than its 1.25V threshold, the fault retry function is disabled; when the over-voltage point drops to its threshold voltage of 1.25V, the internal HGATE pin of Power Module 2 will be allowed to conduct again when the fault condition is cleared. Connect this pin to ground when not in use. The over-voltage resistance setting is determined by the voltage division of R11 and R13 in the Figure 6 XECDC-2 test circuit in

[0096]

[0097] Specific calculation is determined by the following formula: where Vo is the over-voltage value to be set. For example, when setting the over-voltage protection voltage Vo = 36V and R11 = 1M, then according to the formula, R13 is 36K;

[0098] (3) Output clamping test: For the regulator feedback input, connect pin 11 of Power Module 2 to a resistive voltage divider between the output and ground. In the case of over-voltage, control the internal HGATE pin to maintain a voltage of 1.25V at pin 11. Connect this pin to PGND to disable the over-voltage clamping function.

[0099] (4) Load over-current test: Connect pin 2 of Power Module 2 to the input terminal of the current detection resistor. Connect a current detection resistor between pin 2 and pins 9, 14, and 23. During over-current, automatically adjust the voltage of the internal HGATE pin to limit the current detection voltage V SNS across the current detection resistor to 50mV (when the output voltage is higher than 2.5V). The current detector, whose resistance (R SNS ) is determined by the following formula:

[0100]

[0101] where I LIM is the required protection current value. For example: If 2.5A protection is required, then according to the formula, R SNSis 20 mΩ (V SNS is unchanged at 50 mV). When not in use, this pin is connected to the power output terminal.

[0102] As described above, it is only the specific implementation manner of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model can easily think of changes or substitutions, which should all be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claimed rights.

Claims

1. A power supply miniaturization module test fixture, characterized in that: The invention comprises a PCB board (1) and a test socket (2), wherein the PCB board (1) is provided with an XECDC-1 test circuit and an XECDC-2 test circuit, the test socket (2) is mounted on the PCB board (1), and the test socket (2) is provided with a first groove (3) and a second groove (4) for placing a power module 1 and a power module 2, the XECDC-2 test circuit is used to test undervoltage, overvoltage, reverse connection, output clamping and load overcurrent tests of the power module 2, and the XECDC-1 test circuit is used to test the voltage output control of the power module 1; the test socket (2) is connected to a corresponding pad on the PCB board (1) via an elastically retractable test probe (5).

2. A power miniaturized module test fixture according to claim 1, characterized in that: The test seat (2) comprises a base (201) and a box cover (202), and the box cover (202) is covered on the base (201) via two groups of magnets (203).

3. The power miniaturization module test fixture according to claim 1, characterized in that: The XECDC-1 test circuit includes capacitor C1, switch K1, switch K2, switch K3 and switch K4. One end of capacitor C1 is grounded, and the other end is connected to the power-on control end, switch K1 and one end of switch K2. The other end of switch K1 is connected to the CNTL1 end of power module one, the other end of switch K2 is connected to one end of switch K3 and the CNTL2 end of power module one, the other end of switch K3 is connected to one end of switch K4 and the CNTL3 end of power module one, the other end of switch K4 is connected to the IN end, the two VCC ends of power module one are connected to the IN end, the two GND ends of power module one are grounded, and the SCNTL end of power module one is connected to the ON / OFF end.

4. A power miniaturized module test fixture according to claim 3, characterized in that: The XECDC-2 test circuit includes MOS tube V1, MOS tube V2 and power resistor R8. The drain of MOS tube V1 is connected to capacitor C2, capacitor C3, one end of resistor R11 and IN end, and VIN end of power module 2. The other end of R11 is connected to one end of resistor R13 and OV end of power module 2. The other ends of resistor R13, capacitor C2 and capacitor C3 are grounded. The gate of the MOS tube V1 is connected to the GT1 terminal of the power module 2, the source of the MOS tube V1 is connected to the source of the MOS tube V2, the gate of the MOS tube V2 is connected to the GT2 terminal of the power module 2, the drain of the MOS tube V2 is connected to one end of the resistor R7 and the ISEN terminal of the power module 2, the other end of the resistor R7 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to the VOUT terminal of the power module 2, the capacitor C4 and one end of the power resistor R8, the other ends of the capacitor C4 and the power resistor R8 are grounded, the PGND terminal and the EO terminal of the power module 2 are connected through the resistor R6, the OE terminal of the power module 2 is connected to the ground terminal through the resistor R12, the FAULT TIME terminal, the SURGE CURENT terminal, the PLIERSLOCI terminal and the UV terminal of the power module 2 are respectively connected to one end of the capacitor C6, the capacitor C5, the resistor R6 and the resistor R10, the other ends of the capacitor C6, the capacitor C5, the resistor R6 and the resistor R10 are grounded, and the resistors R5, R7 and R9 are adjustable resistors.

5. A power miniaturized module test fixture according to claim 4, characterized in that: The power resistor R8 is mounted on the upper left corner of the PCB (1), and a heat sink (6) is mounted on the power resistor R8. The MOS tube V1 and the MOS tube V2 are attached to the copper layer near the middle of the right side of the PCB (1) through a solder layer, and a via hole (7) is provided there. The switch K1, the switch K2, the switch K3 and the switch K4 are arranged on the front side of the PCB (1), and the power-on control terminal is a switch arranged on the PCB (1) on the right side of the switch K4.

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