Terminal structure and semiconductor device
By setting the field limit ring and field plate in the terminal structure of the SiC MOSFET to shield the electric field of the field limit ring, the problem of insufficient voltage withstandability of SiC MOSFET is solved and a higher voltage withstandability is achieved.
Patent Information
- Application Number
- CN202520931736.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-13
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2035-05-13
AI Technical Summary
In the prior art, SiC MOSFETs have insufficient voltage withstandability and are difficult to operate effectively in large voltage environments.
By providing a plurality of field limit rings in the substrate of the terminal structure and providing a field plate on the field limit ring, part of the field plate is located on the second surface and in contact with the field limit ring, the field plate has a second orthogonal projection on the first surface, covering at least one first orthogonal projection, thereby preventing the electric field from passing through the field plate to reach the field limit ring, shielding the electric field of the at least one field limit ring.
By shielding the electric field of the field limit ring, the width of the field limit ring can be wider, the charge dispersion space becomes larger, and the electric field peak value is reduced, thereby improving the voltage withstandability of the terminal structure.
Smart Images
Figure CN223024873U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of semiconductor devices. Specifically, it relates to a terminal structure and a semiconductor device. Background Art
[0002] The performance of traditional silicon-based semiconductor devices has gradually approached the physical limit of the material. Devices made of the third-generation semiconductor material represented by silicon carbide have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance. As a representative of SiC devices, SiC MOSFET (Silicon Carbide Metal-Oxide-Semiconductor Field-Effect Transistor) has many excellent characteristics such as low on-resistance, fast switching speed, and high operating frequency. It has now been gradually promoted and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible DC power transmission. It needs to challenge some extreme environments, such as being used in a high-voltage environment. Therefore, it is necessary to improve the breakdown voltage capability of silicon carbide devices.
[0003] The above information disclosed in the background art section is only used to enhance the understanding of the background art of the technology described in this article. Therefore, the background art may contain certain information that is not prior art known to those skilled in the art in this country. Summary of the Utility Model
[0004] The main purpose of this application is to provide a terminal structure and a semiconductor device to solve the problem of insufficient breakdown voltage capability of SiC MOSFET in the prior art.
[0005] To achieve the above object, according to one aspect of this application, a terminal structure is provided, including: a substrate having opposite first and second surfaces; a plurality of field limiting rings spaced apart in the substrate, the field limiting rings having a third surface on the side of the first surface close to the second surface, the field limiting rings and the second surface being on the same side of the first surface, and both the field limiting rings and the second surface having a first orthographic projection in the first surface; a field plate, part of the field plate being on the second surface and in contact with the field limiting rings, the field plate having a second orthographic projection on the first surface, and the second orthographic projection covering at least one first orthographic projection.
[0006] Optionally, the part of the substrate between adjacent field limiting rings protrudes beyond the field limiting rings.
[0007] Optionally, the vertical distance between the third surface and the second surface is 0.01 μm to 5 μm, and the width of the third surface in the first direction is 0.1 μm to 10 μm, where the first direction is the arrangement direction of the plurality of field limiting rings.
[0008] Optionally, the terminal structure further includes a field oxide layer that covers the substrate located between adjacent field limiting rings and part of the field limiting rings.
[0009] Optionally, the field plate includes a first conductive layer and a second conductive layer, where: the first conductive layer covers the second surface, part of the third surface, and part of the field oxide layer; the second conductive layer covers the first conductive layer.
[0010] Optionally, the substrate includes a substrate and a drift layer. The drift layer is located on one side of the substrate, the field limiting rings are located in the drift layer, and the surface of the drift layer facing away from the substrate is the first surface.
[0011] Optionally, the terminal structure further includes an alignment mark located in the edge region of the terminal structure. The alignment mark is recessed into the drift layer in the direction from the drift layer to the substrate.
[0012] Optionally, the field oxide layer and the field plate have partial overlap.
[0013] Optionally, the terminal structure further includes a back electrode located on the first surface.
[0014] According to another aspect of the present application, a semiconductor device is provided, including the terminal structure described above.
[0015] Applying the technical solution of the present application, a plurality of field limiting rings are arranged in the substrate of the terminal structure. The field limiting ring has a third surface located on one side of the first surface close to the second surface. The field limiting ring and the second surface are on the same side of the first surface, and both the field limiting ring and the second surface have a first orthographic projection in the first surface; a field plate is arranged on the field limiting ring, and part of the field plate is located on the second surface and in contact with the field limiting ring. The field plate has a second orthographic projection on the first surface, and the second orthographic projection covers at least one first orthographic projection. By making the first orthographic projection located in the second orthographic projection, the electric field can be blocked from passing through the field plate to reach the field limiting ring, thereby shielding at least the electric field of one field limiting ring. If the width of the field limiting ring is much larger than its depth or the length scale related to the charge distribution, electric field concentration may be formed at the edge of the field limiting ring, and it is easily broken down by the electric field. The present application shields at least the electric field of one field limiting ring, so that the field limiting ring will not be affected by the electric field. Furthermore, the width of the field limiting ring can be made wider. The wider width of the field limiting ring can make the dispersion space of the charge in the field limiting ring larger, and the distribution is more dispersed and will not be concentrated in one area, reducing the electric field peak, and thus improving the breakdown voltage resistance of the terminal structure. This terminal structure solves the problem of insufficient breakdown voltage resistance of SiC MOSFETs in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The accompanying drawings forming a part of this application are used to provide a further understanding of the application. The schematic embodiments and descriptions thereof of the application are used to explain the application and do not constitute an improper limitation to the application. In the drawings:
[0017] Figure 1 shows a schematic cross-sectional structure diagram of a terminal structure provided by an embodiment of the present application;
[0018] Figure 2 shows a schematic cross-sectional structure diagram of another terminal structure provided by an embodiment of the present application;
[0019] Figure 3 shows a schematic cross-sectional structure diagram of yet another terminal structure provided by an embodiment of the present application;
[0020] Figure 4 shows a schematic perspective structure diagram of a field limiting ring structure in a terminal structure provided by an embodiment of the present application;
[0021] Figure 5 shows a schematic perspective structure diagram of a field limiting ring structure in another terminal structure provided by an embodiment of the present application.
[0022] Among them, the above-mentioned drawings include the following reference numerals:
[0023] 10. Substrate; 11. Substrate; 12. Drift layer; 20. Field limiting ring; 30. Field plate; 31. First conductive layer; 32. Second conductive layer; 33. Passivation layer; 40. Field oxide layer; 50. Alignment mark; 60. Back electrode. Detailed implementation manners
[0024] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs.
[0025] It should be noted that the terms used herein are only for describing specific implementation manners and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular forms are also intended to include the plural forms. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they specify the presence of features, steps, operations, devices, components, and / or combinations thereof.
[0026] It should be noted that the terms "first", "second", etc. in the description and claims of the present utility model are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present utility model described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily limit to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.
[0027] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element can be directly on the other element or there can also be an intermediate element. Moreover, in the description and claims, when an element is described as "connected" to another element, the element can be "directly connected" to the other element or "connected" to the other element through a third element.
[0028] As introduced in the background art, as a representative of SiC devices, SiC MOSFETs in the prior art have many excellent characteristics such as low on-state loss, fast switching speed, and high operating frequency, and have gradually been popularized and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible DC transmission. However, this device still needs to challenge some extreme environments, such as being used in a high-voltage environment. Therefore, it is necessary to improve the breakdown voltage capability of SiC devices. To solve the problem of insufficient breakdown voltage capability of SiC MOSFETs in the prior art, embodiments of the present application provide a terminal structure and a semiconductor device.
[0029] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.
[0030] According to one aspect of the present application, a terminal structure is provided, as Figures 1 to 3 shown, including: a substrate 10 having opposite first and second surfaces; a plurality of field limiting rings 20 spaced apart in the substrate 10, the field limiting rings 20 having a third surface on the side of the first surface close to the second surface, the field limiting rings 20 and the second surface being on the same side of the first surface, and both the field limiting rings 20 and the second surface having a first orthographic projection in the first surface; a field plate 30, a part of the field plate 30 being located on the second surface and in contact with the field limiting rings 20, the field plate 30 having a second orthographic projection on the first surface, and the second orthographic projection covering at least one first orthographic projection.
[0031] By arranging a plurality of field limiting rings in the substrate of the terminal structure, the field limiting rings have a third surface located on one side of the first surface close to the second surface. The field limiting rings and the second surface are on the same side of the first surface, and both the field limiting rings and the second surface have a first orthographic projection in the first surface. A field plate is arranged on the field limiting rings, and a part of the field plate is located on the second surface and in contact with the field limiting rings. The field plate has a second orthographic projection on the first surface, and the second orthographic projection covers at least one first orthographic projection, that is, it can make the first orthographic projection located in the second orthographic projection. In the thickness direction of the terminal structure, at least one complete field limiting ring is located on the side of the field plate close to the substrate, so as to prevent the electric field from passing through the field plate to reach the field limiting ring, and thus at least shield the electric field of one field limiting ring. If the width of the field limiting ring is much larger than its depth or the length scale related to the charge distribution, an electric field concentration may be formed at the edge of the field limiting ring, which is easily broken down by the electric field. The present application shields the electric field of at least one field limiting ring, so that the field limiting ring will not be affected by the electric field. Furthermore, the width of the field limiting ring can be made wider. The wider width of the field limiting ring can make the dispersion space of charges in the field limiting ring larger, and the distribution is more dispersed, without concentrating in one area, reducing the electric field peak, and thus improving the breakdown voltage capability of the terminal structure. This terminal structure solves the problem of insufficient breakdown voltage capability of SiC MOSFETs in the prior art.
[0032] In some alternative embodiments, as Figures 1 to 3 shown, the above-mentioned substrate 10 includes a substrate 11 and a drift layer 12. The above-mentioned drift layer 12 is located on one side of the substrate 11. The above-mentioned field limiting ring 20 is located in the drift layer 12. The surface of the substrate 11 facing away from the drift layer 12 is the first surface, and the surface of the drift layer 12 facing away from the substrate 11 is the second surface. The doping type of the substrate 11 is the same as that of the drift layer 12. The doping type of the substrate 11 can be N-type, and the doping type of the drift layer 12 can be N-type. A buffer layer (not shown in the figure) can also be arranged between the substrate 11 and the drift layer 12, and the doping type of the buffer layer is consistent with that of the drift layer 12. The materials of the substrate 11 and the drift layer 12 can be any one or more of silicon carbide, silicon and silicon nitride.
[0033] Specifically, as Figure 1As shown, the above-mentioned field limiting ring 20 is distributed in the substrate 10 at intervals along the first direction Y, and the field limiting ring 20 extends along the second direction A. The field limiting ring 20 can be composed of a highly doped semiconductor material. For example, in a substrate of SiC material, an N-type doping material (such as phosphorus, arsenic) is doped, or in a substrate of silicon material, a P-type doping material (such as boron) is doped. A potential difference can be formed between the field limiting ring 20 and the drift layer 12 of the device. The formation of the field limiting ring 20 can adopt two steps of ion implantation and high-temperature annealing. First, the area of the field limiting ring 20 is defined on the substrate 10 through photolithography technology, then a highly doped material is implanted into the defined area of the field limiting ring 20 by an ion implantation process, and finally, the doped material is diffused through high-temperature heat treatment to form a field limiting ring 20 with higher conductivity.
[0034] In high-voltage applications, the field limiting ring can attract and store some charges, thereby reducing the electric field strength in the drift layer of the terminal structure. The doping type of the field limiting ring is opposite to that of the drift layer. The doping type of the field limiting ring is P-type, and the doping concentration can be 10 18 cm -3 ~10 20 cm -3 . As Figure 4 shown, the shape of the field limiting ring 20 can be a strip shape. As Figure 5 shown, the shape of the field limiting ring 20 can be an intermittent strip shape, where the first direction Y and the second direction A are respectively the same as the first direction Y and the second direction A shown in Figure 1 . The shape of the field limiting ring 20 can also be one or a combination of a square, a regular hexagon (not shown in the figure), and the present application does not make specific limitations.
[0035] In high-voltage devices, the non-uniform distribution of the electric field strength is the main cause of electric breakdown. As Figure 2 shown, except for the field limiting ring 20 whose projection is located in the projection of the field plate 30, the width of the remaining field limiting rings 20 gradually increases along the first direction Y. By gradually increasing the spacing between the field limiting rings 20 and the width of the above-mentioned field limiting rings 20, the smooth transition of the electric field strength from the active region to the terminal region can be more effectively controlled. When widening the width of the field limiting ring 20, it is necessary to consider whether it can withstand the electric field, and the width is smaller than that of the field limiting ring 20 whose projection is located in the projection of the field plate 30. Compared with the field limiting ring 20 before widening, a wider field limiting ring 20 can store more charges, make the charges more evenly distributed in a larger area, avoid the excessive concentration of charges at a certain point, which can reduce the peak value of the electric field strength in the terminal structure and improve the breakdown voltage resistance of the device terminal structure. Compared with the spacing between the field limiting rings 20 before increasing, a larger spacing between adjacent field limiting rings 20 helps to disperse and weaken the electric field, avoid the formation of an electric field peak at the edge of the terminal structure, thereby reducing the possibility of breakdown, and thus improving the breakdown voltage resistance of the device terminal structure.
[0036] In some alternative embodiments, such as Figures 1 to 3 shown, the above terminal structure further includes a field oxide layer 40, and the field oxide layer 40 covers the substrate 10 located between adjacent field limit rings 20 and part of the field limit rings 20. The material of the field oxide layer 40 can be one or a combination of SiO2 and SiN. The field oxide layer 40 can be prepared by wet oxidation (formed in a high-temperature water vapor environment), dry oxidation (in a high-temperature environment of oxygen or water vapor, but without a liquid medium), local oxidation process or deposition process. In SiC devices, a field oxide layer 40 made of a silicon nitride material can also be formed by a Chemical Vapor Deposition (CVD) process.
[0037] Specifically, the field oxide layer can effectively control the electric field distribution in the terminal region and prevent electric breakdown caused by over-concentration of the electric field under high voltage. The thickness and dielectric constant of the field oxide layer (different materials have different dielectric constants) can adjust the electric field strength of the drift layer, thereby further improving the breakdown voltage of the device. The present application does not make specific limitations on the thickness of the field oxide layer and the selection of materials.
[0038] Specifically, the structure between the field plate and the field oxide layer can form a parallel-plate capacitor. The field plate serves as the upper electrode, the charge distribution in the field limit ring and the drift layer under the field oxide layer serves as the lower electrode, and the intermediate field oxide layer serves as the insulating medium. When a voltage is applied between the field plate and the semiconductor layer (field limit ring and drift layer), the electric field in the field oxide layer will produce a capacitance effect. This capacitance helps to disperse charges under high voltage, make the charge distribution more uniform, and thus reduce the maximum electric field strength. By adjusting the thickness of the field oxide layer and the layout of the field plate, the capacitance effect can be optimized and the breakdown voltage of the device can be increased. The present application does not make specific limitations on the thickness of the field plate and the selection of materials.
[0039] In some alternative embodiments, such as Figures 1 to 3 shown, the above field plate 30 includes a first conductive layer 31 and a second conductive layer 32, wherein: the first conductive layer 31 covers the second surface, part of the third surface and part of the field oxide layer 40; the second conductive layer 32 covers the first conductive layer 31. The first conductive layer 31 can form a good ohmic contact with the field limit ring 20 to reduce the contact resistance of the device, increase the current density and the conductivity of the device. The second conductive layer 32 is used to increase the thickness of the field plate 30 covering the field limit ring 20 to improve the mechanical strength of the field plate 30 to withstand the electric field and ensure that the field plate 30 does not deform, break or melt under high current density. In addition, the second conductive layer 32 can also be part of the heat dissipation path to help the device dissipate heat during operation.
[0040] In some embodiments, the material of the first conductive layer may be a combination of one or more of Ti (titanium), Ni (nickel), Al (aluminum), and Cu (copper). The material of the second conductive layer may be a metal with high conductivity, such as Al (aluminum), Cu (copper), etc. The first conductive layer and the second conductive layer can be deposited on the first conductive layer by techniques such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition, sputtering process, or electroplating, and then the required pattern can be formed through photolithography and etching processes. The first conductive layer of the above type can provide low-resistance contact with the semiconductor material, enabling current to flow into or out of the device efficiently. The second conductive layer of the above type can enhance the current transmission ability of the device, reduce the resistive heating effect at high current density, and at the same time can also serve as part of the heat dissipation path to improve the heat dissipation of the device.
[0041] In some alternative embodiments, such as Figures 1 to 3 shown, the portion of the substrate 10 located between adjacent field limit rings 20 protrudes above the field limit rings 20. The field limit rings 20 are formed in the drift layer 12 by implantation through the bottom of the microgroove structure, which can make the field limit rings 20 located at a deeper position in the drift layer 12, interact more effectively with the charges in the drift layer 12, and better control the charge distribution from the active region to the terminal region. The greater depth of the position of the field limit rings 20 in the drift layer 12 can enable the field limit rings 20 to have a larger volume to store charges, and can also increase the diffusion region of the charges, thereby more evenly dispersing the electric field, avoiding the formation of electric field spikes, and further improving the breakdown voltage capability of the terminal structure. And when the implantation dose of the field limit ring 20 material is the same, forming a microgroove first in the terminal structure and implanting through the microgroove into the drift layer 12 will make the field limit rings 20 located at a deeper position in the drift layer 12, reducing the process difficulty of forming the field limit rings 20 at a deeper position in the drift layer 12, and can further improve the breakdown voltage capability of the terminal structure.
[0042] In some alternative embodiments, such as Figure 3 shown, the vertical distance H1 between the third surface and the second surface is 0.01 μm to 5 μm, and the width H2 of the third surface in the first direction Y is 0.1 μm to 10 μm, where the first direction Y is the arrangement direction of the plurality of field limit rings 20. Limiting the width of the field limit rings 20 within the above range can balance the simplicity of the process and good breakdown voltage capability. Setting the depth of the microgroove (the groove depth is a micron-level groove) within the above range can better implant into the drift layer 12 to form deeper field limit rings 20.
[0043] In the above alternative embodiments, such as Figures 1 to 3As shown, the terminal structure further includes a passivation layer 33. The passivation layer 33 covers the second conductive layer 32 and the field oxide layer 40, and the passivation layer 33 is used to protect the terminal structure. The material of the passivation layer 33 can be one or a combination of SiO2, SiNx, and polyimide, without specific limitation.
[0044] In some alternative embodiments, as Figures 1 to 3 shown, the above terminal structure further includes an alignment mark 50. The above alignment mark 50 is located in the edge region of the above terminal structure, and the above alignment mark 50 is recessed into the above drift layer 12 in the direction from the above drift layer 12 pointing to the above substrate 11. The above micro-groove structure and the alignment mark 50 can be etched simultaneously. Without adding an etching process, a marking etching process is used to form the alignment mark 50 and the micro-groove structure simultaneously, simplifying the manufacturing process of the terminal structure.
[0045] During the process of manufacturing the terminal structure, a photolithography process using multiple mask plates will be used. The alignment mark can be used to ensure the precise alignment of the subsequent photolithography layer with the previous layer pattern. By accurately reading and identifying the alignment mark, the lithography machine can ensure the alignment of patterns in different layers with an accuracy at the micron or even nanometer level. By measuring the position deviation of the alignment mark, the alignment accuracy problem of the lithography machine can be detected and adjusted in a timely manner, avoiding the reduction of the yield rate and product performance problems caused by inaccurate alignment.
[0046] In some alternative embodiments, as Figures 1 to 3 shown, the above field oxide layer 40 and the above field plate 30 have partial overlap. The width H3 of the composite region between the field plate 30 and the field oxide layer 40 can be 0 μm to 100 μm. Among them, overlapping the field plate 30 and the field oxide layer 40 can shield more electric fields, making the width of the first field limiting ring 20 larger. For example, when there is no overlap between the field plate 30 and the field oxide layer 40, the width of the field limiting ring 20 can be 0.8 μm in the presence of an electric field. When there is an overlap between the field plate 30 and the field oxide layer 40, the width of the field limiting ring 20 can be greater than 1 μm. The widening of the width of the field limiting ring 20 can make the dispersion space of charges in the field limiting ring larger, and the distribution is more dispersed, not concentrated in one area, reducing the electric field peak value, and thus improving the breakdown voltage ability of the terminal structure. The widening of the width of the field limiting ring 20 can also improve the redundancy of the manufacturing process and reduce the difficulty of the manufacturing process.
[0047] In some alternative embodiments, as Figures 1 to 3As shown, the above terminal structure further includes a back electrode 60, and the back electrode 60 is located on the first surface. The material of the back electrode 60 can be one or more of Cu, Ag, and Al, and the present application does not make specific limitations. The preparation process of the back electrode 60 can include thinning the wafer, depositing a metal layer (which can be PVD process and sputtering) and annealing to improve the ohmic contact. The present application does not make specific limitations on the preparation process of the back electrode 60.
[0048] According to another aspect of the present application, a semiconductor device is provided, including the above terminal structure.
[0049] In the semiconductor device provided in the embodiment of the present application, since the above terminal structure is included, a plurality of field limiting rings are provided in the substrate of the terminal structure. The field limiting rings have a third surface located on one side of the first surface close to the second surface. The field limiting rings and the second surface are on the same side of the first surface, and both the field limiting rings and the second surface have a first orthographic projection in the first surface. A field plate is provided on the field limiting rings, and part of the field plate is located on the second surface and is in contact with the field limiting rings. The field plate has a second orthographic projection on the first surface, and the second orthographic projection covers at least one first orthographic projection, that is, the first orthographic projection can be located in the second orthographic projection. In the thickness direction of the terminal structure, at least one complete field limiting ring is located on the side of the field plate close to the substrate, so that the electric field can be blocked from passing through the field plate to reach the field limiting ring, and thus at least one field limiting ring's electric field is shielded. If the width of the field limiting ring is much larger than its depth or the length scale related to the charge distribution, an electric field concentration may be formed at the edge of the field limiting ring, which is easily broken down by the electric field. The present application shields at least one field limiting ring's electric field, so that the field limiting ring will not be affected by the electric field. Furthermore, the width of the field limiting ring can be made wider. Making the width of the field limiting ring wider can make the dispersion space of charges in the field limiting ring larger, and the distribution is more dispersed, not concentrated in one area, reducing the electric field peak, and thus improving the breakdown voltage ability of the terminal structure. This terminal structure solves the problem of insufficient breakdown voltage ability of SiC MOSFETs in the prior art.
[0050] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the preparation method of the terminal structure of the present application will be described in detail below in combination with specific embodiments.
[0051] This embodiment relates to a specific preparation method of a terminal structure, including the following steps:
[0052] Step S1: Provide a substrate, the substrate includes a substrate and a drift layer. The substrate is a 6-inch SiC material with a thickness of 350 μm, and the material of the drift layer is SiC with a doping type of N-type;
[0053] Step S2: Use a mask to prepare a SiO2 mask on the drift layer, and form alignment marks and micro-groove structures by photolithography or dry etching processes;
[0054] Step S3: Perform high-temperature P-type ion implantation in the micro-groove structures to form field limiting ring structures;
[0055] Step S4: Generate a field oxide layer on a part of the field limiting ring structures, and form a first conductive layer on another part of the field limiting ring structures. The first conductive layer covers part of the field oxide layer. The material of the field oxide layer is silicon dioxide, and the material of the first conductive layer is Ti;
[0056] Step S5: Form a second conductive layer on the first conductive layer. The second conductive layer covers the first conductive layer, and the material of the second conductive layer is Ti;
[0057] Step S6: Cover a passivation layer on the second conductive layer and the field oxide layer. The material of the passivation layer is silicon dioxide;
[0058] Step S7: Form a back electrode on the side of the substrate facing away from the drift layer. The material of the back electrode is Al.
[0059] Next, the above terminal structure of the present application will be specifically described in conjunction with specific embodiments.
[0060] Embodiment 1
[0061] The terminal structure provided in this embodiment includes:
[0062] A substrate having opposite first and second surfaces. The substrate includes an N-type substrate and an N-type drift layer. The above drift layer is located on one side of the above substrate. The surface of the above drift layer facing away from the above substrate is the above first surface. The material of the substrate is silicon carbide;
[0063] A plurality of P-type field limiting rings are spaced in the above drift layer. The above field limiting rings have a third surface located on the side of the above first surface close to the above second surface. The above field limiting rings and the above second surface are located on the same side of the above first surface, and both the above field limiting rings and the above second surface have a first orthographic projection in the above first surface. The distance between adjacent field limiting rings is equal;
[0064] A field oxide layer. The above field oxide layer covers the substrate between adjacent field limiting rings and part of the above field limiting rings. The material is silicon dioxide;
[0065] A field plate. Part of the above field plate is located on the above second surface and is in contact with the above field limiting rings. The above field plate has a second orthographic projection on the above first surface. The above second orthographic projection covers at least one first orthographic projection. The material of the field plate can be silicon dioxide. The widths of the field limiting rings not covered by the field plate are the same;
[0066] A first conductive layer and a second conductive layer, wherein: the first conductive layer covers the second surface, a part of the third surface, and a part of the field oxide layer; the second conductive layer covers the first conductive layer, and the materials of the first conductive layer and the second conductive layer can be Al;
[0067] A back electrode, the back electrode is located on the first surface, and the material of the back electrode can be Al;
[0068] Alignment marks, the alignment marks are located in the edge region of the terminal structure, and the alignment marks are recessed in the drift layer along the direction from the drift layer to the substrate.
[0069] Embodiment 2
[0070] The terminal structure provided in this embodiment includes:
[0071] A substrate having opposite first and second surfaces, the substrate includes an N-type substrate and an N-type drift layer, the drift layer is located on one side of the substrate, the surface of the drift layer facing away from the substrate is the first surface, and the material of the substrate is silicon carbide;
[0072] A plurality of P-type field limit rings are spaced in the drift layer, the field limit rings have a third surface on the side of the first surface close to the second surface, the field limit rings and the second surface are on the same side of the first surface, and both the field limit rings and the second surface have a first orthographic projection in the first surface, and the spacing between adjacent field limit rings increases along the direction from the active region to the terminal region;
[0073] A field oxide layer, the field oxide layer covers the substrate between adjacent field limit rings and a part of the field limit rings, and the material is silicon dioxide;
[0074] A field plate, a part of the field plate is located on the second surface and is in contact with the field limit ring, the field plate has a second orthographic projection on the first surface, the second orthographic projection covers at least one first orthographic projection, the material of the field plate can be silicon dioxide, and the width of the field limit ring not covered by the field plate increases along the direction from the active region to the terminal region;
[0075] A first conductive layer and a second conductive layer, wherein: the first conductive layer covers the second surface, a part of the third surface, and a part of the field oxide layer; the second conductive layer covers the first conductive layer, and the materials of the first conductive layer and the second conductive layer can be Al;
[0076] A back electrode, the back electrode is located on the first surface, and the material of the back electrode can be Al;
[0077] Alignment marks, which are located in the edge region of the above-mentioned terminal structure and are recessed into the drift layer along the direction in which the drift layer points to the substrate.
[0078] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects:
[0079] 1) In the terminal structure proposed in the present application, the first orthographic projection of the field limiting ring can be made to be located within the second orthographic projection of the field plate, which can prevent the electric field from passing through the field plate and reaching the field limiting ring, thereby shielding the electric field of at least one field limiting ring. If the width of the field limiting ring is much larger than its depth or the length scale related to the charge distribution, electric field concentration may be formed at the edge of the field limiting ring, making it easily broken down by the electric field. The present application shields the electric field of at least one field limiting ring, so that the field limiting ring will not be affected by the electric field. As a result, the width of the field limiting ring can be made wider. A wider field limiting ring can provide a larger dispersion space for charges in the field limiting ring, making the charges more dispersed and not concentrated in one area, reducing the electric field peak, and thus improving the breakdown voltage withstand capacity of the terminal structure.
[0080] 2) The field limiting ring of the terminal structure proposed in the present application is formed in the drift layer by implantation at the bottom of the microgroove structure, which can make the field limiting ring located at a deeper position in the drift layer. The field limiting ring can interact more effectively with the charges in the drift layer and better control the charge distribution from the active region to the terminal region. Forming the field limiting ring in the microgroove can also reduce the process difficulty of forming a field limiting ring at a deeper position in the drift layer, and can further improve the breakdown voltage withstand capacity of the terminal structure.
[0081] 3) The microgroove structure of the terminal structure proposed in the present application and the alignment marks can be etched simultaneously. Without adding an etching process, the alignment marks and the microgroove structure are formed simultaneously using the marking etching process, which simplifies the preparation process of the terminal structure.
[0082] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.
Claims
1. A terminal structure, characterized in that: include: a substrate having opposing first and second surfaces; A plurality of field limiting rings are spaced apart and disposed in the substrate, wherein the field limiting rings have a third surface disposed on a side of the first surface close to the second surface, the field limiting rings and the second surface are disposed on the same side of the first surface, and both the field limiting rings and the second surface have a first orthographic projection disposed in the first surface; A field plate, part of which is located on the second surface and in contact with the field limiting ring, and the field plate has a second orthographic projection on the first surface, and the second orthographic projection covers at least one first orthographic projection.
2. The terminal structure according to claim 1, characterized in that: A portion of the substrate located between adjacent field limiting rings protrudes from the field limiting rings.
3. The terminal structure according to claim 2, characterized in that: The vertical distance between the third surface and the second surface is 0.01 μm to 5 μm, the width of the third surface in a first direction is 0.1 μm to 10 μm, and the first direction is an arrangement direction of the plurality of field limiting rings.
4. The terminal structure according to claim 2, characterized in that: The terminal structure further includes a field oxide layer, and the field oxide layer covers the substrate between adjacent field limiting rings and a portion of the field limiting rings.
5. The terminal structure according to claim 4, characterized in that: The field plate comprises a first conductive layer and a second conductive layer, wherein: The first conductive layer covers the second surface, a portion of the third surface and a portion of the field oxide layer; The second conductive layer covers the first conductive layer.
6. The terminal structure according to claim 1, characterized in that: The base comprises a substrate and a drift layer, wherein the drift layer is located on one side of the substrate, the field limiting ring is located in the drift layer, and a surface of the drift layer facing away from the substrate is the first surface.
7. The terminal structure according to claim 6, characterized in that: The terminal structure further includes an alignment mark, which is located at an edge region of the terminal structure and is recessed in the drift layer along a direction from the drift layer to the substrate.
8. The terminal structure according to claim 4, characterized in that: The field oxide layer partially overlaps with the field plate.
9. The terminal structure according to claim 1, characterized in that: The terminal structure further includes a back electrode located on the first surface.
10. A semiconductor device, characterized in that: The invention comprises the terminal structure according to any one of claims 1 to 9.