Image sensor

Abstract

The embodiment of the utility model provides an image sensor. The image sensor comprises a substrate having a first side and a second side opposite to the first side, a photoelectric detector area in the substrate, and a gate structure on the first side of the substrate above the photoelectric detector area. A deep trench isolation structure surrounding the photodetector region and extending from the first side to the second side of the substrate, a doped floating node region within the substrate at the first side and disposed between the gate structure and the deep trench isolation structure; and a floating node on the first side of the substrate and contacting a top surface of the deep trench isolation structure and overlying the doped floating node region. The image sensor has isolation of a separate floating node design, while having loose layout requirements of a common floating node design.

Description

Technical Field

[0001] An embodiment of the present utility model relates to an image sensor, and particularly to an image sensor including a deep trench isolation structure. Background Art

[0002] Many modern electronic devices include image sensors. The image sensor has a photodetector, a transfer gate, and a floating node. The transfer gate is configured to form a conductive path between the photodetector and the floating node, causing the charge in the photodetector to be transferred to the image processing circuit through the floating node. The photodetectors are usually spaced apart from each other by a deep trench isolation structure. Summary of the Utility Model

[0003] An embodiment of the present utility model provides an image sensor including a substrate having a first side and a second side opposite to the first side, a photodetector within the substrate, a gate structure on the first side of the substrate above the photodetector, a deep trench isolation structure surrounding the photodetector and extending from the first side of the substrate to the second side, a doped floating node region within the substrate on the first side and disposed between the gate structure and the deep trench isolation structure, and a floating node on the first side of the substrate, the floating node contacting the top surface of the deep trench isolation structure and overlying the doped floating node region.

[0004] An embodiment of the present utility model provides an image sensor including a substrate having a first side and a second side opposite to the first side, a plurality of photodetectors within the substrate, a plurality of gate structures on the first side of the substrate overlying the photodetectors, a deep trench isolation structure including a plurality of sections surrounding the photodetectors in a grid pattern to isolate the photodetectors from each other, and a floating node, the sections intersecting at intersection points, the floating node extending at the intersection points within the grid pattern of the deep trench isolation structure and between the gate structures, wherein the floating node extends beyond the outer sidewalls of the sections at the intersection points.

[0005] Based on the above, the image sensor has a deep trench isolation structure extending through the substrate and a common floating node overlying the deep trench isolation structure. The image sensor has a front-side deep trench isolation structure with a sealing layer partially extending into the substrate and a back-side deep trench isolation structure below the front-side deep trench isolation structure, the floating node being above the front-side deep trench isolation structure and extending above the sidewalls of the front-side deep trench isolation structure to be coupled to a unit of the image sensor. The image sensor has a deep trench isolation structure extending from the lower surface of the floating node to the second surface of the substrate, increasing the isolation of the photodetectors while maintaining a common floating node.

[0006] To make the above features and advantages of the embodiments of the present utility model more obvious and understandable, the following specifically gives embodiments and makes a detailed description in conjunction with the accompanying drawings as follows. Description of the Drawings

[0007] Figure 1 A cross-sectional view showing some embodiments of an image sensor having a deep trench isolation (DTI) structure extending through a substrate.

[0008] Figure 2A - 2B A cross-sectional view and a top view showing some embodiments of an image sensor having a DTI structure extending through a substrate and a common floating node covering the DTI structure.

[0009] Figure 3A - 3E A cross-sectional view showing some embodiments of an image sensor having a DTI structure extending through a substrate in various configurations.

[0010] Figures 4 - 19 A cross-sectional view showing some embodiments of a method of forming an image sensor having a DTI structure extending through a substrate, wherein the backside DTI structure has the same width as the frontside DTI structure.

[0011] Figures 20 - 34 A cross-sectional view showing some embodiments of a method of forming an image sensor having a DTI structure extending through a substrate, wherein the backside DTI structure has a smaller width than the frontside DTI structure.

[0012] Figure 35 A flowchart showing some embodiments of a method of forming an integrated chip having an image sensor, the image sensor having a DTI structure extending through a substrate.

[0013] Description of the Reference Numerals

[0014] 100, 200a, 300a, 300a - 300e, 300b, 300c, 300d, 300e, 400, 500, 600, 600 - 700, 700, 800, 900, 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100, 3200, 3300, 3400: Cross-sectional view; 102: Substrate; 102a: First side; 102b: Second side; 104: Deep trench isolation (DTI) structure; 106: Photoelectric detector; 108: Transfer gate; 110: Floating node; 110p, 136p: Protrusion; 112: Floating node region; 114: Contact; 116: Interconnection structure; 118: Dielectric; 120: Conductive gate; 122: Gate dielectric; 124: Front-side DTI structure; 126: Back-side DTI structure; 128: First insulating core; 130: Sealing layer; 132: Insulating layer; 134: Second insulating core; 136: High-k layer; 138: Insulating base; 200b: Top view; 202: First unit; 204: Second unit; 302: Second insulating layer; 304: Charge carrier; 402: First etching process; 404: First mask layer; 406: First nitride layer; 408: First hard mask layer; 410: First trench; 602: First conformal oxide layer; 702: First sacrificial core; 802: Second etching process; 804: First opening; 1002: Conformal sealing layer; 1102, 2602: Wet etching process; 1104: Notch; 1202: First implantation process; 1204: Second mask layer; 1602: Second implantation process; 1604: Third mask layer; 1702, 3202: Etching process; 1704: Second trench; 2002: Fourth etching process; 2004: Fourth mask layer; 2006: Third trench; 2102: Conformal nitride layer; 2202, 2402: Fifth etching process; 2204, 2206: Portion; 2208: Fourth trench; 2302: Second sacrificial core; 2404: Second opening; 2406: Second conformal sealing layer; 2604: Notch; 2702: Third implantation process; 2704: Fifth mask layer; 3102: Fourth implantation process; 3104: Sixth mask layer; 3204: Fifth trench; 3500: Method; 3502, 3504, 3506, 3508, 3510, 3512, 3514, 3516, 3518, 3520: Action; A - A': Line. Detailed implementation

[0015] The following disclosure provides a number of different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, the formation of a first feature "on" or "above" a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features are formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clearly describing the present disclosure and is not intended to define the relationship between various embodiments and / or configurations.

[0016] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship of one component or feature shown in the figures to another (other) component or feature. In addition to the orientation depicted in the figures, the spatially relative terms also encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used may be interpreted in the same manner.

[0017] An image sensor may include a plurality of photodetectors in a substrate. The photodetectors are arranged in a grid pattern within the openings of a deep trench isolation (DTI) structure. A transfer gate covers the photodetectors on a first side of the substrate. Operation of the transfer gate causes charge to transfer from the photodetectors to a floating node, where the charge is then transferred to an image processing circuit.

[0018] In some image sensors, the floating node may be separate for each photodetector, such that the photodetectors and the floating nodes are grouped together within the active region of the substrate that is laterally surrounded by the DTI structure. This arrangement increases the minimum layout requirements of the image sensor in order to mount the floating nodes and the photodetectors within the grid pattern. The separate floating nodes may also increase the capacitance of the floating nodes due to the increased number of contacts and the reduced conversion gain of the image sensor, resulting in a lower amount of charge transferred at a specified applied voltage.

[0019] When the floating node is at the midpoint between photodetectors, the floating node can also be shared among multiple photodetectors. This arrangement reduces the isolation of the photodetectors because the "fingers" of the DTI structure do not completely surround the photodetectors to make room for the floating node. Due to greater interference between the cells of the image sensor, this lack of isolation results in poorer optical performance of the photodetectors. Therefore, there is a need for an image sensor that has the isolation of a separate floating node design while having the relaxed layout requirements of a shared floating node design.

[0020] The present disclosure provides an image sensor having a DTI structure extending through a substrate and a shared floating node overlying the DTI structure. The DTI structure is formed by fabricating a front-side DTI structure having a sealing layer partially extending into the substrate. The floating node is formed over the front-side DTI structure, extending over the sidewalls of the front-side DTI structure to couple to the cells of the image sensor. After the front-side DTI structure and other front-side processes are completed, a back-side DTI structure is formed under the front-side DTI structure. The back-side DTI structure is formed using self-aligned etching to form a DTI structure extending through the substrate. The above process results in a DTI structure extending from the lower surface of the floating node to the second surface of the substrate, increasing the isolation of the photodetectors while maintaining the shared floating node.

[0021] Figure 1 A cross-sectional view 100 of some embodiments of an image sensor having a DTI structure extending through a substrate is shown.

[0022] A DTI structure 104 including a front-side DTI structure 124 and a back-side DTI structure 126 is disposed within a substrate 102. The DTI structure 104 surrounds a photodetector 106 within the substrate 102. A transfer gate 108 is on a first side 102a of the substrate and overlies the photodetector 106. In some embodiments, the transfer gate 108 extends into the substrate 102 toward the photodetector 106. A floating node 110 overlies the DTI structure 104 on the first side 102a of the substrate 102. The floating node 110 is conformal with the upper surface of the DTI structure 104 and is surrounded by a floating node region 112. The floating node region 112 is a doped region of a first doping type and the photodetector 106 is a doped region of a first doping type. In some embodiments, the transfer gate 108 is spaced apart from the floating node region 112 to reduce the amount of drain leakage caused by the gate. An interconnect structure 116 is coupled to the transfer gate 108 and the floating node 110 through a contact 114.

[0023] The front - side DTI structure 124 includes a first insulating core 128 surrounded by a sealing layer 130 and an insulating layer 132. In some embodiments, the first insulating core 128 is or includes an oxide (such as silicon dioxide (SiO2)) and the like. In some embodiments, the insulating layer 132 is or includes an oxide (such as silicon dioxide (SiO2)) and the like. The sealing layer 130 extends under the first insulating core 128, separating the first insulating core 128 from the back - side DTI structure 126. The sealing layer 130 has a U - shaped cross - section. The insulating layer 132 surrounds the outer sidewall of the sealing layer 130 and extends over the first side 102a of the substrate 102. In some embodiments, the portion of the insulating layer 132 that extends over the first side 102a of the substrate is separated from the portion of the insulating layer 132 that surrounds the outer sidewall of the sealing layer 130.

[0024] The back - side DTI structure 126 includes a second insulating core 134 surrounded by a high - dielectric - constant layer 136. The high - dielectric - constant layer 136 extends over the second insulating core 134, separating the second insulating core from the front - side DTI structure 124. The high - dielectric - constant layer 136 extends across the second side 102b of the substrate 102. The second insulating core 134 extends from an insulating base portion 138. The insulating base portion 138 is separated from the substrate 102 by the high - dielectric - constant layer 136. The insulating base portion protects the high - dielectric - constant layer 136 from damage. The combination of the back - side DTI structure 126 that extends from the front - side DTI structure 124 to the second side 102b of the substrate and the front - side DTI structure 124 that extends from the floating node 110 to the back - side DTI structure results in an image sensor having higher isolation, yet still being able to utilize a shared floating node.

[0025] Figure 2A - 2B Cross - sectional views 200a and top - plan views 200b of some embodiments of an image sensor are shown, the image sensor having DTI structures extending through a substrate and a shared floating node overlying the DTI structures. Figure 2A The cross - sectional view 200a can be taken, for example, along Figure 2B line A - A' in

[0026] The floating node 110 is electrically coupled to the floating node region 112, and the floating node region 112 extends into the first unit 202 and the second unit 204 of the image sensor. The floating node region 112 is configured to conduct charge from one of the photodetectors 106 to the floating node 110 when the corresponding transfer gate 108 is biased. The DTI structure 104 extending from the floating node 110 to the second side 102b of the substrate 102 increases the isolation between the photodetectors, thereby increasing the optical efficiency of the image sensor. In addition, compared with related image sensors, using one floating node 110 for multiple photodetectors 106 reduces the total number of contacts on the image sensor, reduces the capacitance of the floating node 110, and increases the conversion gain (e.g., the amount of charge transferred using the applied specified voltage).

[0027] As Figure 2B shown in the top view 200b, four photodetectors 106 can be positioned around one floating node 110. The floating node region 112 extends into four independent units of the image sensor, such that the four photodetectors 106 can transfer their charge through the floating node 110 during a single readout operation. The DTI structure 104 further extends all the way to the floating node 110, completely isolating the photodetectors 106 from each other.

[0028] Figure 3A - 3E Cross-sectional views 300a - 300e of some embodiments of an image sensor having a DTI structure extending through the substrate in various configurations are shown.

[0029] As Figure 3A shown in the cross-sectional view 300a, in some embodiments, the backside DTI structure 126 extends above the bottom surface of the frontside DTI structure 124. In some embodiments, the portion of the backside DTI structure 126 at the same height as the frontside DTI structure 124 has a greater width than the portion of the backside DTI structure 126 below the bottom surface of the frontside DTI structure 124. In some embodiments, the width of the frontside DTI structure 124 is greater than that of the backside DTI structure 126. In additional embodiments, the first insulating core 128 may have a greater width than the second insulating core 134. In some embodiments, the frontside DTI structure 124 further includes a second insulating layer 302 that surrounds the sealing layer 130 and spaces the sealing layer 130 from the insulating layer 132. In some embodiments, the second insulating layer 302 is or includes a nitride (e.g., silicon nitride (Si3N4)) and the like. In some embodiments, the floating node region 112 extends below the bottom surface of the frontside DTI structure 124. In some embodiments, the high-k dielectric layer 136 extends around the sidewalls and the bottom surface of the second insulating layer 302 and has a protrusion 136p that extends towards and contacts the insulating layer 132.

[0030] The front - side DTI structure 124 has a notch that is above the sealing layer 130, the second insulating layer 302, and the insulating layer 132. The notch extends around the sidewall of the front - side DTI structure 124 in a square pattern. The first insulating core 128 has a flat upper surface that extends between the notches. The floating node 110 has a protrusion 110p that extends into the front - side DTI structure 124 to fill the notch. In some embodiments, the floating node 110 contacts the substrate 102. In other embodiments, a thin portion of the insulating layer 132 extends between the floating node 110 and the substrate 102. In some embodiments, the top surface of the back - side DTI structure 126 extends to a first height measured from the second side 102b of the substrate 102, and the bottom surface of the front - side DTI structure 124 extends to a second height measured from the second side 102b of the substrate 102, where the second height is greater than the first height.

[0031] As Figure 3B Shown in cross - sectional view 300b, in some embodiments, the front - side DTI structure 124 has the same width as the back - side DTI structure 126. In additional embodiments, the second insulating core 134 may have a greater width than the first insulating core 128. In some embodiments, the high - dielectric - constant layer 136 has a protrusion 136p that extends upward to the outer sidewall of the sealing layer 130. The protrusion extends away from the second side 102b of the substrate 102 and has a topmost surface that contacts the insulating layer 132. In some embodiments, the DTI structure 104 is tapered, having a greater width near the first side 102a of the substrate 102 and a smaller width near the second side 102b of the substrate 102.

[0032] As Figure 3C Shown in cross - sectional view 300c, in some embodiments, the portion of the sealing layer 130 directly below the floating node 110 may extend into the substrate 102 to a different depth than the portions of the sealing layer 130 and the first insulating core 128 that are spaced apart from the floating node 110. In some embodiments, the upper surfaces of the sealing layer 130 and the insulating layer 132 that are spaced from the floating node 110 may be substantially flush with the first side 102a of the substrate 102. In additional embodiments, the portion of the first insulating core 128 that is spaced from the floating node 110 may extend above the first side 102a of the substrate 102. Additionally, the portions of the first insulating core 128 and the sealing layer 130 directly below the floating node 110 are pressed into the first side 102a of the substrate 102. In some embodiments, the floating node 110 has a protrusion that extends from the lower side of the floating node 110, and the lower side covers the upper surface of the first insulating core 128. That is, the upper surface of the first insulating core is below the upper surface of the sealing layer 130.

[0033] As Figure 3DAs shown in the cross-sectional view 300d, in some embodiments, the insulating layer 132 may be recessed from the first side of the substrate 102, while the first insulating core 128 may extend above the substrate 102. In additional embodiments, the floating node 110 may extend into the substrate 102 to contact the insulating layer 132 and extend above the first insulating core 128 to extend beyond the opposite side of the front-side DTI structure 124.

[0034] As Figure 3E shown in the cross-sectional view 300e, the interface between the substrate 102 and the high-k dielectric layer 136 may have a texture. During the process of forming the back-side DTI structure 126, a multi-step etching process is performed on the substrate 102, which includes dry plasma etching and wet etching. The etching process may damage the substrate 102 and introduce charge traps and stray charge carriers 304 at the surface near the substrate 102. The charge traps and stray charge carriers 304 at the interface with the back-side DTI structure 126 may increase the dark current in the image sensor. In some embodiments, the implantation processes for forming the floating node region (see Figure 1 112) and the photodetector (see Figure 1 106) may also damage the substrate 102 and introduce stray charge carriers 304. After the etching process and the implantation process, forming the high-k dielectric layer 136 may reduce the amount of charge trapping at the interface and attract charge carriers 304 from the substrate 102, thereby reducing the amount of dark current detected by the image sensor. In some embodiments, boron is incorporated into the high-k dielectric layer 136 at the interface between the substrate 102 and the high-k dielectric layer 136 to reduce the amount of dark current. In some embodiments, the high-k dielectric layer 136 is charged to accumulate charge carriers from the substrate 102. It should be understood that Figures 3C - 3E the features shown may be applicable to other embodiments described herein.

[0035] Figures 4 - 19 A cross-sectional view shows some embodiments of a method of forming an image sensor having a DTI structure extending through a substrate, where the back-side DTI structure has the same width as the front-side DTI structure. Although Figures 4 - 19 described with respect to one method, it should be understood that Figures 4 - 19 the structures disclosed in

[0036] As Figure 4As shown in the cross-sectional view 400, a substrate 102 is provided. An insulating layer 132 is formed on the substrate 102. In some embodiments, the insulating layer 132 is a thermal oxide. A first nitride layer 406 is formed above the insulating layer 132. A first hard mask layer 408 is formed above the first nitride layer 406. A first mask layer 404 is formed above the first nitride layer 406. In some embodiments, the first nitride layer 406 and the first hard mask layer 408 are formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other suitable deposition processes, or a combination of the foregoing. In some embodiments, the first mask layer 404 is a photoresist. In some embodiments, the first nitride layer 406 is or includes silicon nitride (Si3N4), etc. In some embodiments, the first hard mask layer 408 is or includes silicon oxide (SiO2), dense silicon dioxide, etc.

[0037] After the first mask layer 404 is formed, the first mask layer 404 is patterned to form an opening. In some embodiments, the first mask layer 404 is patterned using photolithography. Then a first etching process 402 is performed. During the execution of the first etching process 402, the first hard mask layer 408, the first nitride layer 406, the insulating layer 132, and the substrate 102 are etched in the regions exposed by the first mask layer 404. In some embodiments, the first etching process 402 can be a dry etching, such as plasma etching, etc. The first etching process 402 results in the formation of a first trench 410 in the substrate 102, and the first trench 410 is formed to correspond to the pattern of the opening of the first mask layer 404. The pattern is a grid pattern. Subsequently, the first mask layer 404 is removed.

[0038] As Figure 5 shown in the cross-sectional view 500, an oxide liner is formed on the surface of the first trench 410, and the insulating layer 132 extends along the surface of the trench. In some embodiments, the oxide liner is formed using a thermal process, a deposition process, or a combination of the foregoing.

[0039] As Figure 6 shown in the cross-sectional view 600, a first conformal oxide layer 602 is deposited in the first trench 410 (shown in dashed lines). The first conformal oxide layer 602 fills the first trench 410 and overlies the first hard mask layer 408. In some embodiments, the first conformal oxide layer 602 can be deposited using CVD, PVD, ALD, some other suitable deposition processes, or a combination of the foregoing.

[0040] As Figure 7As shown in the cross-sectional view 700, the first hard mask layer (see Figure 6 408) and a portion of the first conformal oxide layer (see Figure 6 602) that extends above the top surface of the first nitride layer 406 are removed. In some embodiments, a planarization process (e.g., a chemical mechanical planarization process) is used to remove the portion of the first conformal oxide layer (see Figure 6 602) and the first hard mask layer (see Figure 6 408). The removal process results in the first sacrificial core 702 remaining in the substrate 102.

[0041] As Figure 8 shown in the cross-sectional view 800, a portion of the first sacrificial core 702 and a portion of the insulating layer 132 are removed during the second etching process 802, leaving a first opening 804. In some embodiments, the etching process is a wet etching process configured to etch silicon dioxide (SiO2).

[0042] As Figure 9 shown in the cross-sectional view 900, a second oxide liner is formed over the exposed sidewalls of the substrate 102, and annealing is performed to reform the oxide layer between the first nitride layer 406 and the first sacrificial core 702.

[0043] As Figure 10 shown in the cross-sectional view 1000, a conformal seal layer 1002 is formed over the first nitride layer 406. In some embodiments, the conformal seal layer 1002 is or includes dense silicon dioxide (SiO2), silicon nitride, polysilicon, a silicon epitaxial layer, a combination of the foregoing, etc. The conformal seal layer 1002 is conformal with the first opening 804 and the first nitride layer 406. After forming the conformal seal layer 1002, a first insulating core 128 is formed over the conformal seal layer 1002. The first insulating core 128 is formed by depositing a conformal oxide layer over the substrate 102 and then removing a portion of the conformal oxide layer above the top surface of the conformal seal layer 1002 using a planarization process (e.g., a CMP process). In some embodiments, the first insulating core is or includes silicon dioxide (SiO2), etc.

[0044] As Figure 11 shown in the cross-sectional view 1100, a portion of the conformal seal layer (see Figure 10 1002) above the first side 102a of the substrate 102 is removed, and the first nitride layer (see Figure 10 406) is removed such that the seal layer 130 remains within the substrate 102. In some embodiments, one or more wet etching processes 1102 are used to remove the portion of the conformal seal layer (see Figure 10 1002) and the first nitride layer (see Figure 10406). That is, in some embodiments, the portion of the conformal seal layer (see Figure 10 1002) can be removed using a first wet etching process 130 that is selective to the material of the seal layer, and the first nitride layer (see Figure 10 406) can subsequently be removed using a second wet etching process with an etching chemical that is selective to silicon nitride. In some embodiments, where the seal layer 130 includes a nitride (e.g., silicon nitride (Si3N4)), the portion of the conformal seal layer (see Figure 10 1002) and the first nitride layer (see Figure 10 406) can be removed using a single wet etching process 1102. One or more wet etching processes 1102 result in notches 1104 being formed within the seal layer 130. The notches extend in a square pattern around the openings in the grid pattern of the seal layer 130. In some embodiments, the wet etching process 1102 for removing the portion of the conformal seal layer (see Figure 10 1002) and the first nitride layer (see Figure 10 406) also removes a portion of the insulating layer 132. In some embodiments, one or more wet etching processes 1102 expose a portion of the substrate 102 adjacent to the seal layer 130.

[0045] As Figure 12 shown in the cross-sectional view 1200, a second mask layer 1204 is formed over the substrate 102. In some embodiments, the second mask layer 1204 is a photoresist. Subsequently, the second mask layer 1204 is patterned to form openings therein corresponding to the positions of the floating node regions 112 to be formed subsequently. After patterning the second mask layer 1204, a first implantation process 1202 is performed to dope the substrate 102 corresponding to the pattern of the openings in the second mask layer 1204 to form the floating node regions 112. In some embodiments, the dopant is of a first doping type (e.g., n-type doping). In some embodiments, the dopant is implanted into the insulating layer 132 adjacent to the floating node regions 112. Subsequently, the second mask layer 1204 is removed.

[0046] As Figure 13As shown in the cross-sectional view 1300, the floating node 110 is formed on the substrate 102 above the floating node region 112. In some embodiments, the floating node 110 is formed using CVD, PVD, ALD, epitaxy, some other suitable deposition process, or a combination of the foregoing. The floating node 110 is or includes polysilicon, epitaxial silicon, metal, another conductive material, or a combination of the foregoing. Prior to forming the floating node 110, a portion of the insulating layer 132 covering the substrate 102 is removed. In some embodiments, prior to forming the floating node 110 and the floating node region 112, a portion of the insulating layer 132 covering the substrate 102 is removed. Thus, the floating node directly contacts the first side 102a of the substrate 102 and the floating node region 112.

[0047] As Figure 14 shown in the cross-sectional view 1400, a transfer gate 108 is formed on the first side 102a of the substrate 102. Forming the transfer gate 108 includes forming a gate dielectric 122 using one or more dry etching and deposition steps and forming a conductive gate 120 above the gate dielectric using one or more dry etching and deposition steps. In some embodiments, the transfer gate 108 extends through the insulating layer 132 (if present) and into the substrate 102. In other embodiments, the transfer gate 108 is formed over the first side 102a of the substrate 102 and does not extend into the substrate 102.

[0048] As Figure 15 shown in the cross-sectional view 1500, a dielectric 118 is formed above the insulating layer 132. A contact 114 and an interconnect structure 116 are formed within the dielectric. The contact 114 couples the floating node 110 and the transfer gate 108 to the interconnect structure 116. In some embodiments, the contact 114 and the interconnect structure 116 are formed using one or more etching steps, one or more deposition steps, one or more damascene processes, one or more dual damascene processes, the like, or a combination of the foregoing.

[0049] As Figure 16 shown in the cross-sectional view 1600, a third mask layer 1604 is formed above the second side 102b of the substrate 102. In some embodiments, the third mask layer 1604 is a photoresist. The third mask layer 1604 is then patterned. In some embodiments, the third mask layer 1604 is patterned using photolithography. A second implantation process 1602 is then performed. The second implantation process 1602 implants dopants according to the pattern of the third mask layer 1604, resulting in the formation of a photodetector 106 of a first doping type directly above the transfer gate 108. The third mask layer 1604 is subsequently removed.

[0050] As Figure 17As shown in the cross-sectional view 1700, the first sacrificial core 702 (shown in dashed lines) is removed from the substrate 102 to form a second trench 1704. In some embodiments, one or more etching processes 1702 are used to remove the first sacrificial core 702. In some embodiments, a portion of the substrate 102 is removed prior to the one or more etching processes 1702 to expose the first sacrificial core 702. In some embodiments, the one or more etching processes 1702 include a highly selective wet etching process. The wet etching process is a self-aligned etching. In some embodiments, the one or more etching processes 1702 may also remove a portion of the insulating layer 132 that previously surrounded the first sacrificial core 702. Additionally, a portion of the insulating layer 132 surrounding the outer sidewalls of the sealing layer 130 may also be removed.

[0051] As Figure 18 As shown in the cross-sectional view 1800, a high-k dielectric layer 136 is formed over the second side 102b of the substrate 102. In some embodiments, the high-k dielectric layer 136 is or includes a high-k dielectric material, boron, a combination of the foregoing, etc. The high-k dielectric layer 136 is configured to attract stray charge carriers from the substrate 102 and reduce the amount of charge trapping at the surface of the substrate 102, thereby reducing the dark current in the currently formed image sensor. The high-k dielectric layer 136 is conformal with the second side 102b and the second trench 1704 within the substrate 102, such that the high-k dielectric layer 136 extends over the second side 102b and up to the sealing layer 130. In some embodiments, the high-k dielectric layer 136 extends upward to contact the insulating layer 132 at the sidewalls of the sealing layer 130 and fills a portion of the second trench 1704 that was previously occupied by the insulating layer 132 prior to the step corresponding to Figure 17 the step.

[0052] As Figure 19 As shown in the cross-sectional view 1900, a second insulating core 134 is formed within the second trench 1704, covering the inner sidewalls of the high-k dielectric layer 136. An insulating base portion 138 is formed simultaneously with the second insulating core and covers a portion of the high-k dielectric layer 136 on the second side 102b of the substrate 102. In some embodiments, both the insulating base portion 138 and the second insulating core 134 are or include an oxide (such as silicon dioxide (SiO2)), etc. In some embodiments, the second insulating core 134 is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing. After depositing the second insulating core 134 and the insulating base portion 138, a planarization process may be performed to reduce the thickness of the insulating base portion 138. The insulating base portion 138 is configured to protect the high-k dielectric layer 136 from damage. The formation of the second insulating core 134 completes the backside DTI structure 126.

[0053] Figures 20 - 34A cross-sectional view of some embodiments showing an alternative method of forming an image sensor having a DTI structure extending through a substrate is shown, where the backside DTI structure has a smaller width than the frontside DTI structure. Although Figures 20 - 34 is described with respect to one method, it should be understood that Figures 20 - 34 the structures disclosed in Figures 20 - 34 are not limited to this method and may exist separately as structures independent of the method. Although Figures 4 - 19 the numbered etching steps and other structures follow Figure 16 the marking rules of Figures 20 - 34 (e.g., the third trench is described after the second trench of Figures 4 - 19 ), it should be understood that the method associated with Figures 4 - 19 is independent of the method associated with

[0054] and the method steps described below are not limited to being after the method steps associated with Figure 20 As shown in cross-sectional view 2000 of

[0055] a substrate 102 is provided. An insulating layer 132 is formed on the substrate 102. In some embodiments, the insulating layer 132 is a thermal oxide. A first nitride layer 406 is formed above the insulating layer 132. A first hard mask layer 408 is formed above the first nitride layer 406. A fourth mask layer 2004 is formed above the first nitride layer 406. In some embodiments, the first nitride layer 406 and the first hard mask layer 408 are formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing. In some embodiments, the fourth mask layer 2004 is a photoresist. In some embodiments, the first nitride layer 406 is or includes silicon nitride (Si3N4), etc. In some embodiments, the first hard mask layer 408 is or includes silicon dioxide (SiO2), dense silicon dioxide, etc. Figure 4 ) and the pattern is a grid pattern. Subsequently, the fourth mask layer 2004 is removed.

[0056] As Figure 21As shown in the cross-sectional view 2100, an oxide liner is formed across the surface of the first trench 410 such that the insulating layer 132 extends along the surface of the trench. After forming the oxide liner, a conformal nitride layer 2102 is formed over the insulating layer 132. In some embodiments, the oxide liner is formed using a thermal process, a deposition process, or a combination of the foregoing. In some embodiments, the conformal nitride layer 2102 is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing.

[0057] As Figure 22 shown in the cross-sectional view 2200, a fifth etching process 2202 is performed to remove a portion 2204 of the conformal nitride layer (see Figure 21 2102) and a portion 2206 of the insulating layer 132, resulting in the further extension of the fourth trench 2208 into the substrate 102. The fourth trench 2208 extends from the bottom surface of the third trench 2006 and has a smaller width than the third trench 2006 because the portions of the conformal nitride layer 2102 and the insulating layer 132 near the sidewalls of the third trench 2006 have a lower etching rate than the conformal nitride layer 2102 and the insulating layer 132 near the center of the third trench 2006. The first nitride layer 406 and the first hardmask layer 408 further prevent the fifth etching process 2202 from damaging the first side 102a of the substrate 102.

[0058] As Figure 23 shown in the cross-sectional view 2300, a second sacrificial core 2302 is formed in the third trench 2006 (shown in dashed lines) and the fourth trench 2208 (shown in dashed lines). In some embodiments, the second sacrificial core 2302 is formed by depositing a conformal oxide layer (not shown) over the first side 102a of the substrate 102. The conformal oxide layer fills the third trench 2006 and the fourth trench 2208 and overlies the first hardmask layer 408. In some embodiments, the conformal oxide layer can be deposited using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing. After depositing the conformal oxide layer, the first hardmask layer (see Figure 22 408) and the portion of the conformal oxide layer extending over the top surface of the first nitride layer 406 are removed. In some embodiments, a planarization process (e.g., a chemical mechanical planarization process) is used to remove the portion of the conformal oxide layer and the first hardmask layer (see Figure 22 408). The removal process results in the second sacrificial core 2302 remaining in the substrate 102. The inner sidewalls of the fourth trench 2208 (shown in dashed lines) and the second insulating layer 302 are lined with the second sacrificial core 2302.

[0059] As Figure 24As shown in the cross-sectional view 2400, a fifth etching process 2402 is used to remove portions of the second sacrificial core 2302, leaving a second opening 2404. In some embodiments, the fifth etching process 2402 is a wet etching process configured to selectively etch silicon dioxide (SiO2).

[0060] After forming the second opening 2404, a second conformal seal layer 2406 is formed over the first nitride layer 406. In some embodiments, the second conformal seal layer 2406 is or includes dense silicon dioxide (SiO2), silicon nitride, polysilicon, silicon epitaxial layer, combinations of the foregoing, etc. The second conformal seal layer 2406 is conformal with the second opening 2404 and the first nitride layer 406. In some embodiments, the second conformal seal layer 2406 can be deposited using CVD, PVD, ALD, some other suitable deposition process, or combinations of the foregoing.

[0061] As Figure 25 shown in the cross-sectional view 2500, a first insulating core 128 is formed over the second conformal seal layer 2406. The first insulating core 128 is formed by depositing a conformal oxide layer over the substrate 102 and then removing portions of the conformal oxide layer above the upper surface of the second conformal seal layer 2406 using a planarization process (e.g., a CMP process). In some embodiments, the first insulating core is or includes silicon dioxide (SiO2), etc.

[0062] As Figure 26 shown in the cross-sectional view 2600, portions of the second conformal seal layer (see Figure 25 2406), the first nitride layer (see Figure 24 406), and the second insulating layer 302 above the first side 102a of the substrate 102 are removed such that the seal layer 130 remains in the substrate 102. In some embodiments, the portions of the second conformal seal layer (see Figure 25 2406), the first nitride layer (see Figure 24 406), and the second insulating layer 302 are removed using one or more wet etching processes 2602. That is, in some embodiments, a first wet etching process selective to the material of the seal layer 130 can be used to remove the portions of the second conformal seal layer (see Figure 25 2406), and subsequently a second wet etching process with an etching chemistry selective to silicon nitride can be used to remove the first nitride layer (see Figure 24 406) and portions of the second insulating layer 302. In some embodiments, where the seal layer 130 includes a nitride (e.g., silicon nitride (Si3N4)), the portions of the second conformal seal layer (see Figure 25 2406), the first nitride layer (seeFigure 24 The portion of the 406) and the second insulating layer 302 can be removed using a single wet etching process 2602. One or more wet etching processes 2602 result in the formation of a notch 2604 within the sealing layer 130. In some embodiments, the wet etching process(es) 2602 for removing the portion of the second conformal sealing layer (see Figure 25 of 2406) and the first nitride layer (see Figure 24 in 406) also remove a portion of the insulating layer 132. In some embodiments, the wet etching process(es) 2602 expose a portion of the substrate 102 near the sealing layer 130.

[0063] As Figure 27 shown in the cross-sectional view 2700 of, a fifth mask layer 2704 is formed over the substrate 102. In some embodiments, the fifth mask layer 2704 is a photoresist. Subsequently, the fifth mask layer 2704 is patterned to form an opening in the fifth mask layer 2704 corresponding to the location of the floating node region 112 to be formed subsequently. After patterning the fifth mask layer 2704, a third implantation process 2702 is performed to dope the substrate 102 corresponding to the pattern of the opening in the fifth mask layer 2704, thereby forming the floating node region 112. In some embodiments, the dopant is of a first doping type (e.g., n-type doping). In some embodiments, the dopant is implanted into the insulating layer 132 near the floating node region 112. Subsequently, the fifth mask layer 2704 is removed.

[0064] As Figure 28 shown in the cross-sectional view 2800 of, a floating node 110 is formed on the substrate 102 above the floating node region 112. In some embodiments, the floating node 110 is formed using CVD, PVD, ALD, epitaxy, some other suitable deposition process, or a combination of the foregoing. The floating node 110 is or includes polysilicon, epitaxial silicon, metal, another conductive material, or a combination of the foregoing. In some embodiments, the floating node region 112 is exposed by a previous etching process, resulting in the floating node 110 directly contacting the floating node region. In another embodiment, a portion of the insulating layer 132 extends between the floating node 110 and the floating node region 112. The thickness of the portion of the insulating layer 132 between the floating node 110 and the floating node region 112 is small such that during the operation of the image sensor, charge from the photodetector (see Figure 1 of 106) can be conducted from the floating node region 112 to the floating node 110 via quantum tunneling or the like. In yet another embodiment, an etching process is performed to remove a portion of the insulating layer 132 prior to forming the floating node 110, resulting in the lower surface of the floating node 110 directly contacting the first side 102a of the substrate and the floating node region 112.

[0065] As Figure 29 shown in cross-sectional view 2900 of Figure 29 , a transfer gate 108 is formed on a first side 102a of a substrate 102. Forming the transfer gate 108 includes forming a gate dielectric 122 using one or more dry etching and deposition steps, and forming a conductive gate 120 above the gate dielectric using one or more dry etching and deposition steps. In some embodiments, the transfer gate 108 extends through the first side 102a and the insulating layer 132 (if present) and into the substrate 102. In other embodiments, the transfer gate 108 is disposed over the first side 102a of the substrate 102 and does not extend into the substrate 102.

[0066] As Figure 30 shown in cross-sectional view 3000 of Figure 30 , a dielectric 118 is formed above a first side 102a of a substrate 102. A contact 114 and an interconnect structure 116 are formed within the dielectric. The contact 114 couples a floating node 110 and the transfer gate 108 to the interconnect structure 116. In some embodiments, the contact 114 and the interconnect structure 116 are formed using one or more etching steps, one or more deposition steps, one or more damascene processes, the like, or a combination of the foregoing.

[0067] As Figure 31 shown in cross-sectional view 3100 of Figure 31 , a sixth mask layer 3104 is formed above a second side 102b of a substrate 102. In some embodiments, the sixth mask layer 3104 is a photoresist. The sixth mask layer 3104 is then patterned. In some embodiments, the sixth mask layer 3104 is patterned using photolithography. A fourth implantation process 3102 is then performed. The fourth implantation process 3102 implants dopants according to the pattern of the sixth mask layer 3104, resulting in a photodetector 106 of a first doping type directly above the transfer gate 108. The sixth mask layer 3104 is subsequently removed.

[0068] As Figure 32 shown in cross-sectional view 3200 of Figure 32 , a second sacrificial core 2302 (shown in dashed lines) is removed from the substrate 102 to form a fifth trench 3204. In some embodiments, the second sacrificial core 2302 is removed using one or more etching processes 3202. In some embodiments, a portion of the substrate 102 is removed prior to the one or more etching processes 3202 to expose the second sacrificial core 2302. In some embodiments, the one or more etching processes 3202 include a wet etching process. The wet etching process is a self-aligned etch. In some embodiments, the one or more etching processes 3202 may also remove a portion of the insulating layer 132 that previously surrounded the second sacrificial core 2302. Additionally, a portion of the insulating layer 132 surrounding the outer sidewalls of the sealing layer 130 may also be removed.

[0069] As shown Figure 33 in cross-sectional view 3300 of Figure 33 , a high-k layer 136 is formed over a second side 102b of a substrate 102. In some embodiments, the high-k layer 136 is or includes a high-k dielectric material, boron, a combination of the foregoing, etc. The high-k layer 136 is configured to attract stray charge carriers from the substrate 102 and reduce the amount of charge trapping at the surface of the substrate 102, thereby reducing dark current in a currently formed image sensor. The high-k layer 136 is conformal with the second side 102b and a fifth trench 3204 within the substrate 102, resulting in the high-k layer 136 extending over the second side 102b and to a seal layer 130. In some embodiments, the high-k layer 136 extends across a surface of the seal layer 130 to contact an insulating layer 132 and fill a portion of a second trench 1704 that was previously occupied by the insulating layer 132 prior to a step corresponding to Figure 32 that of Figure 32 .

[0070] As shown Figure 34 in cross-sectional view 3400 of Figure 34 , a second insulating core 134 is formed within the fifth trench 3204 and covers an inner sidewall of the high-k layer 136. An insulating base portion 138 is formed simultaneously with the second insulating core and covers a portion of the high-k layer 136 on the second side 102b of the substrate 102. In some embodiments, the second insulating core 134 is formed using CVD, PVD, ALD, some other suitable deposition process, or a combination of the foregoing. After depositing the second insulating core 134 and the insulating base portion 138, a planarization process may be performed to reduce the thickness of the insulating base portion 138. The insulating base portion 138 is configured to protect the high-k layer 136 from damage. The formation of the second insulating core 134 completes a backside DTI structure 126 beneath a frontside DTI structure 124.

[0071] Figure 35 A flowchart shows some embodiments of a method of forming an integrated chip having an image sensor with a DTI structure extending through a substrate.

[0072] Although method 3500 is shown and described below as a series of acts or events, it should be understood that the illustrated order of such acts or events should not be construed as restrictive. For example, some acts may occur in a different order and / or concurrently with other acts or events not shown and / or described herein. Additionally, not all illustrated acts are required to implement one or more aspects or embodiments described herein. Further, one or more of the acts described herein may be performed in one or more separate acts and / or phases.

[0073] At act 3502, a first trench is etched into a first side of a substrate. Figure 4A cross-sectional view 400 corresponding to some embodiments of operation 3502 is shown.

[0074] At operation 3504, the first trench is filled with a sacrificial core including an insulating material. Figures 6 - 7 A cross-sectional view 600 - 700 corresponding to some embodiments of operation 3504 is shown.

[0075] At operation 3506, etching is performed to remove a portion of the sacrificial core on the first side of the substrate, leaving an opening. Figure 8 A cross-sectional view 800 corresponding to some embodiments of operation 3506 is shown.

[0076] At operation 3508, a sealing layer is formed over the first side of the substrate and within the opening. Figure 10 A cross-sectional view 1000 corresponding to some embodiments of operation 3508 is shown.

[0077] At operation 3510, the opening is filled with an insulating core including an insulating material. Figure 10 A cross-sectional view 1000 corresponding to some embodiments of operation 3510 is shown.

[0078] At operation 3512, etching is performed to remove a portion of the sealing layer over the first side of the substrate. Figure 11 A cross-sectional view 1100 corresponding to some embodiments of operation 3512 is shown.

[0079] At operation 3514, a floating node is formed over the insulating core and the remaining portion of the sealing layer. Figure 13 A cross-sectional view 1300 corresponding to some embodiments of operation 3514 is shown.

[0080] At operation 3516, etching is performed to remove the sacrificial core below the sealing layer. Figure 17 A cross-sectional view 1700 corresponding to some embodiments of operation 3516 is shown.

[0081] At operation 3518, the first trench is lined with a high-k dielectric layer. Figure 18 A cross-sectional view 1800 corresponding to some embodiments of operation 3518 is shown.

[0082] At operation 3520, the first trench is filled with a second insulating core extending from the second side of the substrate. Figure 19 A cross-sectional view 1900 corresponding to some embodiments of operation 3520 is shown.

[0083] Accordingly, the present disclosure relates to a new method of forming an integrated chip having an image sensor with a DTI structure extending through a substrate.

[0084] Accordingly, in some embodiments, the present disclosure relates to an image sensor that includes a substrate having a first side and a second side opposite the first side, a photodetector within the substrate, a gate structure on the first side of the substrate above the photodetector, a deep trench isolation (DTI) structure surrounding the photodetector and extending from the first side of the substrate to the second side, a doped floating node region within the substrate on the first side and disposed between the gate structure and the DTI structure; and a floating node on the first side of the substrate in contact with a top surface of the DTI structure and overlying the doped floating node region.

[0085] In some embodiments, the deep trench isolation structure further includes a front-side deep trench isolation structure and a back-side deep trench isolation structure. The front-side deep trench isolation structure extends from the first side into a first depth within the substrate and includes a first insulating core surrounded by a sealant layer and an oxide liner. The back-side deep trench isolation structure extends from the second side into the first depth within the substrate and includes a second insulating core surrounded by a high-k layer. In some embodiments, the front-side deep trench isolation structure has a first width measured from a first sidewall of the oxide liner to a second sidewall of the oxide liner, and the high-k layer has a second width measured from a first sidewall of the high-k layer to a second sidewall of the high-k layer, and wherein the second width is equal to or less than the first width. In some embodiments, a top surface of the back-side deep trench isolation structure extends to a first height measured from the second side of the substrate, and a bottom surface of the front-side deep trench isolation structure extends to a second height measured from the second side of the substrate, the second height being greater than the first height. In some embodiments, the high-k layer has a protrusion that extends from an outer surface of the high-k layer toward the oxide liner and contacts the oxide liner. In some embodiments, the back-side deep trench isolation structure has a first width measured at a height below the front-side deep trench isolation structure and a second width measured at a height above the first depth, wherein the second width is greater than the first width. In some embodiments, the floating node further includes a plurality of protrusions extending into the deep trench isolation structure and a bottom surface extending between the protrusions, wherein the protrusions extend further into the deep trench isolation structure than the bottom surface.

[0086] In other embodiments, the present disclosure relates to an image sensor, the image sensor including a substrate having a first side and a second side opposite the first side, a plurality of photodetectors within the substrate, a plurality of gate structures overlying the photodetectors on the first side of the substrate, a deep trench isolation (DTI) structure including sections surrounding the photodetectors in a grid pattern to isolate the photodetectors from each other, wherein the plurality of sections intersect at intersections, a floating node extending at intersections within the grid pattern of the DTI structure between the gate structures, the floating node extending beyond outer sidewalls of the sections intersecting at the intersections and toward the photodetectors.

[0087] In some embodiments, a top surface of the deep trench isolation structure has a notch surrounding a flat upper surface, and wherein the floating node has a protrusion that fills the notch at the intersections within the grid pattern. In some embodiments, the notch extends in a square pattern around an opening in the grid pattern. In some embodiments, the deep trench isolation structure further includes a front-side deep trench isolation structure and a back-side deep trench isolation structure, the front-side deep trench isolation structure on the first side of the substrate and including an insulating core surrounded by a sealing layer having a U-shaped cross-section, the back-side deep trench isolation structure on the second side of the substrate and extending to a bottom surface of the sealing layer. In some embodiments, the image sensor further includes an insulating base portion on the second side of the substrate, wherein the back-side deep trench isolation structure extends from the insulating base portion, and the back-side deep trench isolation structure further includes a second insulating core and a high-k layer separating the second insulating core from the substrate. In some embodiments, the high-k layer extends above the second side of the substrate to separate the insulating base portion from the substrate. In some embodiments, the floating node is surrounded by a floating node region of a first doping type and extends into the substrate surrounding the intersections within the grid pattern.

[0088] In yet another embodiment, the present disclosure relates to a method of forming an image sensor, the method including etching a first trench into a first side of a substrate, filling the first trench with a sacrificial core including an insulating material, performing an etching to remove a portion of the sacrificial core on the first side of the substrate to leave an opening, forming a sealing layer over the first side of the substrate and within the opening, filling the opening with an insulating core including an insulating material, performing an etching to remove a portion of the sealing layer over the first side of the substrate, forming a floating node over the insulating core and the remaining portion of the sealing layer, performing an etching to remove the sacrificial core below the sealing layer, lining the first trench with a high-k layer, filling the first trench with a second insulating core extending from a second side of the substrate.

[0089] In some embodiments, the method further includes forming a photodetector adjacent to the sacrificial core between removing the portion of the sealing layer and removing the sacrificial core, and forming a floating node region before removing the sacrificial core. In some embodiments, the method further includes forming an insulating layer in the first trench before forming the sealing layer, wherein removing the sacrificial core below the sealing layer further removes a portion of the insulating layer surrounding the sealing layer, and wherein the second trench is lined with the high-k layer such that the high-k layer replaces the portion removed from the insulating layer. In some embodiments, the method further includes etching an initial trench before etching the first trench into the first side of the substrate, and the initial trench is lined with a first insulating layer including a first material and a second insulating layer including a second material different from the first material, wherein the etching of the first trench is a self-aligned etching using the first insulating layer and the second insulating layer to define the sidewalls of the first trench. In some embodiments, the method further includes forming a plurality of photodetectors in the substrate between removing the portion of the sealing layer and removing the sacrificial core, wherein the first trench is etched in a grid pattern, and wherein the photodetectors are formed between a plurality of segments of the grid pattern. In some embodiments, the method further includes forming an insulating base while forming the second insulating core, wherein the insulating base covers the second side of the substrate.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them; although the embodiments of the present invention have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An image sensor, characterized in that: include: a substrate having a first side and a second side opposite the first side; a photodetector in the substrate; a gate structure on the first side of the substrate above the photodetector; a deep trench isolation structure surrounding the photodetector and extending from the first side of the substrate to the second side; a doped floating node region in the substrate at the first side and disposed between the gate structure and the deep trench isolation structure; as well as A floating node, on the first side of the substrate, contacts a top surface of the deep trench isolation structure and overlies the doped floating node region.

2. The image sensor according to claim 1, characterized in that The deep trench isolation structure further comprises: a frontside deep trench isolation structure extending from the first side to a first depth within the substrate, the frontside deep trench isolation structure comprising a first insulating core surrounded by a sealing layer and an oxide liner; and A backside deep trench isolation structure extends from the second side to the first depth within the substrate, the backside deep trench isolation structure comprising a second insulating core surrounded by a high dielectric constant layer.

3. The image sensor according to claim 2, characterized in that The front deep trench isolation structure has a first width measured from a first sidewall of the oxide liner to a second sidewall of the oxide liner, and the high dielectric constant layer has a second width measured from a first sidewall of the high dielectric constant layer to a second sidewall of the high dielectric constant layer, and the second width is equal to or less than the first width.

4. The image sensor according to claim 2, characterized in that: The top surface of the backside deep trench isolation structure extends to a first height measured from the second side of the substrate, and the bottom surface of the frontside deep trench isolation structure extends to a second height measured from the second side of the substrate, and the second height is greater than the first height.

5. The image sensor according to claim 1, characterized in that The floating node further comprises: a plurality of protrusions extending into the deep trench isolation structure; and A lower surface extends between the protrusions, wherein the protrusions extend further into the deep trench isolation structure than the lower surface.

6. An image sensor, characterized in that: include: a substrate having a first side and a second side opposite the first side; a plurality of photodetectors within the substrate; a plurality of gate structures on the first side of the substrate overlying the photodetector; a deep trench isolation structure including a plurality of segments surrounding the photodetectors in a grid pattern, isolating the photodetectors from one another, wherein the segments intersect at intersection points; as well as A floating node extends at the intersection within the grid pattern of the deep trench isolation structure and between the gate structures, wherein the floating node extends beyond the outer sidewalls of the segment at the intersection.

7. The image sensor according to claim 6, characterized in that: The top surface of the deep trench isolation structure has a recess surrounding a flat upper surface, and the floating node has a protrusion that fills the recess at the intersection within the grid pattern.

8. The image sensor according to claim 6, characterized in that: The deep trench isolation structure further comprises: a front side deep trench isolation structure on the first side of the substrate and comprising an insulating core surrounded by a sealing layer, the sealing layer having a U-shaped cross section; and A backside deep trench isolation structure is on the second side of the substrate and extends to a bottom surface of the sealing layer.

9. The image sensor according to claim 8, characterized in that: Also includes: An insulating base portion is on the second side of the substrate, wherein the backside deep trench isolation structure extends from the insulating base portion, and wherein the backside deep trench isolation structure further includes a second insulating core and a high dielectric constant layer separating the second insulating core from the substrate.

10. The image sensor according to claim 6, characterized in that: The floating node is surrounded by a floating node region of a first doping type and extends into the substrate surrounding the intersection within the grid pattern.

Images