VPX test base plate
By designing the VPX test baseboard, providing a universal standard interface and extended standard PCIE slot, the problem of limited types of peripheral service cards in the existing VPX test solutions is solved, and comprehensive testing of VPX motherboards and multiple PCIE peripheral cards is achieved.
Patent Information
- Application Number
- CN202421696194.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-17
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-07-17
AI Technical Summary
In the existing VPX testing solutions, there are limited types of peripheral service cards used to test, resulting in a narrow test coverage and the inability to fully detect various peripheral service cards.
A VPX test base plate is designed, which divides the interface functional area, VPX functional area, PCIE functional area and power supply area through marking, provides a common standard interface and extended standard PCIE slot, and supports a variety of PCIE signal configurations.
It uses standard testing equipment to conduct comprehensive testing of various functions of the VPX main controller, supports testing of a variety of standard PCIE peripheral cards, and fully tests the design indicators of the VPX motherboard.
Smart Images
Figure CN223038106U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a test base plate, in particular to a VPX test base plate. Background Art
[0002] The currently adopted test scheme involves the process of matching and testing a VPX main board with a VPX base plate. In this configuration, all interfaces on the VPX base plate comply with the VPX interface standard. However, there is an obvious drawback in this configuration in practical applications, that is, the types of peripheral service cards available for testing are very limited and the quantity is scarce. This leads to a very narrow coverage of the test work and cannot comprehensively and deeply detect various peripheral service cards. Content of the Utility Model
[0003] The technical problem to be solved by the utility model is to provide a VPX test base plate to solve the problems existing in testing the functions of the VPX main board controller in the background art.
[0004] The VPX test base plate of the utility model is realized through the following technical scheme. A VPX test base plate includes a test base plate main body, and the test base plate main body is sequentially divided into an interface function area, a VPX function area, a PCIE function area, and a power supply area from left to right by marking lines.
[0005] As a preferred technical scheme, VPX connectors P4, P5, and P6 are led out from the interface function area through leads.
[0006] As a preferred technical scheme, a VPX main board is inserted and arranged at the first position (1) of the VPX function area, and the second position of the VPX function area is a function slot.
[0007] As a preferred technical scheme, the first PCIE interface at the uppermost part of the PCIE function area is led out through the VPX connector P2 of the VPX main board. The first PCIE interface supports at most one PCIE X16 function interface, and this function interface can be configured into a X16 PCIE interface, two X8 PCIE interfaces, or four X4 PCIE interfaces;
[0008] The third PCIE interface in the middle part of the PCIE function area is led out through the VPX connector P3 of the VPX main board. The third PCIE interface supports at most a PCIE X8 function interface, and this function interface can be configured into a X8 PCIE interface or two X4 PCIE interfaces;
[0009] The second PCIE interface of the PCIE functional area is led out through the VPX connector P1 of the VPX main board. The second PCIE interface supports a maximum of one PCIE X16 functional interface, and this functional interface can be configured into a PCIE interface of X16, two PCIE interfaces of X8, or four PCIE interfaces of X4.
[0010] As a preferred technical solution, the configurations of the first PCIE interface, the second PCIE interface, and the third PCIE interface are specifically as follows:
[0011] When the PCIE signal on the P1 connector is configured into a signal of X16, only the X16 slot in the above-mentioned PCIE functional area is available;
[0012] When the PCIE signal on the P1 connector is configured into two signals of X8, the X16 and X8 slots are available, and the last 8 lanes of the X16 slot have no function;
[0013] When the PCIE signal on the P1 connector is configured into four signals of X4, all four X4 slots are available, and only the first 4 lanes of the X16 and X8 slots have functions.
[0014] As a preferred technical solution, the power supply area (400) supports power supply by VPX power supply, ATX power supply, and a separate 12V power supply.
[0015] The beneficial effects of the present utility model are as follows:
[0016] All interfaces of the VPX main controller in the present utility model are designed as general standard interfaces, and standard test equipment can be used to test each function of the main controller;
[0017] According to the standard signal definition of the VPX main controller, the present utility model designs a test backplane. Among them, the main board slots are VPX standard slots, and other interfaces are extended to general standard interfaces through this test backplane. The PCIE signal is extended to a standard PCIE slot in the form of a gold finger, which can test many kinds of standard PCIE peripheral cards; the design indexes of the VPX main board can be fully tested. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0019] Figure 1 It is a three-dimensional structural schematic diagram of the present utility model;
[0020] Figure 2 This is a schematic diagram of the PCIE slot structure of the present utility model.
[0021] Explanation of reference numerals:
[0022] 100, interface function area; 200, VPX function area; 300, PCIE function area; 400, power supply area; 1, first position; 2, function slot; 3, first PCIE interface; 4, second PCIE interface; 5, third PCIE interface; 6, VPX power supply; 7, ATX power supply; 8, separate 12V power supply. Specific embodiments
[0023] All features disclosed in this specification, or all steps in the disclosed methods or processes, except for mutually exclusive features and / or steps, can be combined in any manner.
[0024] As Figure 1 and Figure 2 shown, a VPX test base plate of the present utility model, the main body of the test base plate is sequentially divided into an interface function area 100, a VPX function area 200, a PCIE function area 300, and a power supply area 400 from left to right by a marking line.
[0025] Among them, VPX connectors P4, P5, and P6 are led out from the interface function area 100 through leads.
[0026] Among them, a VPX main board is inserted and arranged at the first position 1 of the VPX function area 200, and the second position of the VPX function area 200 is a function slot 2.
[0027] In addition, the first PCIE interface 3 at the uppermost part of the PCIE function area 300 is led out through the VPX connector P2 of the VPX main board. The first PCIE interface 3 supports at most one PCIE X16 function interface. The first PCIE interface 3 can be flexibly configured, and can be configured into a X16 PCIE interface, or can be configured into two X8 PCIE interfaces, or can also be configured into 4 X4 PCIE interfaces;
[0028] The second PCIE interface 4 at the lower part of the PCIE function area 300 is led out through the VPX connector P1 of the VPX main board. The second PCIE interface 4 supports a maximum of one PCIE X16 function interface; The second PCIE interface 4 can be flexibly configured, and can be configured into a X16 PCIE interface, or can be configured into two X8 PCIE interfaces, or can also be configured into 4 X4 PCIE interfaces;
[0029] The third PCIE interface 5 in the middle part of the PCIE functional area 300 is led out through the VPX connector P3 of the VPX motherboard. The third PCIE interface 5 supports at most the functional interface of PCIE X8; it can be configured into a functional interface of PCIE X8 or two functional interfaces of PCIE X4.
[0030] Through the PCIE functional area 300, all PCIE signal configurations on P1, P2, and P3 can be tested.
[0031] In addition, the power supply area 400 supports power supply by the VPX power supply 6, the ATX power supply 7, and the separate 12V power supply 8.
[0032] Illustrated with the PCIE signals on the connector P1 Figure 2 Usage methods of the 4 PCIE slots above:
[0033] The PCIE signals on P1 are configured into a signal of X16. Figure 2 Only the X16 slot can be used, and a PCIE X16 peripheral card can be inserted on it.
[0034] The PCIE signals on P1 are configured into two signals of X8. Figure 2 Both the X16 and X8 slots in it can be used. In the X16 slot, only the first 8 PCIE lanes are functional, and the last 8 lanes are non-functional.
[0035] The PCIE signals on P1 are configured into 4 signals of X4. Figure 2 All 4 PCIE slots in it need to be used. In the X16 and X8 slots, only the first 4 lanes can be recognized, and the subsequent signals are non-functional.
[0036] As mentioned above, it is only the specific implementation manner of the present utility model, but the protection scope of the present utility model is not limited thereto. Any changes or substitutions that are thought of without creative work should be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model should be subject to the protection scope defined by the claims.
Claims
1. A VPX test baseboard, comprising a test baseboard body, characterized in that: The test baseboard body is divided into an interface function area (100), a VPX function area (200), a PCIE function area (300) and a power supply area (400) from left to right by marking lines.
2. The VPX test baseboard according to claim 1, characterized in that: The interface functional area (100) is provided with VPX connectors P4, P5 and P6 via leads.
3. The VPX test baseboard according to claim 1, characterized in that: The first position (1) of the VPX functional area (200) is inserted with a VPX mainboard, and the second position of the VPX functional area (200) is a functional slot (2).
4. The VPX test baseboard according to claim 1, characterized in that: The first PCIE interface (3) at the uppermost part of the PCIE functional area (300) is led out through a VPX connector P2 of the VPX mainboard, and the first PCIE interface (3) supports at most one PCIE X16 functional interface, and the functional interface can be configured as one X16 PCIE interface, two X8 PCIE interfaces, or four X4 PCIE interfaces; The third PCIE interface (5) in the middle part of the PCIE functional area (300) is led out through the VPX connector P3 of the VPX mainboard, and the third PCIE interface (5) supports a PCIE X8 functional interface at most, and the functional interface can be configured as one X8 PCIE interface or two X4 PCIE interfaces; The second PCIE interface (4) at the bottom of the PCIE functional area (300) is led out through a VPX connector P1 of the VPX mainboard. The second PCIE interface (4) supports a maximum of one PCIE X16 functional interface. The functional interface can be configured as one X16 PCIE interface, two X8 PCIE interfaces or four X4 PCIE interfaces.
5. The VPX test baseboard according to claim 4, characterized in that: The configurations of the first PCIE interface (3), the second PCIE interface (4) and the third PCIE interface (5) are specifically as follows: When the PCIE signal on the P1 connector is configured as an X16 signal, only the X16 slot is available in the above PCIE functional area; When the PCIE signal on the P1 connector is configured as two X8 signals, the X16 and X8 slots are available, and the last 8 lanes of the X16 slot are non-functional; When the PCIE signals on the P1 connector are configured as four X4 signals, all four X4 slots are available, and only the first four lanes of the X16 and X8 slots are functional.
6. The VPX test baseboard according to claim 1, characterized in that: The power supply area (400) supports power supply from a VPX power supply (6), an ATX power supply (7) and a separate 12V power supply (8).