Network memory
By using on-board storage components in network memory, embedded substrates and connecting pins, the existing products are solved by solving the problems of large, bulky and poor earthquake resistance, and a smaller, lighter and stable network memory is achieved.
Patent Information
- Application Number
- CN202421602762.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-07-08
AI Technical Summary
The existing network memory is large and bulky due to external mechanical hard disks or SSDs, and has poor shock resistance. It cannot withstand the mechanical impact caused by drops and vibrations, resulting in poor stability.
The data storage solution is adopted in the on-board form, and the storage components are embedded in the substrate, and the pins are connected to the substrate pins, simplifying the entire machine structure, omitting external connectors and fixing screws, achieving a smaller and lighter network memory.
Improves the stability and shock resistance of network memory, reduces chassis housing size, reduces cost, and enhances product durability.
Smart Images
Figure CN223038401U_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of data storage, and particularly relates to a network storage device. Background Art
[0002] In existing Network Attached Storage (NAS) products, data storage is mostly achieved by: 1) connecting an external 2.5-inch mechanical hard disk, solid state drive (SSD), or an external 3.5-inch mechanical hard disk through a SATA interface. 2) connecting an external NVME protocol SSD through an M.2 interface.
[0003] However, for the above NAS products, since the mechanical hard disk or SSD is externally connected through an interface, the entire NAS product is large, has a bulky appearance, poor shock resistance, and cannot withstand the mechanical impact caused by dropping and vibration, resulting in poor stability of the NAS product. Summary of the Utility Model
[0004] An embodiment of this application provides a network storage device, which can solve the problems that the entire NAS product is large, has a bulky appearance, poor shock resistance, and cannot withstand the mechanical impact caused by dropping and vibration, resulting in poor stability of the NAS product.
[0005] An embodiment of this application provides a network storage device, which includes: a substrate; a storage element, the storage element is embedded in the substrate, and the pins of the storage element are connected to the pins of the substrate.
[0006] In an embodiment of this application, the network storage device includes: a substrate; a storage element, the storage element is embedded in the substrate, and the pins of the storage element are connected to the pins of the substrate. Embedding the storage element in the substrate makes the network storage device smaller and lighter, and can improve the stability of the network storage device. Description of the Drawings
[0007] Figure 1 is a schematic structural diagram of a network storage device provided by an embodiment of this application;
[0008] Figure 2 is a schematic structural diagram of another network storage device provided by an embodiment of this application;
[0009] Figure 3 is a schematic structural diagram of another network storage device provided by an embodiment of this application.
[0010] Description of the Reference Numerals:
[0011] Substrate - 10, reset circuit - 101, storage element - 20, processor - 30, clock crystal - 40, power supply - 50, sub - power supply - 501. Detailed implementation
[0012] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.
[0013] The terms "first", "second", etc. in the description and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and / or" in the description and claims means at least one of the connected objects, and the character " / " generally represents an "or" relationship between the associated objects before and after.
[0014] The following will, with reference to the accompanying drawings, provide a detailed description of a network storage device provided by the embodiments of the present application through specific embodiments and their application scenarios.
[0015] Figure 1 FIG. is a schematic structural diagram of a network storage device provided by an embodiment of the present application. The network storage device includes: a substrate 10; a storage element 20, the storage element 20 is embedded in the substrate 10, and the pins of the storage element 20 are connected to the pins of the substrate 10.
[0016] Specifically, as Figure 1 shown, the present application uses an on - board data storage solution for the network storage device, that is, the storage element 20 is embedded in the substrate 10. Therefore, the pins of the storage element 20 can be connected to the pins of the substrate 10 by welding.
[0017] The network storage device is the NAS network storage device. The storage component 20 can be a BGA SSD, which is an embedded solid-state drive. It adopts the TFBGA packaging form and supports Serial ATA 3.1. By combining advanced NAND flash memory with SSD controller and flash memory management technology, the BGA SSD can provide more reliable and higher performance. The BGA SSD is characterized by small size, light weight, fast speed, low power consumption, and also has a wide operating temperature range, shock resistance, and vibration resistance. In the embodiment of the present application, the storage component 20 can also support other communication protocols. For example, the storage component 20 can be a Sata BGA SSD, a PCIE BGA SSD, or a USB BGA SSD, etc. No specific limitation is made on the storage component 20 here.
[0018] The storage component 20 provided in the embodiment of the present application, the network storage device includes: a substrate 10; a storage component 20, the storage component 20 is embedded in the substrate 10, and the pins of the storage component 20 are connected to the pins of the substrate 10. The storage component 20 is embedded in the substrate 10, making the whole machine system simpler. The connector socket and fixing screws for connecting to the traditional hard disk are omitted, and the assembly process of the whole machine is omitted, making the network storage device small in size, light in weight, fast in speed, and low in power consumption. It is beneficial to the miniaturization of the network storage device, reduces the size of the chassis shell of the network storage device, reduces the cost, and can improve the seismic resistance of the network storage device. At the same time, the network storage device has no external interface, improving the stability of the network storage device.
[0019] In one implementation, the network storage device further includes: a processor 30, the processor 30 is embedded in the substrate 10, and the processor 30 is connected to the data transmission pins of the storage component 20 through the substrate 10.
[0020] Specifically, as Figure 2 shown, the network storage device can also include a processor 30. In the pin definition of the package of the storage component 20, there are data transmission pins. The processor 30 (CPU) can be connected to the data transmission pins of the storage component 20 through the circuit on the substrate 10. In this way, data interaction for storing data of the NAS product can be carried out between the processor 30 and the BGA SSD.
[0021] In one implementation, the data transmission pins include data sending pins and data receiving pins; the processor 30 is respectively connected to the data sending pins and the data receiving pins through the substrate 10.
[0022] Specifically, the data transmission pins of the storage component 20 can include data sending pins and data receiving pins, as Figure 3As shown, the processor 30 can be respectively connected to the data sending pin and the data receiving pin of the storage element 20 through the circuit on the substrate 10. In this way, the storage element 20 can receive the data sent by the processor 30 through the data receiving pin and send data to the processor 30 through the data sending pin, realizing the data transmission between the processor 30 and the memory element 20. Among them, the circuit connecting the data sending pin and the data receiving pin of the processor 30 and the storage element 20 can be the high-speed differential bus SATA_TXp / n and SATA_RXp_n that support the SATA3.0 protocol. In this way, the processor 30 can communicate with the storage element 20 through the high-speed differential bus SATA_TXp / n and SATA_RXp_n that support the SATA3.0 protocol to realize data interaction. In the embodiment of the present application, the circuit connecting the data sending pin and the data receiving pin of the processor 30 and the storage element 20 can also be the high-speed differential bus PCIE_TXp / n and PCIE_RXp_n that support the PCIE protocol. In this way, the processor 30 can perform data transmission with the storage element 20 through the high-speed differential bus PCIE_TXp / n and PCIE_RXp_n that support the PCIE protocol to realize the interaction of stored data. Of course, the circuit connecting the data sending pin and the data receiving pin of the processor 30 and the storage element 20 can also be a high-speed differential bus that supports other communication protocols, and the communication protocol of this high-speed differential bus is not specifically limited herein.
[0023] In one implementation, the network memory further includes:
[0024] A processor 30, the processor 30 is embedded in the substrate, and the processor 30 is connected to the reset pin of the storage element 20 through the substrate 10.
[0025] Specifically, in the package pin definition of the storage element 20, there is also a reset (RST) pin. As Figure 3 shown, the processor 30 can be connected to the reset pin of the storage element 20 through the circuit on the substrate 10. In this way, the processor 30 can perform a reset operation on the storage element 20.
[0026] In one implementation, the network memory further includes: a clock crystal 40; the clock crystal 40 is embedded in the substrate 10, and the clock crystal 40 is connected to the clock pin of the storage element 20 through the second circuit of the substrate 10.
[0027] Specifically, the package pin definition of the storage element 20 also includes clock pins (XTAL_IN, XTAL_OUT). The network memory further includes a clock crystal 40, and the clock crystal 40 is embedded in the substrate 10. As Figure 3As shown, the clock crystal 40 is connected to the clock pin of the storage element 20 through the circuit of the substrate 10. In the embodiments of the present application, different external clock crystals 40 can be selected according to different external clock frequencies required by the storage element 20.
[0028] In one implementation, the network memory further includes: a power supply 50, the power supply 50 is embedded in the substrate 10, the power supply 50 is connected to the processor 30 through the substrate 10, and the power supply 50 is connected to the power pin of the storage element 20 through the substrate 10.
[0029] Specifically, as Figure 3 shown, the network memory further includes a power supply 50, and the package pin definition of the storage element 20 further includes a power pin. The power supply 50 is also embedded in the substrate 10, the power supply 50 is connected to the processor 30 through the circuit of the substrate 10, and the power supply 50 is connected to the power pin of the storage element 20 through the circuit of the substrate 10. In this way, the power supply 50 can be controlled by the processor 30 to realize power-off and power-on of the storage element 20. As timing control, it can also perform a power-on operation after the storage element 20 abnormally freezes.
[0030] In one implementation, the power supply 50 includes a plurality of sub-power supplies 501, and the power pins include: a plurality of sub-power pins, and the plurality of sub-power supplies 501 are respectively connected to the plurality of sub-power pins through the substrate 10.
[0031] In the embodiments of the present application, the power supply 50 can include a plurality of sub-power supplies 501. In the package pin definition of the storage element 20, a plurality of different sub-power pins can be defined, such as sub-power pins supporting different voltages, such as sub-power pins supporting 1.1V, sub-power pins supporting 3.3V, sub-power pins supporting 1.2V, etc. In this way, the sub-power pins supporting different voltages need to be connected to different sub-power supplies 501 for power supply. As an example, for example Figure 3 shown, the power supply 50 can be output by three groups of independent DC-DC sub-power supplies 501 respectively, that is, the power supply 50 includes three sub-power supplies 501. Then, the three sub-power supplies 501 can respectively supply power to three types of sub-power pins supporting different voltages in the storage element 20. For example, the first sub-power supply 501 supplies power to the sub-power pin supporting 1.1V in the storage element 20, the second sub-power supply 501 supplies power to the sub-power pin supporting 1.2V in the storage element 20, and the third sub-power supply 501 supplies power to the sub-power pin supporting 3.3V in the storage element 20. The plurality of sub-power supplies 501 can all be controlled by the processor 30 for power-on and power-off, so that independent power supply can be realized for different types of sub-power pins of the storage element 20.
[0032] In one implementation, the substrate 10 further includes: a reset circuit 101, and the reset circuit 101 is connected to the reset pin of the storage element 20.
[0033] As Figure 3 shown, the substrate 10 further includes a reset circuit 101, and this reset circuit 101 is connected to the reset pin of the storage element 20. This reset circuit 101 generally includes a capacitor (C) and a resistor (R), and a reset signal can be transmitted to the reset pin of the storage element 20 through this reset circuit 101, and thus the RC power-on reset of the storage element 20 can be realized.
[0034] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific implementation manners. The above specific implementation manners are merely illustrative rather than restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all of them fall within the protection scope of the present application.
Claims
1. A network storage, characterized in that: include: substrate; A storage element, wherein the storage element is embedded in the substrate, a pin of the storage element is connected to a pin of the substrate, and the storage element is packaged by BGA; A plurality of sub-power supplies with different voltages are respectively connected to different sub-power supply pins of the storage element through the substrate.
2. The network storage according to claim 1, characterized in that: The network storage further comprises: A processor is embedded in the substrate, and the processor is connected to a data transmission pin of the storage element through the substrate.
3. The network storage according to claim 2, characterized in that: The data transmission pins include a data transmission pin and a data receiving pin; The processor is connected to the data sending pin and the data receiving pin respectively through the substrate.
4. The network storage according to claim 1, characterized in that: The network storage further comprises: A processor is embedded in the substrate, and the processor is connected to a reset pin of the storage element through the substrate.
5. The network storage according to claim 1, characterized in that: The network storage further comprises: A clock crystal is embedded in the substrate, and the clock crystal is connected to a clock pin of the storage element through the substrate.
6. The network storage according to claim 1, characterized in that: The network storage further comprises: A power supply is embedded in the substrate, the power supply is connected to the processor through the substrate, and the power supply is connected to the power pin of the storage element through the substrate.
7. The network storage according to claim 6, characterized in that: The power supply includes a plurality of sub-power supplies, and the power pin includes a plurality of sub-power pins.
8. The network storage according to claim 1, characterized in that: The substrate further comprises: A reset circuit is connected to a reset pin of the storage element.