Storage device

Abstract

The utility model discloses a storage device, which comprises a control unit, a plurality of storage units, a plurality of switch units and a plurality of detection units, wherein the switch units are arranged in one-to-one correspondence with the storage units; the detection units are arranged in one-to-one correspondence with the storage units; the storage unit comprises a storage signal input end and a storage signal output end; the switch unit comprises a switch input end, a switch output end and a switch control end; part of switch input ends are electrically connected with the same storage signal providing end, and switch output ends are electrically connected with the storage signal input end. The detection unit comprises a detection signal providing end and a detection signal output end, and the detection signal providing end is electrically connected with the storage signal output end; the control unit comprises a plurality of storage signal write-in ends, a plurality of detection signal input ends and a plurality of switch signal output ends, each storage signal write-in end is electrically connected with each storage signal providing end, each detection signal output end is electrically connected with each detection signal input end, and each switch signal output end is electrically connected with each switch control end.

Description

Technical Field

[0001] The utility model relates to the field of storage technologies, and in particular to a storage device. Background Art

[0002] Existing storage units include multiple storage devices. Inside the storage unit, a partial number of storage devices are connected to the same input electrical signal to store the same data. However, due to certain differences in the internal impedance of each storage device, when the same electrical signal is input to each storage device, the electrical signal will first flow through the storage device with a smaller internal impedance, resulting in a relatively low data consistency among the storage devices that are originally required to store the same data, and a relatively low storage reliability of the storage unit. How to improve the storage reliability of the storage unit has become a technical problem that urgently needs to be solved currently. Content of the Utility Model

[0003] The utility model provides a storage device, which can improve the storage reliability of the storage device.

[0004] The utility model provides a storage device, including a control unit, multiple storage units, multiple switch units respectively arranged corresponding to each of the storage units, and multiple detection units respectively arranged corresponding to each of the storage units;

[0005] The storage unit includes a storage signal input end and a storage signal output end;

[0006] The switch unit includes a switch input end, a switch output end and a switch control end; a part of the switch input ends are electrically connected to the same storage signal providing end, and the switch output end is electrically connected to the storage signal input end;

[0007] The detection unit includes a detection signal providing end and a detection signal output end, and the detection signal providing end is electrically connected to the storage signal output end;

[0008] The control unit includes multiple storage signal writing ends, multiple detection signal input ends and multiple switch signal output ends. Each of the storage signal writing ends is electrically connected to each of the storage signal providing ends, each of the detection signal output ends is electrically connected to each of the detection signal input ends, and each of the switch signal output ends is electrically connected to each of the switch control ends.

[0009] Optionally, the storage device includes:

[0010] A substrate;

[0011] The switch unit is located on one side of the substrate;

[0012] The storage unit is located on the side of the switch unit away from the substrate.

[0013] Optionally, the storage unit includes a memristor;

[0014] The memristor comprises a first electrode, a first insulating layer, a third conductive layer, a second insulating layer and a second electrode which are stacked in sequence;

[0015] The first electrode is electrically connected to the switch output terminal, and the second electrode is electrically connected to the detection signal providing terminal.

[0016] Optionally, the switch unit includes a switch transistor;

[0017] The first electrode of the switch transistor is electrically connected to the storage signal supply terminal, the second electrode of the switch transistor is electrically connected to the first electrode, and the gate of the switch transistor is electrically connected to the switch signal output terminal.

[0018] Optionally, the storage device further includes:

[0019] A semiconductor layer, located on one side of the substrate; the semiconductor layer includes an active layer of the switch transistor;

[0020] A passivation layer is located on a side of the semiconductor layer away from the substrate; the passivation layer comprises a plurality of opening structures and passivation structures surrounding each of the opening structures; the opening structures comprise a first pole opening structure, a second pole opening structure and a gate opening structure; the gate opening structure is located between the first pole opening structure and the second pole opening structure;

[0021] A first conductive layer, including a gate of the switch transistor located within the gate opening structure;

[0022] The second conductive layer includes a first electrode of the switch transistor located in the first electrode opening structure, and a second electrode of the switch transistor located in the second electrode opening structure.

[0023] Optionally, the semiconductor layer includes a first nitride layer and a second nitride layer which are stacked;

[0024] The second nitride layer is located on a side of the first nitride layer facing away from the substrate.

[0025] Optionally, the semiconductor layer further includes: a third nitride layer;

[0026] The third nitride layer is located on a side of the second nitride layer facing away from the first nitride layer.

[0027] Optionally, the detection unit includes a light emitting element and a current detection element;

[0028] The first end of the light-emitting element is electrically connected to the storage signal output terminal, the second end of the light-emitting element is electrically connected to the current input terminal of the current detection element, the current output terminal of the current detection element is electrically connected to the ground terminal, and the current detection signal output terminal of the current detection element is electrically connected to the detection signal input terminal.

[0029] Optionally, the second pole of the switching transistor is multiplexed as the first electrode.

[0030] Optionally, the storage device further includes a buffer layer located between the substrate and the switching unit.

[0031] The technical solution of the present invention is to set a detection unit electrically connected to the storage unit and the control unit respectively, so that the control unit determines the storage state of the storage unit according to the detection signal obtained by the detection unit. The control unit is also electrically connected to each storage signal providing terminal, and according to the electrical signals of each storage signal providing terminal and the storage state of the storage unit, controls the on or off state of the switching unit electrically connected to each storage unit, so that the storage signal provided by the storage signal providing terminal can only be transmitted to one storage unit at the same time, to improve the storage accuracy and reliability of each storage unit, and further improve the consistency of the stored data in each storage unit storing the same storage signal, and improve the storage reliability of the storage device. Description of the Drawings

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some specific embodiments of the present invention. For those skilled in the art, according to the basic concepts of the device structure, driving method and manufacturing method disclosed and prompted by various embodiments of the present invention, they can be extended and extended to other structures and drawings. Undoubtedly, these should be within the scope of the claims of the present invention.

[0033] Figure 1 FIG. 1 is a schematic structural diagram of a storage device provided by an embodiment of the present invention;

[0034] Figure 2 FIG. 2 is a partial structural diagram of a storage device provided by an embodiment of the present invention;

[0035] Figure 3 FIG. 3 is a partial structural diagram of another storage device provided by an embodiment of the present invention;

[0036] Figure 4 FIG. 4 is a partial structural diagram of yet another storage device provided by an embodiment of the present invention;

[0037] Figure 5Partial structural schematic diagram of another storage device provided by an embodiment of the present utility model;

[0038] Figure 6 Structural schematic diagram of another storage device provided by an embodiment of the present utility model;

[0039] Figure 7 Partial structural schematic diagram of a storage device provided by an embodiment of the present utility model;

[0040] Figure 8 Partial structural schematic diagram of another storage device provided by an embodiment of the present utility model;

[0041] Figure 9 Process structural schematic diagram of preparing a partial storage device provided by an embodiment of the present utility model. Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the present utility model clearer, the following will, with reference to the accompanying drawings in the embodiments of the present utility model, clearly and completely describe the technical solutions of the present utility model through implementation manners. Obviously, the described embodiments are some but not all of the embodiments of the present utility model. Based on the basic concepts disclosed and prompted by the embodiments in the present utility model, all other embodiments obtained by those skilled in the art fall within the protection scope of the present utility model.

[0043] Figure 1 Structural schematic diagram of a storage device provided by an embodiment of the present utility model, as Figure 1 shown, the storage device includes a control unit 10, a plurality of storage units 20, a plurality of switch units 30 provided in one-to-one correspondence with the respective storage units 20, and a plurality of detection units 50 provided in one-to-one correspondence with the respective storage units 20. The storage unit 20 includes a storage signal input terminal S1 and a storage signal output terminal S2. The switch unit 30 includes a switch input terminal D1, a switch output terminal D2, and a switch control terminal D3. Some of the switch input terminals D1 are electrically connected to the same storage signal providing terminal Sg, and the switch output terminal D2 is electrically connected to the storage signal input terminal S1. The detection unit 50 includes a detection signal providing terminal T1 and a detection signal output terminal T2, and the detection signal providing terminal T1 is electrically connected to the storage signal output terminal S2. The control unit 10 includes a plurality of storage signal writing terminals, a plurality of detection signal input terminals, and a plurality of switch signal output terminals. Each storage signal writing terminal is electrically connected to each storage signal providing terminal Sg, each detection signal output terminal T2 is electrically connected to each detection signal input terminal, and each switch signal output terminal is electrically connected to each switch control terminal D3.

[0044] Among them, the control unit 10 includes devices such as a controller, the storage unit 20 includes devices such as a memristor, the switching unit 30 includes switching devices such as transistors, the detection unit 50 includes current detection devices or voltage detection devices, etc., the storage signal providing terminal Sg includes voltage signals, etc. The storage device may include multiple storage signal providing terminals Sg, which can be set according to actual needs. For the convenience of description, the following embodiments will be described by taking the storage device including 2 storage signal providing terminals as an example, namely the storage signal providing terminal Sg1 and the storage signal providing terminal Sg2, and it can also be others, which will not be specifically limited here.

[0045] It should be noted that the number of switching units 30 electrically connected to the same storage signal providing terminal Sg can be set according to actual needs. Exemplarily, the number of switching units 30 electrically connected to the storage signal providing terminal Sg1 is n, which are respectively the switching units 301, 302, ···, 30n. Correspondingly, the number of storage units 20 indirectly electrically connected to the storage signal providing terminal Sg1 through each switching unit 30 is also n, which are respectively the storage units 201, 202, ···, 20n. The detection units 50 electrically connected to each storage unit 201, 202, ···, 20n are respectively the detection units 501, 502, ···, 50n. The number of switching units 30 electrically connected to the storage signal providing terminal Sg2 is m, which are respectively the switching units 301, 302, ···, 30m. Correspondingly, the number of storage units 20 indirectly electrically connected to the storage signal providing terminal Sg2 through each switching unit 30 is also m, which are respectively the storage units 201, 202, ···, 20m. The detection units 50 electrically connected to each storage unit 201, 202, ···, 20m are respectively the detection units 501, 502, ···, 50m.

[0046] Specifically, the detection unit 50 can detect the signal stored in the storage unit 30, and output the detection signal to the control unit 10 according to the signal stored in the storage unit 20. The storage signal writing end of the control unit 10 is electrically connected to each storage signal providing end Sg. The control unit 10 can determine the current storage state of the storage unit 20 according to the storage signal provided by the storage signal providing end Sg and the detection signal provided by the detection unit 50, so as to control the switch unit 30 corresponding to the storage unit 20 to be in the on state or the off state according to the current storage state of the storage unit 20. Each switch unit 30 electrically connected to the same storage signal providing terminal Sg is turned on in a time-sharing manner. For example, when the storage signal provided by the storage signal providing terminal Sg1 can control the storage unit 20 to be in a low-impedance storage state, the detection unit 50 detects the signal output by the storage signal output terminal S2 of the storage unit 20 and converts it into a detection signal and transmits it to the control unit 10. The detection signal includes a current signal or a voltage signal, etc. If the detection signal is less than the preset signal, it means that the storage unit 20 has not yet stored the storage signal in place. At this time, the control unit 10 can control the switch unit 30 corresponding to the storage unit 20 to be in a conducting state, so that the storage signal of the storage signal providing terminal Sg can be transmitted to the storage unit 20 through the switch unit 30. The preset signal can be determined according to the storage signal provided by the storage signal providing terminal Sg. If the detection signals obtained by the detection units 50 corresponding to multiple storage units 20 are all smaller than the preset signals, the control unit 10 controls the switch units 30 corresponding to each storage unit 20 to be in the on state in a certain order, so as to prevent the storage signal from passing through the storage unit 20 with smaller impedance first when the switch units 30 corresponding to each storage unit 20 are in the on state at the same time, thereby causing different data stored in each storage unit 20. The embodiment of the utility model controls the on state of the switch units 30 corresponding to each storage unit 20 in a time-sharing manner through the control unit 10, so that the storage signal provided by the storage signal providing terminal Sg can only be transmitted to one storage unit 20 at the same time, so as to improve the consistency of the storage signals of each storage unit 20 indirectly electrically connected to the same storage signal providing terminal Sg, and improve the storage reliability of the storage device.

[0047] The technical solution provided by the utility model is to set a detection unit electrically connected to the storage unit and the control unit respectively, so that the control unit determines the storage state of the storage unit according to the detection signal obtained by the detection unit. The control unit is also electrically connected to each storage signal providing end, so as to control the on or off state of the switch unit electrically connected to each storage unit according to the electrical signal of each storage signal providing end and the storage state of the storage unit, so that the storage signal provided by the storage signal providing end can only be transmitted to one storage unit at the same time, so as to improve the storage accuracy and reliability of each storage unit, thereby improving the consistency of the stored data in each storage unit storing the same storage signal, and improving the storage reliability of the storage device.

[0048] Optionally, Figure 2 This is a partial structural schematic diagram of a storage device provided by an embodiment of the present invention. As Figure 2 shown, the storage device includes a substrate 4. The switching unit 30 is located on one side of the substrate 4, and the storage unit 20 is located on the side of the switching unit 30 away from the substrate 4.

[0049] Among them, the substrate 4 serves as the substrate of the storage device and plays a role of fixing and supporting in the storage device. The substrate 4 includes materials such as silicon, silicon carbide or sapphire, which can be set according to actual needs and are not specifically limited here.

[0050] Specifically, by arranging the storage unit 20 on the side of the switching unit 30 away from the substrate 4, the length of the electrical connection path between the switching unit 30 and the storage unit 20 is reduced, thereby reducing the power loss of the storage signal in the transmission line and simultaneously reducing the overall size of the storage device. In addition, by arranging the switching unit 30 and the storage unit 20 in sequence on one side surface of the substrate 4, when preparing the storage device, the switching unit 30 and the storage unit 20 can be prepared in sequence on one side of the substrate 4 to improve the connection reliability between the switching unit 30 and the storage unit 20, and further improve the working reliability of the storage device.

[0051] Optionally, Figure 3 This is a partial structural schematic diagram of another storage device provided by an embodiment of the present invention. Referring to Figure 1 and Figure 3 , the storage unit 20 includes a memristor 26. The memristor 26 includes a first electrode 21, a first insulating layer 23, a third conductive layer 25, a second insulating layer 24 and a second electrode 22 which are stacked in sequence. The first electrode 21 is electrically connected to the switch output terminal D2, and the second electrode 22 is electrically connected to the detection signal providing terminal T1.

[0052] Among them, the first electrode 21 includes conductive materials such as aluminum, platinum or tungsten, the second electrode 22 includes conductive materials such as tungsten, nickel or copper, the first insulating layer 23 and the second insulating layer 24 include nitride materials such as AlN, SiNx or BN, the third conductive layer 25 includes conductive materials such as copper or silver, and the thickness of the third conductive layer 25 can be set according to actual needs. Exemplarily, the thickness of the third conductive layer 25 is 3 nm to 5 nm, which can be set according to actual needs and is not specifically limited here.

[0053] Specifically, the working principle of the memristor 26 is as follows: Taking the first insulating layer 23 and the second insulating layer 24 both being aluminum nitride and the third conductive layer 25 being copper as an example, when a set voltage is provided to the first electrode 21 or the second electrode 22 of the memristor 26, the copper element in the third conductive layer 25 will diffuse into the lattice defects of the aluminum nitride layer and exist in the first insulating layer 23 and the second insulating layer 24. The type of conductive filament dominated by nitrogen vacancies is transformed into a conductive filament dominated by the doped element copper. The current inside the memristor 26 is mainly transmitted through the conductive filament dominated by the doped element copper, and the memristor 26 is transformed into a low-resistance state. When a reset voltage is provided to the first electrode 21 or the second electrode 22, the copper atoms in the metal conductive filament will return to the third conductive layer 25 under the action of the reset voltage, causing the memristor 26 to be transformed into a high-resistance state. In this way, different storage signals can be provided by the storage signal providing end Sg to make the storage unit 20 in different storage states. In addition, by arranging the third conductive layer 25 between the first insulating layer 23 and the second insulating layer 24, the doping concentration of the first insulating layer 23 and the second insulating layer 24 can be changed to adjust the type of conductive filament formed between the first electrode 21 and the second electrode 22. Furthermore, the polarity of the reset voltage of the memristor 20 is the same as the polarity of the set voltage. The reset voltage and the set voltage can both be positive or both be negative, enabling the storage signal providing end Sg to only provide a positive-polarity or negative-polarity storage signal without providing a reverse voltage, making the storage device have a lower power consumption, improving the storage state switching rate of the storage unit 20, and enhancing the working reliability of the storage device.

[0054] Optionally, Figure 4 is a partial structural schematic diagram of another storage device provided by an embodiment of the present invention. Refer to Figure 1 and Figure 4 , the switching unit 30 includes a switching transistor 33. The first pole 331 of the switching transistor 33 is electrically connected to the storage signal providing end Sg, the second pole 332 of the switching transistor 33 is electrically connected to the first electrode 21, and the gate G of the switching transistor 33 is electrically connected to the switching signal output end.

[0055] Among them, the switching transistor 33 can include a high electron mobility transistor, and the high electron mobility transistor has a high electron mobility to improve the switching efficiency and signal transmission rate of the switching transistor 33.

[0056] Specifically, the switching transistor 33 may include a P-type transistor, an N-type transistor, etc., which can be set according to actual needs. Taking the switching transistor 33 as an N-type transistor as an example, when the gate G of the switching transistor 33 receives a high-level switching signal, the switching transistor 33 is in the on state, so that the storage signal received by the first pole 331 can be transmitted to the second pole 332. When the gate G of the switching transistor 33 receives a low-level switching signal, the switching transistor 33 is in the off state, so that the second pole 332 cannot receive the storage signal received by the first pole 331, thereby enabling the subsequent storage unit 20 to maintain the current storage state.

[0057] Optionally, referring to Figure 4 , the storage device further includes a semiconductor layer 40, a passivation layer 44, a first conductive layer 53, and a second conductive layer 54. The semiconductor layer 40 is located on one side of the substrate 4, and the semiconductor layer 40 includes the active layer of the switching transistor 33. The passivation layer 44 is located on the side of the semiconductor layer 40 away from the substrate 4. The passivation layer 44 includes a plurality of opening structures and passivation structures 444 respectively surrounding each opening structure. The opening structures include a first pole opening structure 441, a second pole opening structure 442, and a gate opening structure 443. The gate opening structure 443 is located between the first pole opening structure 441 and the second pole opening structure 442. The first conductive layer 53 includes the gate G of the switching transistor 33 located within the gate opening structure 443. The second conductive layer 54 includes the first pole 331 of the switching transistor 33 located within the first pole opening structure 441, and the second pole 332 of the switching transistor 33 located within the second pole opening structure 442.

[0058] Among them, the semiconductor layer 40 includes semiconductor materials such as gallium nitride, the passivation structures 444 in the passivation layer 44 include materials such as silicon nitride, the first conductive layer 53 includes conductive materials such as titanium, aluminum, nickel, or copper, and the second conductive layer 54 includes conductive materials such as nickel or copper, which can be set according to actual needs and are not specifically limited here.

[0059] Specifically, by setting a passivation structure 444 around the opening structure, a gate G, a first electrode 331, and a second electrode 332 are arranged in the opening structure to protect the gate G, the first electrode 331, and the second electrode 332 from external corrosive media entering the gate G, the first electrode 331, or the second electrode 332, so as to extend the service life of the switching transistor 33. When preparing the electrode structure of the switching transistor 33, a whole passivation layer 44 can be prepared on the side of the semiconductor layer 40 away from the substrate 4, and then a first electrode opening structure 441, a second electrode opening structure 442, and a gate opening structure 443 are prepared in the passivation layer 44 through processes such as etching. Then, a first conductive layer 53 and a second conductive layer 54 are prepared through processes such as chemical vapor deposition. The second conductive layer 54 includes the first electrode 331 located in the first electrode opening structure 441 and the second electrode 332 located in the second electrode opening structure 442, and the first conductive layer 53 includes the gate G located in the gate opening structure 443. By setting the gate opening structure 443 between the first electrode opening structure 441 and the second electrode opening structure 442, the gate G is located between the first electrode 331 and the second electrode 332. When a switching signal is provided to the gate G, a conductive channel can be generated in the active layer in the semiconductor layer 40, so that the first electrode 331 and the second electrode 332 are connected through the conductive channel of the active layer.

[0060] Optionally, continue to refer to Figure 4 , the semiconductor layer 40 includes a first nitride layer 41 and a second nitride layer 42 arranged in a stacked manner; the second nitride layer 42 is located on the side of the first nitride layer 41 away from the substrate 4.

[0061] Among them, the electron mobility in the first nitride layer 41 is different from that in the second nitride layer 42. The first nitride layer 41 includes materials such as gallium nitride, and the second nitride layer 42 includes materials such as aluminum gallium nitride, which can be set according to actual needs.

[0062] Specifically, compared with materials such as silicon or silicon carbide, nitride materials have higher electron mobility and saturation electron rate. Therefore, by making the semiconductor layer 40 include nitride materials, the switching transistor 33 can achieve a smaller on-resistance and switching signal, and the working efficiency of the switching transistor 33 can be improved. In addition, by setting the electron mobility in the first nitride layer 41 to be different from that of the second nitride layer 42, and the materials of the first nitride layer 41 and the second nitride layer 42 are different, so that the first nitride layer 41 and the second nitride layer 42 form a heterostructure. After providing a switching signal for controlling the conduction of the switching transistor 33 to the gate G, a piezoelectric effect is generated in the lattice materials of the first nitride layer 41 and the second nitride layer 42. The positive and negative charges inside the lattice are separated under the action of the piezoelectric effect, and the separated charges move to the junction of the heterostructure under the action of the electric field, that is, the interface between the first nitride layer 41 and the second nitride layer 41, causing the energy band of the heterostructure to bend, forming a quantum well in the deep bend of the conduction band, and confining the electrons generated by the piezoelectric effect in the quantum well. Therefore, a two-dimensional electron gas will be formed at the interface between the second nitride layer 42 and the first nitride layer 41 and the second nitride layer 42, thereby forming an electrical connection path to enable the second pole 332 and the first pole 331 to achieve electrical signal connection.

[0063] Optionally, Figure 5 is a partial structural schematic diagram of another storage device provided by an embodiment of the present invention. Refer to Figure 1 and Figure 5 , the semiconductor layer 40 further includes a third nitride layer 43; the third nitride layer 43 is located on the side of the second nitride layer 42 away from the first nitride layer 41.

[0064] Among them, the electron mobility of the third nitride layer 43 is different from that of the second nitride layer 42. The third nitride layer 43 includes materials such as gallium nitride and can be set according to actual needs, and no specific limitation is made here.

[0065] Specifically, by providing the third nitride layer 43 in the semiconductor layer 40 and making the electron mobility in the second nitride layer 42 different from that of the third nitride layer 43, so that the second nitride layer 42 and the third nitride layer 43 form a heterostructure, the conduction path in the switching transistor 33 is provided by the third nitride layer 43 and the second nitride layer 42. In addition, both the second nitride layer 42 and the third nitride layer 43 are provided on the side of the first nitride layer 41 away from the substrate 4 to reduce the lattice mismatch degree between adjacent two-layer materials, improve the preparation quality of the second nitride layer 42 and the third nitride layer 43, and further improve the device quality and working reliability of the switching transistor 33.

[0066] Optionally, Figure 6The following is a schematic structural diagram of another storage device provided by an embodiment of the present invention, as Figure 6 shown, the detection unit 50 includes a light-emitting element 51 and a current detection element 52. The first end of the light-emitting element 51 is electrically connected to the storage signal output terminal S2, the second end of the light-emitting element 51 is electrically connected to the current input terminal of the current detection element 52, the current output terminal of the current detection element 52 is electrically connected to the ground terminal GND, and the current signal output terminal of the current detection element 52 is electrically connected to the detection signal input terminal.

[0067] Among them, the light-emitting element 51 includes a light-emitting diode, etc., and the current detection element 52 includes an ammeter, etc., which can be set according to actual needs and are not specifically limited here.

[0068] Specifically, when the storage unit 20 is in a high-impedance storage state, the electrical signal received by the first end of the light-emitting element 51 is small, and the light-emitting element 51 cannot emit light. At this time, no current flows through the light-emitting element 51 or the current flowing through the light-emitting element 51 is small, and the current signal obtained by the current detection element 52 is also small. When the storage unit 20 is in a low-impedance storage state, the electrical signal received by the first end of the light-emitting element 51 is large, which can drive the light-emitting element 51 to emit light. At this time, there is current in the light-emitting element 51, and the current detection element 52 can obtain a certain current signal. The current detection element 52 transmits the obtained current signal to the control unit 10, so that the control unit 10 controls the switch unit 30 to be in a conducting state or a cutoff state according to the magnitude of the current signal, improving the control reliability of the control unit 10 over each switch unit 30, and further improving the storage reliability of the storage device.

[0069] Optionally, Figure 7 The following is a partial structural schematic diagram of a storage device provided by an embodiment of the present invention. Referring to Figure 1 and Figure 7 , the second pole 332 of the switching transistor 33 is multiplexed as the first electrode 21 to reduce the overall size of the storage device and make the storage device thinner and lighter.

[0070] Optionally, Figure 8 The following is a partial structural schematic diagram of another storage device provided by an embodiment of the present invention, as Figure 8 shown, the storage device further includes a buffer layer 45 located between the substrate 4 and the switch unit 30.

[0071] Specifically, the material of the buffer layer 45 can be set according to the material of the switching unit 30. Exemplarily, when the material of the switching unit 30 adjacent to the substrate 4 includes nitrides, the buffer layer 45 can include nitride materials such as gallium nitride to solve the lattice mismatch problem when adjacent materials are different. The buffer layer 45 can provide a better growth interface for the switching unit 30, enabling the material of the switching unit 30 to have better crystal quality, improving the preparation quality of the switching unit 30, and further improving the device performance and working reliability of the switching unit 30.

[0072] In an alternative embodiment, Figure 9 is a schematic structural diagram of a process for manufacturing a partial storage device provided by an embodiment of the present invention. As Figure 9 shown, first, a substrate 4 is provided. The substrate 4 includes materials such as silicon or silicon carbide. The buffer layer 45, the first nitride layer 41, the second nitride layer 42, and the third nitride layer 42 are sequentially grown on one side of the substrate 4 by metal organic chemical vapor deposition. The buffer layer 45, the first nitride layer 41, and the third nitride layer 42 all include gallium nitride materials. The silicon doping content in the buffer layer 45 is less than 10^18 / cm 3 , the thickness of the buffer layer 45 is set in the range of 1 μm - 2 μm, the thickness of the first nitride layer 41 is set in the range of 10 nm - 20 nm, the second nitride layer 42 includes aluminum gallium nitride material, the aluminum content in the second nitride layer 42 is set in the range of 20% - 40%, the thickness of the second nitride layer 42 is set in the range of 10 nm - 30 nm, and the silicon doping content in the third nitride layer 43 is 10^18 / cm 3 -10^19 / cm 3, by increasing the concentration of silicon doping in the third nitride layer 43, the carrier concentration in the third nitride layer 43 is increased, thereby improving the electron mobility of the third nitride layer 43; a whole-layer passivation material layer 440 is formed on the side of the third nitride layer 43 away from the substrate 4 by using plasma-enhanced chemical vapor deposition technology. The passivation material layer 440 includes Si3N4 material, and the thickness of the passivation material layer 440 is set in the range of 200 nm - 300 nm; a first electrode opening structure 441, a second electrode opening structure 442, and a third electrode opening structure 443 are etched in the passivation material layer 440 by using reactive ion etching technology to form a passivation layer 44 including a plurality of opening structures and passivation structures 444 respectively surrounding each opening structure; a first electrode 331 is formed in the first electrode opening structure 441 by using magnetron sputtering technology or electron beam evaporation technology, and a second electrode 332 is formed in the second electrode opening structure 442. The first electrode 331 and the second electrode 332 include nickel or copper materials; a gate G is formed in the third electrode opening structure 443 by using electron beam evaporation technology. The gate G includes materials such as nickel, aluminum, or metal alloy; a first insulating layer 23, a third conductive layer 25, and a second insulating layer 24 are sequentially grown on the side of the second electrode 332 away from the substrate 4 by using laser etching or magnetron sputtering technology. The first insulating layer 23 and the second insulating layer 24 include materials such as aluminum nitride, silicon nitride, or boron nitride, and the third conductive layer 25 includes materials such as copper or silver. The thickness of the third conductive layer 25 is 3 nm. The second electrode 22 includes electrode materials such as tungsten or copper. The size of the insulating layer 26 can be the same as the size of the third electrode 23. Exemplarily, the sizes of the first insulating layer 23 and the second electrode 332 are both 1 μm × 3 μm. Finally, annealing is performed at a preset temperature to enhance the electrical connection stability and reliability between the memory cells and the switching units in the memory device, and improve the manufacturing reliability of the memory device.

[0073] Note that the above is only the preferred embodiment of the present invention and the applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein. Various obvious changes, re-adjustments, mutual combinations, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A storage device, characterized in that: include: A control unit, a plurality of storage units, a plurality of switch units arranged in one-to-one correspondence with each of the storage units, and a plurality of detection units arranged in one-to-one correspondence with each of the storage units; The storage unit comprises a storage signal input terminal and a storage signal output terminal; The switch unit comprises a switch input terminal, a switch output terminal and a switch control terminal; part of the switch input terminals are electrically connected to the same storage signal providing terminal, and the switch output terminal is electrically connected to the storage signal input terminal; The detection unit comprises a detection signal providing end and a detection signal output end, and the detection signal providing end is electrically connected to the storage signal output end; The control unit includes multiple storage signal writing terminals, multiple detection signal input terminals and multiple switch signal output terminals, each of the storage signal writing terminals is electrically connected to each of the storage signal providing terminals, each of the detection signal output terminals is electrically connected to each of the detection signal input terminals, and each of the switch signal output terminals is electrically connected to each of the switch control terminals.

2. The storage device according to claim 1, characterized in that include: substrate; The switch unit is located at one side of the substrate; The storage unit is located at a side of the switch unit facing away from the substrate.

3. The storage device according to claim 2, characterized in that: The storage unit includes a memristor; The memristor comprises a first electrode, a first insulating layer, a third conductive layer, a second insulating layer and a second electrode which are stacked in sequence; The first electrode is electrically connected to the switch output terminal, and the second electrode is electrically connected to the detection signal providing terminal.

4. The storage device according to claim 3, characterized in that: The switch unit includes a switch transistor; The first electrode of the switch transistor is electrically connected to the storage signal supply terminal, the second electrode of the switch transistor is electrically connected to the first electrode, and the gate of the switch transistor is electrically connected to the switch signal output terminal.

5. The storage device according to claim 4, characterized in that: Also includes: A semiconductor layer, located on one side of the substrate; the semiconductor layer includes an active layer of the switch transistor; A passivation layer, located on a side of the semiconductor layer facing away from the substrate; The passivation layer comprises a plurality of opening structures and passivation structures surrounding each of the opening structures; The opening structure includes a first pole opening structure, a second pole opening structure and a gate opening structure; The gate opening structure is located between the first gate opening structure and the second gate opening structure; A first conductive layer, including a gate of the switch transistor located within the gate opening structure; The second conductive layer includes a first electrode of the switch transistor located in the first electrode opening structure, and a second electrode of the switch transistor located in the second electrode opening structure.

6. The storage device according to claim 5, characterized in that: The semiconductor layer includes a first nitride layer and a second nitride layer stacked; The second nitride layer is located on a side of the first nitride layer facing away from the substrate.

7. The storage device according to claim 6, characterized in that: The semiconductor layer further includes: a third nitride layer; The third nitride layer is located on a side of the second nitride layer facing away from the first nitride layer.

8. The storage device according to claim 5, characterized in that: The detection unit includes: a light emitting element and a current detection element; The first end of the light-emitting element is electrically connected to the storage signal output end, the second end of the light-emitting element is electrically connected to the current input end of the current detection element, the current output end of the current detection element is electrically connected to the ground end, and the current detection signal output end of the current detection element is electrically connected to the detection signal input end.

9. The storage device according to claim 5, characterized in that: The second electrode of the switch transistor is multiplexed as the first electrode.

10. The storage device according to claim 2, characterized in that: Also includes: A buffer layer is located between the substrate and the switch unit.

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