Package structure with dam structure

Abstract

The utility model provides a packaging structure which comprises a packaging substrate, a semiconductor device, a plurality of passive devices, a cover body and a dam structure. A semiconductor device is disposed on and electrically connected to a package substrate. A plurality of passive devices are disposed on a package substrate, wherein a semiconductor device is surrounded by the plurality of passive devices. A lid is disposed on the package substrate, and the lid covers the semiconductor device and the plurality of passive devices. A dam structure is disposed between the package structure and the cover, wherein the dam structure covers the plurality of passive devices and laterally encloses the semiconductor device.

Description

Technical Field

[0001] The utility model relates to a packaging structure with a dam structure. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. Generally, this increase in integration density comes from the repeated reduction of the minimum feature size, which enables more components to be integrated into a given area. With the recent increasing demands for minimization, higher speed, greater bandwidth, and lower power consumption and latency, the demand for large-scale and reliable electronic devices using advanced semiconductor die packaging technologies has increased. For large-scale electronic devices, the reliability issue of packaging is a problem to be solved. Summary of the Utility Model

[0003] The utility model provides a packaging structure, which includes a packaging substrate, a semiconductor device, a plurality of passive devices, a cover body, and a dam structure. The semiconductor device is configured on the packaging substrate and electrically connected thereto. The plurality of passive devices are configured on the packaging substrate, and the semiconductor device is surrounded by the plurality of passive devices. The cover body is configured on the packaging substrate, and the cover body covers the semiconductor device and the plurality of passive devices. The dam structure is configured between the packaging substrate and the cover body, and the dam structure covers the plurality of passive devices and laterally encloses the semiconductor device. In some embodiments, the semiconductor device includes an intermediate circuit substrate, at least one semiconductor die, and an insulation encapsulation, wherein the intermediate circuit substrate is configured on the packaging substrate and electrically connected thereto, at least one semiconductor die is configured on the intermediate circuit substrate and electrically connected thereto, and the insulation encapsulation is configured on the intermediate circuit substrate and laterally encapsulates at least one semiconductor die. In some embodiments, the packaging structure further includes a thermal interface material disposed between the semiconductor device and the cover body. In some embodiments, the packaging structure further includes a metal layer between the thermal interface material and the semiconductor device. In some embodiments, the thermal interface material includes a metal thermal interface material, and the metal thermal interface material coats the top surface and a plurality of sidewalls of the semiconductor device. In some embodiments, the metal thermal interface material contacts the dam structure. In some embodiments, the cavity between the packaging substrate and the cover body includes an internal region between the semiconductor device and the dam structure and an external region between the dam structure and the cover body. In some embodiments, the internal region is an airtight region, the external region is an open region, and the internal structure and the external structure are spaced apart by the dam structure. In some embodiments, the dam structure contacts the plurality of passive devices.

[0004] The present utility model provides a packaging structure, which includes a packaging substrate, a semiconductor device, a cover body, and a dam structure. The semiconductor device is disposed on the packaging substrate and electrically connected thereto. The cover body is disposed on the packaging substrate, and the cover body covers the semiconductor device. The dam structure is disposed between the packaging substrate and the cover body, wherein the dam structure includes a plurality of main portions extending along a plurality of sidewalls of the semiconductor device, and a plurality of extending portions contacting a plurality of ends of the plurality of main portions, wherein the plurality of main portions and the plurality of extending portions laterally enclose the semiconductor device. In some embodiments, a first minimum distance between the plurality of main portions and a plurality of sidewalls of the cover body is greater than a second minimum distance between the plurality of extending portions and the plurality of sidewalls of the cover body. In some embodiments, the packaging structure further includes a plurality of passive devices disposed on the packaging substrate, wherein the semiconductor device is surrounded by the plurality of passive devices, and the plurality of main portions extend between the semiconductor device and the plurality of passive devices. In some embodiments, the plurality of passive devices include a plurality of groups of passive devices, and a first group among the plurality of groups of passive devices and a second group among the plurality of groups of passive devices are laterally spaced apart via one of the plurality of extending portions. In some embodiments, the plurality of groups of passive devices are distributed in a plurality of outer regions surrounded by the plurality of extending portions. In some embodiments, the plurality of regions surrounded by the plurality of extending portions are distributed near a plurality of corners of the semiconductor device and / or a plurality of midpoints of a plurality of sidewalls of the semiconductor device.

[0005] The present utility model provides a packaging structure, which includes a packaging substrate, a semiconductor device, a cover body, and a dam structure. The semiconductor device is disposed on the packaging substrate and electrically connected thereto. The cover body is disposed on the packaging substrate, and the cover body covers the semiconductor device. The dam structure is disposed between the packaging substrate and the cover body, wherein the dam structure includes: a plurality of main portions extending along a plurality of sidewalls of the semiconductor device; and a plurality of extending portions laterally extending from a plurality of ends of the plurality of main portions to a plurality of inner sidewalls of the cover body, and wherein the plurality of main portions and the plurality of extending portions laterally enclose the semiconductor device. In some embodiments, the packaging structure further includes a plurality of groups of passive devices disposed on the packaging substrate, wherein the semiconductor device is surrounded by the plurality of passive devices, and the plurality of main portions extend between the semiconductor device and the plurality of groups of passive devices. In some embodiments, a first group among the plurality of groups of passive devices and a second group among the plurality of groups of passive devices are laterally spaced apart via one of the plurality of extending portions. In some embodiments, the plurality of regions surrounded by the plurality of extending portions do not have the plurality of groups of passive devices. In some embodiments, a first minimum distance between the plurality of main portions and a plurality of sidewalls of the cover body is greater than a second minimum distance between the plurality of extending portions and the plurality of sidewalls of the cover body. Description of the Drawings

[0006] The various aspects of the present disclosure will be best understood when the following detailed description is read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 4 Some embodiments in accordance with the present disclosure are illustrated as cross-sectional views of a process flow for fabricating a Chip-on-Wafer-on-Substrate (CoWoS) structure.

[0008] Figure 5 Some embodiments in accordance with the present disclosure are illustrated as top views of the association between a dam structure and a plurality of passive devices mounted on a package substrate.

[0009] Figure 6 Some alternative embodiments in accordance with the present disclosure are illustrated as cross-sectional views of a Chip-on-Wafer-on-Substrate (CoWoS) structure.

[0010] Figures 7 to 10 Some alternative embodiments in accordance with the present disclosure are illustrated as cross-sectional views of a process flow for fabricating a Chip-on-Wafer-on-Substrate (CoWoS) structure.

[0011] Figure 11 Some alternative embodiments in accordance with the present disclosure are illustrated as top views of the association between a dam structure and a plurality of passive devices mounted on a package substrate.

[0012] Figure 12 Some other embodiments in accordance with the present disclosure are illustrated as cross-sectional views of a Chip-on-Wafer-on-Substrate (CoWoS) structure. Detailed Description

[0013] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one component or feature shown in the figures to another component or feature. Except for the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the components in use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0015] Other features and processes may also be included. For example, test structures may be included to assist in the verification testing of 3D packaging or 3D IC devices. For instance, the test structure may include test pads formed in a redistribution layer or on a substrate, allowing the use of testing, probing, and / or probe cards for 3D packaging or 3D ICs and the like. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in conjunction with test methods that include intermediate verification of known good die to increase yield and reduce costs.

[0016] To improve the reliability of the chip-on-wafer-on-substrate (CoWoS) structure, a plurality of novel dam structures will be provided in the chip-on-wafer-on-substrate (CoWoS) structure according to multiple embodiments. Throughout the various viewpoints and schematic embodiments, the same reference numerals are used to designate the same components. It should be understood that even though the chip-on-wafer-on-substrate (CoWoS) structure is used as an example to explain the concepts of the embodiments of the present disclosure, the embodiments of the present disclosure can be easily applied to other similar dam structure designs.

[0017] Figures 1 to 4 Cross-sectional views of a process flow for manufacturing a chip-on-wafer-on-substrate (CoWoS) structure are illustrated according to some embodiments of the present disclosure.

[0018] Please refer to Figure 1, a packaging structure 100 is provided, which includes a packaging substrate 110, a semiconductor device 120, and a plurality of passive components 130. The semiconductor device 120 and the plurality of passive components 130 are mounted on the top surface of the packaging substrate 110. The semiconductor device 120 and the plurality of passive components 130 are electrically connected to the packaging substrate 110. The semiconductor device 120 may include at least one semiconductor die 121 and an insulation encapsulation 122, and the insulation encapsulation 122 laterally encapsulates at least one semiconductor die 121. The semiconductor device 120 may further include an interposer wiring substrate 123, a plurality of conductive terminals 124, a dielectric layer 125, a plurality of conductive terminals 126, and a dielectric layer 127. For example, the packaging structure 100 including the packaging substrate 110, the semiconductor device 120, and the plurality of passive components 130 is called a chip-on-wafer-on-substrate (CoWoS) structure.

[0019] As Figure 1As shown, the encapsulation substrate 110 may be a printed circuit board or other suitable type of wiring substrate. At least one semiconductor die 121 may be or include at least one first semiconductor die 121a and at least one second semiconductor die 121b. The at least one first semiconductor die 121a and the at least one second semiconductor die 121b are arranged side-by-side on an interposer wiring substrate 123. In some embodiments, the first semiconductor die 121a includes a High-Bandwidth-Memory (HBM) cube, the High-Bandwidth-Memory cube includes a plurality of stacked high-bandwidth memory dies and a control die for controlling the operation of the stacked plurality of high-bandwidth memory dies, and the second semiconductor die 121b includes a System-on-Chip die (SoC die). In some other embodiments, the first semiconductor die 121a and the second semiconductor die 121b may be dies of a System on Integrated Circuit (SoIC) with multiple functions. The first semiconductor die 121a and the second semiconductor die 121b are arranged on the interposer wiring substrate 123 and are electrically connected to the interposer wiring substrate 123 through a plurality of conductive terminals 124. Through a Chip-on-Wafer (CoW) bonding process, the plurality of semiconductor dies 121 are bonded to the interposer wiring substrate 123 through the plurality of conductive terminals 124. The conductive terminals 124 are arranged between the semiconductor die 121 and the interposer wiring substrate 123. The plurality of conductive terminals 124 may be or include a plurality of micro-bumps for electrically connecting to the plurality of semiconductor dies 121 and the interposer wiring substrate 123. A dielectric layer 125 is arranged on the interposer wiring substrate 123. The dielectric layer 125 is arranged between the plurality of semiconductor dies 121 and the interposer wiring substrate 123 to laterally encapsulate the plurality of conductive terminals 124. In some embodiments, the dielectric layer 125 includes an underfill material, a molding compound, a polymer, an oxide material, a nitride material, or a combination thereof. Therefore, the shear stress borne by the plurality of conductive terminals 124 can be minimized through the dielectric layer, and the reliability of the plurality of conductive terminals 124 can be improved through the dielectric layer. The material of the dielectric layer 125 may be or include an epoxy resin or other suitable dielectric material.

[0020] As Figure 1 shown, an insulating encapsulation 122 is disposed on an intermediate circuit substrate 123 to laterally encapsulate a plurality of semiconductor dies 121 and a dielectric layer 125. A plurality of top surfaces (e.g., a plurality of back surfaces) of the plurality of semiconductor dies 121 are substantially flush with the top surface of the insulating encapsulation 122, and a plurality of sidewalls of the insulating encapsulation 122 are substantially aligned with a plurality of sidewalls of the intermediate circuit substrate 123. A plurality of conductive terminals 126 are disposed on the bottom surface of the intermediate circuit substrate 123, and the intermediate circuit substrate 123 is electrically connected to the package substrate 110 through the plurality of conductive terminals 126. The plurality of conductive terminals 126 may be or include a plurality of Controlled Collapse Chip Connection bumps (C4 bumps) for electrically connecting to the intermediate circuit substrate 123 and the package substrate 110. A dielectric layer 127 is disposed on the package substrate 110. The dielectric layer 127 is disposed between the intermediate circuit substrate 123 and the package substrate 110 to laterally encapsulate the plurality of conductive terminals 126. In some embodiments, the dielectric layer 127 includes an underfill material, a molding compound, a polymer, an oxide material, a nitride material, or a combination thereof. Furthermore, the dielectric layer 127 covers a plurality of sidewalls of the intermediate circuit substrate 123 and a lower portion of a plurality of sidewalls of the insulating encapsulation 122.

[0021] As Figure 1As shown, the semiconductor die 121 is electrically connected to the package substrate 110 through the intermediate circuit substrate 123, a plurality of conductive terminals 124, and a plurality of conductive terminals 126. The intermediate circuit substrate 123 may include a silicon interposer, an organic interposer, or other suitable intermediate circuit substrates. The intermediate circuit substrate 123 may include a plurality of conductive wirings formed thereon. Furthermore, the intermediate circuit substrate 123 may include a plurality of conductive through vias formed therein. The intermediate circuit substrate 123 may be a silicon intermediate circuit substrate with a fine line pitch (e.g., sub-μm pitch), an organic interposer with a less aggressive fine line pitch (e.g., 4-μm pitch), or an intermediate circuit substrate with a Local Silicon Interconnect (LSI) die. In an embodiment where the intermediate circuit substrate 123 is a silicon intermediate circuit substrate, the CoWoS package structure 100 is referred to as a CoWoS-S package; in an embodiment where the intermediate circuit substrate 123 is an organic intermediate circuit substrate, the CoWoS package structure 100 is referred to as a CoWoS-R package; in an embodiment where the intermediate circuit substrate 123 is an intermediate circuit substrate with a Local Silicon Interconnect (LSI) die, the CoWoS package structure 100 is referred to as a CoWoS-L package.

[0022] In some embodiments, the semiconductor device 120 may further include a backside metal layer 128 disposed on the top surfaces (e.g., back surfaces) of the plurality of semiconductor dies 121 and the top surface of the insulation encapsulation 122. The backside metal layer 128 covers and contacts the top surfaces (e.g., back surfaces) of the plurality of semiconductor dies 121 and the top surface of the insulation encapsulation 122. The backside metal layer 128 may be a single-layer metal structure or a multi-layer metal structure. The backside metal layer 128 may be or include a copper layer or other metal layers with a favorable thermal conductivity.

[0023] The passive device 130 can be a surface mounted device (SMD) mounted on the top surface of the package substrate 110. The plurality of passive devices 130 can be or include capacitors, inductors, resistors, or the like. The passive device 130 is laterally spaced from the semiconductor device 120. In other words, the plurality of passive devices 130 are spaced from the dielectric layer 180 of the insulating encapsulation 122 of the semiconductor device 120 and do not contact it.

[0024] Please refer to Figure 2 , the adhesive 140 is applied on the package substrate 110. The material of the adhesive 140 can be or include a thermally conductive adhesive, a silicone based adhesive, or an epoxy resin-based adhesive. The material of the adhesive 140 can be or include a rubber based material with a curing promoting material. In some embodiments, the adhesive 140 is applied on the top surface of the package substrate 110. Additionally, the adhesive 140 can include a plurality of separate adhesive patterns.

[0025] In some embodiments, a thermal interface material (TIM) 129 is applied above the top surfaces (e.g., the plurality of back surfaces) of the plurality of semiconductor dies 121 and the top surface of the insulating encapsulation 122. For example, the thermal interface material 129 is applied on the top surface of the backside metal layer 128 such that the backside metal layer 128 is disposed between the thermal interface material 129 and the semiconductor device 120. The thermal interface material 129 can be or include a deformable and / or flowable material during the bonding process of the lid 160 (as Figure 4 shown) and the semiconductor device 120. For example, the thermal interface material 129 is a metal thermal interface material or the like.

[0026] As Figure 2 shown, a dam structure 150 is formed on the top surface of the package substrate 110. The dam structure 150 can be wide enough to cover the plurality of passive devices 130. The plurality of passive devices 130 can be sealed by the dam structure 150. The dam structure 150 contacts the plurality of passive devices 130. The dam structure 150 can be laterally spaced from the semiconductor device 120. In some embodiments, the height of the dam structure 150 is substantially flush with the top surface of the thermal interface material 129. In some other embodiments, the height of the dam structure 150 is higher than the top surface of the thermal interface material 129.

[0027] The dam structure 150 may have a bottom width W B , a middle width W M and a top width W T , where the middle width W of the dam structure 150 M is greater than the bottom width W of the dam structure 150 B and the top width W of the dam structure 150 T . Furthermore, the bottom width W of the dam structure 150 B may be different from the top width W of the dam structure 150 T . In some embodiments, the bottom width W of the dam structure 150 B is greater than the top width W of the dam structure 150 T ; in some alternative embodiments, the bottom width W of the dam structure 150 B is less than the top width W of the dam structure 150 T . To properly cover and seal the plurality of passive devices 130, the bottom width W of the dam structure 150 B may be greater than the side dimension L1 of the passive device 130. The plurality of passive devices 130 may be arranged along a ring-shaped path, and the dam structure 150 may cover and extend along the ring-shaped path such that the plurality of passive devices 130 are covered and the semiconductor device 120 is laterally surrounded by the dam structure 150. Furthermore, the semiconductor device 120 is disposed within a region (e.g., an inner region) surrounded by the dam structure 150, and the adhesive 140 is distributed outside the region (e.g., an outer region) surrounded by the dam structure 150. The inner region surrounded by the dam structure 150 (i.e., the region where the semiconductor device 120 is disposed) is an air-tight region. In other words, the inner region surrounded by the dam structure 150 (i.e., the region where the semiconductor device 120 is disposed) is sealed by the dam structure 150 and is not in communication with the external environment.

[0028] Please refer to Figure 3, after forming the thermal interface material 129, the adhesive 140, and the dam structure 150, a cover 160 is provided and attached to the encapsulation structure 100 such that the thermal interface material 129 is disposed between the semiconductor device 120 and the cover 160. The cover 160 is attached to the encapsulation substrate 110 through the adhesive 140 formed therebetween such that the dam structure 150 is disposed between the encapsulation substrate 110 and the cover 160. The cover 160 is mounted on the top surface of the encapsulation substrate 110 to cover the dam structure 150, and a plurality of passive devices 130 are encapsulated by the dam structure 150 and the semiconductor device 120. The cover 160 includes a cover portion 162 and a lower end portion 164 extending from the bottom surface of the cover portion 162 to the encapsulation substrate 110. The cover portion 162 covers the plurality of semiconductor dies 121, the insulation encapsulation 122, the thermal interface material 129, and the dam structure 150. The bottom surface of the lower end portion 164 of the cover 160 is attached to the encapsulation substrate 110 through the adhesive 140, and the cover portion 162 of the cover 160 is attached to the semiconductor device 120 through the thermal interface material 129. In some embodiments, a metal layer 170 is coated on the bottom surface of the cover portion 162, and the cover portion 162 of the cover 160 is attached to the semiconductor device 120 through the metal layer 170, the thermal interface material 129, and the backside metal layer 128.

[0029] The cover 160 may further include alignment notches (not shown in the figures) formed at the corners of the cover 160 such that the cover 160 can be assembled with the encapsulation substrate 110 precisely and quickly.

[0030] In some embodiments, where the adhesive 140 includes a plurality of separated adhesive patterns, the lower end portion 164 of the cover 160 adheres to and is spaced from the top surface of the encapsulation substrate 110 through the plurality of adhesive patterns of the adhesive 140. Since the adhesive 140 includes a plurality of adhesive patterns, the area between the dam structure 150 and the lower end portion 164 of the cover 160 (e.g., the outer area) is not airtight or a sealed area. In other words, the outer area between the dam structure 150 and the lower end portion 164 of the cover 160 communicates with the outside environment. As Figure 3 shown, in some embodiments, a cavity is located between the encapsulation substrate 110 and the cover 160, and the cavity includes an inner area between the semiconductor device 120 and the dam structure 150; and an outer area between the dam structure 150 and the lower end portion 164 of the cover 160. For example, the inner area is an airtight area, the outer area is an open area, and the inner area is spaced from the outer area through the dam structure 150.

[0031] In some embodiments, the thermal interface material 129 includes a metallic thermal interface material, and the metallic thermal interface material covers the top surface and a plurality of sidewalls of the semiconductor device 120. In some embodiments, the metallic thermal interface material contacts the dam structure 150.

[0032] As Figure 3 shown, when the cover 160 is provided and pressed on the encapsulation structure 100, the covered portion 162 of the cover 160 presses on the thermal interface material 129, causing the thermal interface material 129 to deform and flow outward. The plurality of deformed portions 129a of the thermal interface material 129 can flow laterally and downward to cover the plurality of sidewalls of the semiconductor device 120. In some embodiments, the plurality of deformed portions 129a of the thermal interface material 129 contact the dielectric layer 127. In some other embodiments, the plurality of deformed portions 129a of the thermal interface material 129 contact the dielectric layer 127 and the dam structure 150. In some embodiments, the region enclosed by the covered portion 162 of the cover 160, the dam structure 150, the encapsulation substrate 110, and the semiconductor device 120 is filled with the plurality of deformed portions 129a of the thermal interface material 129. In some alternative embodiments, the region enclosed by the covered portion 162 of the cover 160, the dam structure 150, the encapsulation substrate 110, and the semiconductor device 120 is partially filled with the plurality of deformed portions 129a of the thermal interface material 129.

[0033] As Figure 3 shown, when the cover 160 is provided and pressed on the encapsulation structure 100, the dam structure 150 is pressed by the covered portion 162 of the cover 160, causing the dam structure 150 to deform and the top end of the dam structure to adhere to the bottom surface of the covered portion 162 of the cover 160. In some embodiments, the dam structure 150 is laterally spaced from the semiconductor device 120, and the plurality of deformed portions 129a of the thermal interface material 129 contact the dielectric layer 127 and the dam structure 150.

[0034] Please refer to Figure 4, a plurality of conductive terminals 112 are formed on the bottom surface of the package substrate 110. The plurality of conductive terminals 112 formed on the bottom surface of the package substrate 110 can be a plurality of solder balls arranged in an array, and for example, the solder balls can be formed by a reflowing process after a ball mount process. In some embodiments, where the conductive terminal 112 includes a solder ball, the package substrate 110 is a ball grid array (BGA) circuit board. After the plurality of conductive terminals 112 are formed on the bottom surface of the package substrate 110, a singulation process can be performed to cut the package substrate 110 to obtain a plurality of singulated semiconductor devices as shown in Figure 4 as shown.

[0035] Figure 5 A top view showing the association between the dam structure 150 and the plurality of passive devices 130 mounted on the package substrate 110 according to some embodiments of the present disclosure.

[0036] Please refer to Figure 4 and Figure 5 , the semiconductor device 120 including a plurality of semiconductor dies 121a and 121b and laterally encapsulated by an insulating encapsulation 122 is surrounded by a plurality of passive devices 130 and a dam structure 150. The plurality of passive devices 130 are arranged along an annular path (e.g., a rectangular ring-shaped path), and the dam structure 150 can cover and extend along the annular path such that the plurality of passive devices 130 are covered by the dam structure 150. To properly cover and seal the plurality of passive devices 130, the bottom width W of the dam structure 150 B can be greater than the side dimension L1 of the passive device 130. As shown in the right part of Figure 5 , the side distance L2 between the semiconductor device 120 and the lower end portion 164 of the cover 160 is greater than the bottom width W of the dam structure 150 B , and the bottom width W of the dam structure 150 B is greater than the side dimension L1 of the passive device 130.

[0037] Because the bottom width W of the dam structure 150 B is greater than the side dimension L1 of the passive device 130, the dam structure 150 is strong enough to prevent the bleeding of the plurality of deformed portions 129a of the thermal interface material 129 (as shown in Figure 3 ).

[0038] Figure 6Some alternative embodiments according to the present disclosure are illustrated as a cross-section of a chip-on-wafer-on-substrate (CoWoS) structure.

[0039] Please refer to Figures 4 to 6 , except for the geometry of the dam structure 250, the encapsulation structure 200 shown in Figure 6 is the same as the encapsulation structure 100 shown in Figure 4 . As shown in Figure 6 , the dam structure 250 may have a bottom width W B , a middle width W M , and a top width W T , wherein the middle width W M of the dam structure 250 is less than the bottom width W B of the dam structure 250 and the top width W T of the dam structure 250. Furthermore, the bottom width W B of the dam structure 250 may be different from the top width W T of the dam structure 250. In some embodiments, the bottom width W B of the dam structure 250 is greater than the top width W T of the dam structure 250; in some embodiments, the bottom width W B of the dam structure 250 is less than the top width W T of the dam structure 250. In order to properly cover and seal the plurality of passive devices 130, the bottom width W B of the dam structure 250 may be greater than the side dimension L1 of the passive device 130.

[0040] Figures 7 to 10 Some alternative embodiments according to the present disclosure are illustrated as a cross-section of a process flow for manufacturing a chip-on-wafer-on-substrate (CoWoS) structure. Figure 11 Some alternative embodiments according to the present disclosure are illustrated as a top view of the relationship between the dam structure 150 and the plurality of passive devices 130 mounted on the package substrate 110.

[0041] Please refer to Figures 1 to 4 and Figures 7 to 10 , except that the dam structure 350 in the encapsulation structure 300 is formed on the package substrate 110 instead of covering the plurality of passive devices 130, the process flow shown in Figures 7 to 10 is the same as the process flow shown in Figures 1 to 4 .

[0042] Please refer to Figures 8 to 11, the dam structure 350 of the present disclosure includes a plurality of main portions 350a and a plurality of extending portions 350b. The plurality of main portions 350a extend along a plurality of sidewalls of the semiconductor device 120, the plurality of extending portions 350b connect a plurality of ends of the plurality of main portions 350a, and the plurality of main portions 350a and the plurality of extending portions 350b laterally enclose the semiconductor device 120. The plurality of extending portions 350b may extend laterally from the plurality of ends of the plurality of main portions 350a to a plurality of inner sidewalls of the cover 160. The plurality of main portions 350a extend between the semiconductor device 120 and the plurality of passive devices 130. A first minimum distance between the plurality of main portions 350a and a plurality of inner sidewalls of a lower end portion 164 of the cover 160 is greater than a second minimum distance between the plurality of extending portions 350b and the plurality of inner sidewalls of the lower end portion 164 of the cover 160. In some embodiments, the plurality of passive devices 130 includes a plurality of passive device groups 130a, 130b, 130c, 130d, and 130e; and a first group 130a among the plurality of passive device groups 130a, 130b, 130c, 130d, and 130e is laterally spaced from a second group 130b among the plurality of passive device groups 130a, 130b, 130c, 130d, and 130e via one of the plurality of extending portions 350b. The plurality of passive devices 130 may be distributed in a plurality of outer regions surrounded by the plurality of extending portions 350b of the dam structure 350. Furthermore, the plurality of regions surrounded by the plurality of extending portions 350b are distributed near a plurality of corners of the semiconductor device 120 and / or midpoints of a plurality of sidewalls of the semiconductor device 120.

[0043] As Figure 11As shown, the passive device group 130a is laterally spaced from the passive device group 130b via the extension portion 350b1; the passive device group 130b is laterally spaced from the passive device group 130c via the extension portion 350b2; the passive device group 130c is laterally spaced from the passive device group 130d via the extension portion 350b3; the passive device group 130d is laterally spaced from the passive device group 130e via the extension portion 350b4; and the passive device group 130e is laterally spaced from the passive device group 130a via the extension portion 350b5. The passive device group 130a is arranged along a straight path substantially parallel to the main portion 350a2; the passive device group 130b is arranged along a straight path substantially parallel to the main portion 350a3; the passive device groups 130c and 130d are arranged along a straight path substantially parallel to the main portion 350a4; and the passive device group 130e is arranged along a straight path substantially parallel to the main portion 350a1. Furthermore, the main portion 350a1 extends along a straight path between the semiconductor device 120 and the passive device group 130e; the main portion 350a2 extends along a straight path between the semiconductor device 120 and the passive device group 130a; the main portion 350a3 extends along a straight path between the semiconductor device 120 and the passive device group 130b; the main portion 350a4 extends along a straight path between the semiconductor device 120 and the passive device group 130c; and the main portion 350a5 extends along a straight path between the semiconductor device 120 and the passive device group 130d.

[0044] A plurality of regions surrounded by the plurality of extension portions 350b1, 350b2, 350b3, and 350b5 are distributed near the plurality of corners of the semiconductor device 120. Furthermore, the region surrounded by the extension portion 350b4 is distributed near the midpoint of the sidewall of the semiconductor device 120. In some other embodiments, the plurality of extension portions 350b1, 350b2, 350b3, 350b4, and 350b5 exhibit different shapes, as shown in the right portion of Figure 11 .

[0045] Since Figure 7 , Figure 9 and Figure 10 have the same process details as Figure 1 , Figure 3 and Figure 4 , the detailed description of Figure 7 , Figure 9 and Figure 10 is omitted.

[0046] Figure 12 Some other embodiments according to the present disclosure are illustrated as a cross-sectional view of a chip-on-wafer-on-substrate (CoWoS) structure.

[0047] Please refer to Figures 10 to 12 , except for the geometry of the dam structure 350, the encapsulation structure 400 shown in Figure 12 is the same as the encapsulation structure 300 shown in Figure 10 . As shown in Figure 12 , the dam structure 450 may have a bottom width W B , a middle width W M and a top width W T , where the middle width W M of the dam structure 450 is less than the bottom width W B of the dam structure 450 and the top width W T of the dam structure 450. Furthermore, the bottom width W B of the dam structure 450 may be different from the top width W T of the dam structure 450. In some embodiments, the bottom width W B of the dam structure 450 is greater than the top width W T of the dam structure 450; in some alternative embodiments, the bottom width W B of the dam structure 450 is less than the top width W T of the dam structure 450. In order to properly cover and seal the plurality of passive devices 130, the bottom width W B of the dam structure 450 may be greater than the side dimension L1 of the plurality of passive devices 130.

[0048] In the above-mentioned embodiments, the plurality of extensions 350b1, 350b2, 350b3, 350b4 and 350b5 of the dam structure 350 may teach the plurality of deformed portions 129a of the thermal interface material 129 (as shown in Figure 9 ), so that the seepage of the plurality of deformed portions 129a of the thermal interface material 129 can be effectively prevented. Therefore, the reliability of the encapsulation structures 300 and 400 can be significantly improved.

[0049] According to some embodiments of the present disclosure, a packaging structure is provided, which includes a packaging substrate, a semiconductor device, a plurality of passive devices, a cover body, and a dam structure. The semiconductor device is disposed on the packaging substrate and electrically connected thereto. The plurality of passive devices are disposed on the packaging substrate, and the semiconductor device is surrounded by the plurality of passive devices. The cover body is disposed on the packaging substrate, and the cover body covers the semiconductor device and the plurality of passive devices. The dam structure is disposed between the packaging substrate and the cover body, and the dam structure covers the plurality of passive devices and laterally encloses the semiconductor device. In some embodiments, the semiconductor device includes an intermediate circuit substrate, at least one semiconductor die, and an insulating encapsulation, wherein the intermediate circuit substrate is disposed on the packaging substrate and electrically connected thereto, at least one semiconductor die is disposed on the intermediate circuit substrate and electrically connected thereto, and the insulating encapsulation is disposed on the intermediate circuit substrate and laterally encapsulates at least one semiconductor die. In some embodiments, the packaging structure further includes a thermal interface material disposed between the semiconductor device and the cover body. In some embodiments, the packaging structure further includes a metal layer between the thermal interface material and the semiconductor device. In some embodiments, the thermal interface material includes a metal thermal interface material, and the metal thermal interface material coats the top surface and a plurality of sidewalls of the semiconductor device. In some embodiments, the metal thermal interface material contacts the dam structure. In some embodiments, the cavity between the packaging substrate and the cover body includes an inner region between the semiconductor device and the dam structure and an outer region between the dam structure and the cover body. In some embodiments, the inner region is an airtight region, the outer region is an open region, and the inner structure and the outer structure are spaced apart via the dam structure. In some embodiments, the dam structure contacts the plurality of passive devices.

[0050] According to some other embodiments of the present disclosure, a packaging structure is provided, which includes a packaging substrate, a semiconductor device, a cover body, and a dam structure. The semiconductor device is disposed on the packaging substrate and electrically connected thereto. The cover body is disposed on the packaging substrate, and the cover body covers the semiconductor device. The dam structure is disposed between the packaging substrate and the cover body, wherein the dam structure includes a plurality of main portions extending along a plurality of sidewalls of the semiconductor device, and a plurality of extending portions contacting a plurality of ends of the plurality of main portions, wherein the plurality of main portions and the plurality of extending portions laterally enclose the semiconductor device. In some embodiments, a first minimum distance between the plurality of main portions and a plurality of sidewalls of the cover body is greater than a second minimum distance between the plurality of extending portions and the plurality of sidewalls of the cover body. In some embodiments, the packaging structure further includes a plurality of passive devices disposed on the packaging substrate, wherein the semiconductor device is surrounded by the plurality of passive devices, and the plurality of main portions extend between the semiconductor device and the plurality of passive devices. In some embodiments, the plurality of passive devices include a plurality of groups of passive devices, and a first group among the plurality of groups of passive devices and a second group among the plurality of groups of passive devices are laterally spaced apart via one of the plurality of extending portions. In some embodiments, the plurality of groups of passive devices are distributed in a plurality of outer regions surrounded by the plurality of extending portions. In some embodiments, the plurality of regions surrounded by the plurality of extending portions are distributed near a plurality of corners of the semiconductor device and / or a plurality of midpoints of a plurality of sidewalls of the semiconductor device.

[0051] According to some other embodiments of the present disclosure, a packaging structure is provided, which includes a packaging substrate, a semiconductor device, a cover body, and a dam structure. The semiconductor device is disposed on the packaging substrate and electrically connected thereto. The cover body is disposed on the packaging substrate, and the cover body covers the semiconductor device. The dam structure is disposed between the packaging substrate and the cover body, wherein the dam structure includes: a plurality of main portions extending along a plurality of sidewalls of the semiconductor device; and a plurality of extending portions laterally extending from a plurality of ends of the plurality of main portions to a plurality of inner sidewalls of the cover body, and wherein the plurality of main portions and the plurality of extending portions laterally enclose the semiconductor device. In some embodiments, the packaging structure further includes a plurality of groups of passive devices disposed on the packaging substrate, wherein the semiconductor device is surrounded by the plurality of passive devices, and the plurality of main portions extend between the semiconductor device and the plurality of groups of passive devices. In some embodiments, a first group among the plurality of groups of passive devices and a second group among the plurality of groups of passive devices are laterally spaced apart via one of the plurality of extending portions. In some embodiments, the plurality of regions surrounded by the plurality of extending portions do not have the plurality of groups of passive devices. In some embodiments, a first minimum distance between the plurality of main portions and a plurality of sidewalls of the cover body is greater than a second minimum distance between the plurality of extending portions and the plurality of sidewalls of the cover body.

[0052] The foregoing has outlined the features of several embodiments in order that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as those introduced in the embodiments herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure and make various changes, substitutions, and alterations thereto.

Claims

1. A packaging structure, comprising: Package substrate; A semiconductor device, disposed on the packaging substrate and electrically connected to the packaging substrate; a plurality of passive components disposed on the packaging substrate, wherein the semiconductor device is surrounded by the plurality of passive components; A cover body, disposed on the packaging substrate, the cover body covers the semiconductor device and the plurality of passive components; as well as A dam structure is disposed between the packaging substrate and the cover, wherein the dam structure covers the plurality of passive components and laterally closes the semiconductor device.

2. The package structure according to claim 1, wherein the semiconductor device comprises: An intermediate circuit substrate, configured on the packaging substrate and electrically connected to the packaging substrate; At least one semiconductor bare chip is disposed on the intermediate circuit substrate and electrically connected to the intermediate circuit substrate; as well as The insulating package is disposed on the intermediate circuit substrate and laterally encapsulates the at least one semiconductor die. 3 . The package structure according to claim 1 , wherein the thermal interface material comprises a metal thermal interface material, and the metal thermal interface material covers a top surface and a plurality of sidewalls of the semiconductor device.

4. The package structure according to claim 1, wherein the cavity between the package substrate and the cover comprises: an interior region between the semiconductor device and the dam structure; as well as An external area between the dam structure and the cover. 5 . The packaging structure according to claim 4 , wherein the inner region is an airtight region, the outer region is an open region, and the inner region and the outer region are spaced apart from each other via the dam structure.

6. A packaging structure, comprising: Package substrate; A semiconductor device, disposed on the packaging substrate and electrically connected to the packaging substrate; A cover body, disposed on the packaging substrate, the cover body covers the semiconductor device; as well as A dam structure is disposed between the packaging substrate and the cover, wherein the dam structure comprises: a plurality of main portions extending along a plurality of sidewalls of the semiconductor device; as well as A plurality of extension portions are connected to the plurality of ends of the plurality of main portions, wherein the plurality of main portions and the plurality of extension portions laterally enclose the semiconductor device. 7 . The package structure according to claim 6 , wherein a first minimum distance between the plurality of main portions and the plurality of side walls of the cover is greater than a second minimum distance between the plurality of extension portions and the plurality of side walls of the cover. 8 . The package structure of claim 6 , wherein the plurality of passive components comprises a plurality of passive component groups, and a first group among the plurality of passive component groups is laterally spaced apart from a second group among the plurality of passive component groups via one of the plurality of extension portions.

9. A packaging structure, comprising: Package substrate; A semiconductor device, disposed on the packaging substrate and electrically connected to the packaging substrate; A cover body, disposed on the packaging substrate, the cover body covers the semiconductor device; as well as A dam structure is disposed between the packaging substrate and the cover, wherein the dam structure comprises: a plurality of main portions extending along a plurality of sidewalls of the semiconductor device; as well as A plurality of extension portions extend laterally from the plurality of ends of the plurality of main portions to the plurality of inner side walls of the cover, wherein the plurality of main portions and the plurality of extension portions laterally enclose the semiconductor device. 10 . The package structure according to claim 9 , wherein a plurality of regions surrounded by the plurality of extension portions are free of a plurality of passive device groups.

Images