Novel chip with glass passivation structure
By setting a first groove on the chip substrate and covering the glass passivation film and low-temperature oxide film, the problems of unstable performance of the existing chip and the influence of glass stress during scribing are solved, and the stable and reliable performance of the chip is achieved.
Patent Information
- Application Number
- CN202421646794.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-11
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-07-11
AI Technical Summary
The existing chips with passivation structures have problems such as poor product performance and unstable performance, and the stress of the glass during scribing will affect the reliability of the chip.
A chip with a new type of glass passivation structure is designed. By providing a first trench on both end edges of the upper part of the substrate, and covering the glass passivation film in the slope area of the trench, and covering the low-temperature oxide film in the flat gentle area, the existence of glass at the edge of the chip is avoided.
Effective passivation protection on the chip is achieved, avoiding the influence of the stress of the glass during scribing on the chip reliability, and making the performance of the chip stable and reliable.
Smart Images
Figure CN223038937U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to semiconductor devices, in particular to a chip with a novel glass passivation structure. Background Art
[0002] Chips with a glass passivation structure usually use a glass layer to passivate and protect the chips. However, for the existing chips with a glass passivation structure, there is glass in the dicing lane. When dicing, the glass needs to be cut, but the stress generated by the glass during dicing will have an adverse effect on the reliability of the chips. On the other hand, the existing chips with a glass passivation structure also have defects such as poor product performance and unstable performance. Therefore, how to provide a chip with a glass passivation structure that has good product performance and stable and reliable performance has become an objective need. Summary of the Utility Model
[0003] The utility model provides a chip with a novel glass passivation structure to solve the problems of poor product performance and unstable performance of the existing chips with a glass passivation structure.
[0004] To achieve the purpose of the utility model, the utility model provides a chip with a novel glass passivation structure. The chip includes a substrate, a first doping layer disposed on the upper surface of the substrate, a second doping layer disposed on the lower surface of the substrate, a first electrode disposed on the upper surface of the first doping layer, and a second electrode disposed on the lower surface of the second doping layer. At both ends of the upper part of the substrate, a first trench is respectively provided. On the upper surface of the first trench, a glass passivation film and a low-temperature oxidation film are provided. The glass passivation film covers part of the upper surface of the first doping layer and part of the inner wall of the first trench. The low-temperature oxidation film covers part of the upper surface of the first doping layer, the upper surface of the glass passivation film, and the edge of the inner wall of the first trench.
[0005] The substrate is of N-type <111> crystal orientation, with a thickness of 250 - 350 microns and a resistivity of 0.002 - 3.0 Ω·cm.
[0006] The first doping layer is P-type doped. A first PN junction is formed between the first doping layer and the substrate. Both ends of the first PN junction are respectively connected to two first trenches.
[0007] The second doping layer is a high-concentration N-type doping formed by phosphorus diffusion.
[0008] In some embodiments, the second doping layer is P-type doped. A second PN junction is formed between the second doping layer and the substrate.
[0009] Further, at both ends of the lower part of the substrate, a second trench is respectively provided. Both ends of the second PN junction are respectively connected to two second trenches.
[0010] The cross-section of the first trench is in a "C" shape, which includes a ramp region extending from the upper part of the substrate to the edge of the first doping layer and a flat region located at the edge of the substrate. The glass passivation film covers the ramp region of the first trench, and the low-temperature oxidation film covers the flat region of the first trench. The structure of the second trench is symmetrical to that of the first trench.
[0011] The first electrode is a metal electrode made of metal titanium nickel silver, tin copper alloy or nickel gold alloy, and it covers the upper surface of a part of the first doping layer.
[0012] The second electrode is a metal electrode made of metal titanium nickel silver, tin copper alloy or nickel gold alloy, and it covers the lower surface of the second doping layer.
[0013] The second electrode is a metal electrode made of metal titanium nickel silver, tin copper alloy or nickel gold alloy, and it covers the lower surface of a part of the second doping layer.
[0014] The beneficial effects of the present utility model are as follows: By respectively arranging a first trench at both edge ends of the upper part of the substrate, and a glass passivation film is arranged in the first trench, the chip can be passivated and protected. At the same time, the glass passivation film only covers the ramp region of the first trench, and only the low-temperature oxidation film covers the flat region of the first trench, which not only plays a good passivation and protection role, but also ensures that there is no glass structure at the edge of the chip, so that the glass will not be cut during dicing, thus avoiding the adverse effect of the stress generated by the glass during dicing on the reliability of the chip from the root cause, and making the performance of the chip stable and reliable. Description of the Drawings
[0015] Figure 1 is a schematic structural diagram of Embodiment 1 of the present utility model.
[0016] Figure 2 is a process flow chart of the manufacturing process of Embodiment 1 of the present utility model.
[0017] Figure 3 is a schematic screen printing process diagram of Embodiment 1 of the present utility model.
[0018] Figure 4 is a schematic structural diagram of Embodiment 2 of the present utility model.
[0019] In the figure, 10, substrate; 20, first doping layer; 21, first PN junction; 30, second doping layer; 31, second PN junction; 40, first electrode; 50, second electrode; 60, first trench; 61, second trench; 70, glass passivation film; 80, low-temperature oxidation film; 90, printing screen; 91, squeegee; 92, glass paste. Detailed Embodiments
[0020] The technical solution of the present utility model will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.
[0021] Embodiment 1
[0022] Please refer to Figure 1 , a chip with a novel glass passivation structure provided in this embodiment includes a substrate 10, a first doping layer 20, a second doping layer 30, a first electrode 40, a second electrode 50, a first trench 60, a glass passivation film 70, and a low-temperature oxidation film 80. The chip of the present utility model can be used for various circuit protection components.
[0023] As Figure 1 shown, the substrate 10 is an N-type <111> crystal orientation substrate single crystal wafer with a thickness of 250 - 350 μm and a resistivity of 0.002 - 3.0 Ω·cm. A first doping layer 20 is provided on the upper surface of the substrate 10, and a second doping layer 30 is provided on the lower surface of the substrate 10. Among them, the first doping layer 20 partially covers the upper surface of the substrate 10, and the second doping layer 30 covers the lower surface of the substrate 10. Specifically, the first doping layer 20 is P-type doped, which is formed by boron diffusion with a diffusion temperature of 1260 °C, a diffusion time of 15 - 25 hours, a diffusion sheet junction depth of 15 - 20 microns, and a sheet resistance R of 20 - 50 Ω. The second doping layer 30 is highly doped with N-type, which is formed by phosphorus diffusion with a diffusion temperature of 1150 °C, a diffusion time of 3 - 5 hours, and a sheet resistance R of 0.3 - 1 Ω. A first PN junction 21 is formed between the first doping layer 20 and the substrate 10. Utilizing the reverse cut-off characteristic of the PN junction, the over-voltage protection function of the chip can be realized.
[0024] As Figure 1As shown in the figure, a first trench 60 is provided at each of the two end edges of the upper part of the substrate 10. The first trench 60 is in a "C" shape, and its groove depth is 60 to 80 microns. The trench 60 includes a ramp area and a flat area. Among them, the ramp area extends from the upper part of the substrate 10 to the edge of the first doping layer 20, and the flat area is located at the edge of the substrate 10. Both ends of the first PN junction 21 are respectively connected to the two first trenches 60. Among them, the connection part of the first PN junction 21 and the first trench 60 is the ramp area of the first trench 60. A glass passivation film 70 and a low-temperature oxidation film 80 are provided on the upper surface of the first trench 60, which are used for passivation protection of the first PN junction 21. Specifically, the glass passivation film 70 covers the upper surface of a part of the first doping layer 20 and the ramp area of the first trench 60. The negative ion centers in the glass passivation film 70 can effectively capture metal ions to avoid the contamination of the first PN junction 21 by metal ions, thereby reducing leakage current and making the high-temperature performance of the chip more stable. The low-temperature oxidation film 80 covers the upper surface of a part of the first doping layer 20, the upper surface of the glass passivation film 70 and the flat area of the first trench 60, and its film thickness is 4000 ± 2000 Å. The low-temperature oxidation film 80 can effectively avoid the effect of thermal expansion and contraction on the glass during the solidification of the solder during the welding process. In this embodiment, since the ramp area of the first trench 60 is covered with the glass passivation film 70, it can provide passivation protection for the first PN junction 21, while the flat area of the first trench 60 is only covered with the low-temperature oxidation film 80 without the glass passivation film 70, which can not only achieve passivation protection of the chip, but also ensure that the chip is not adversely affected during dicing, thus making the performance of the product stable and reliable.
[0025] As Figure 1 shown, a first electrode 40 is provided on the upper surface of the first doping layer 20, and a second electrode 50 is provided on the lower surface of the second doping layer 30. The first electrode 40 and the second electrode 50 are both metal electrodes, and a layer of metal titanium nickel silver, tin copper alloy or nickel gold alloy can be respectively covered on the first doping layer 20 and the second doping layer 30 by PVD, electroplating or electroless plating to form the first electrode 40 and the second electrode 50. In this embodiment, the first electrode 40 partially covers the upper surface of the first doping layer 20, and the second electrode 50 covers the lower surface of the second doping layer 30. In some embodiments, before manufacturing the first electrode 40, via holes can be formed by photoresist, and the residual low-temperature oxidation film 80 in the via holes can be removed by wet etching. Since there is a low-temperature oxidation film 80 between the two ends of the first electrode 40 and the glass passivation film 70, there is no glass in the via hole area, and the quality of the chip will not be adversely affected by the stress generated by the glass when making the via hole, further improving the quality of the chip.
[0026] As Figure 2 shown, the manufacturing process of the chip with the novel glass passivation structure of this embodiment includes:
[0027] S10. Provide a substrate.
[0028] In this step, the substrate 10 is an N-type <111> crystal orientation single crystal wafer with a thickness of 250 - 350 μm and a resistivity of 0.002 - 3.0 Ω·cm. Specifically, a dense oxide layer of 1.6 - 2.0 μm is formed by hydrothermal synthesis. Among them, the hydrothermal synthesis temperature is 1100 °C, the hydrothermal synthesis time is 14 hours, the hydrogen flow rate is 7.0 L / min, and the oxygen flow rate is 5.0 L / min.
[0029] S20. Prepare a second doped layer.
[0030] In this step, a second doped layer 30 is formed on the lower surface of the substrate 10 by phosphorus diffusion. Among them, the diffusion temperature is 1150 °C, the diffusion time is 3 - 5 hours, and the sheet resistance R is 0.3 - 1.0 Ω.
[0031] S30. Prepare a first doped layer.
[0032] In this step, a first doped layer 20 is formed on the upper surface of the substrate 10 by boron diffusion. Among them, the diffusion temperature is 1260 °C, the diffusion time is 15 - 25 hours, the diffusion junction depth of the diffusion sheet is 15 - 20 μm, and the sheet resistance R is 20 - 50 Ω.
[0033] S40. Prepare a first trench.
[0034] In this step, a trench 60 is formed at each of the upper two ends of the substrate 10. Specifically, a negative photoresist is used, the etching solution is maintained at -5 °C, and etching is carried out for 8 - 15 minutes to form a first trench 60 with a trench depth of 60 - 80 μm. Among them, the composition of the etching solution is: hydrofluoric acid: glacial acetic acid: nitric acid: sulfuric acid = 9:9:12:4.
[0035] S50. Prepare a glass passivation film.
[0036] In this step, a glass passivation film 70 is prepared on the upper surface of the first trench 60. Among them, the main component of the glass passivation film 70 is glass paste. The glass powder model in the glass paste is GP200S or GP200 / W020, and the glass paste ratio is: butyl carbitol: ethyl cellulose: glass powder = 1:0.05:1.25. After the glass paste is prepared, it needs to be ball milled for 12 - 48 hours to ensure its uniformity.
[0037] As Figure 3As shown in the figure, in this embodiment, the glass passivation film 70 is prepared by a screen printing process. Specifically, first, the wafer is placed on a fully automatic alignment platform, and the wafer is adsorbed on a flat carrier table through vacuum. The fully automatic alignment platform aligns the alignment key points formed by the first photolithography on the wafer through an optical recognition system, and automatically adjusts the position of the carrier table so that the pattern on the wafer is consistent with the template stored in the optical recognition system, and the pattern control accuracy is within ±0.5um. After the wafer is aligned, the carrier table moves the wafer under the printing screen 90 in the printing area. The position of the printing screen has been accurately positioned in advance, and the printing screen will not move during the entire operation process. The printing screen is made of stainless steel or nylon. Only the area corresponding to the slope of the wafer trench is designed with a hollow on the printing screen, and all other areas on the printing screen, including the area corresponding to the wafer table and the middle area of the wafer trench, are designed without a hollow. The slurry can be applied to the hollow design area, and the slurry cannot be applied to the non-hollow design area. The designed width of the non-hollow area in the middle of the wafer trench on the printing screen is 15-45um. Then, pour the glass slurry 92 onto the printing screen 90. Since there are hollow and non-hollow designed patterns on the printing screen 90, the glass slurry is scraped into the slope area of the first trench 60 of the wafer by the squeegee 91, and it is ensured that the glass slurry will not be scraped into the flat area of the first trench 60. The squeegee is repeated twice to ensure that the glass slurry in the slope area of the first trench 60 is full. The material of the squeegee 91 is rubber, and the angle between the squeegee 91 and the printing screen is 50 degrees - 70 degrees. Then, the wafer is carried out by the carrier table. After the vacuum adsorption is released, the wafer printed with the glass slurry is horizontally placed in a Teflon basket, and then the Teflon basket containing the wafer is moved into a nitrogen protection oven for baking. The baking temperature is 150°C, and the baking time is 10-20min. Finally, the baked wafer is taken out and loaded into a quartz boat, and then the quartz boat carrying the wafer is pushed into a glass sintering furnace for glass sintering. The sintering temperature is 820±10°C, and the sintering time is 10-30min. The whole process is carried out with oxygen during sintering, and the oxygen flow rate is 6L / min. In this embodiment, through the automatic screen printing process, the reliability problems introduced by the manual operation of the traditional glass scraping process can be avoided, the human error can be reduced, the fullness of the glass in the first trench can be well guaranteed, and the passivation protection effect of the glass passivation film 70 on the first PN junction 21 can be improved. In addition, this process can effectively reduce the waste of glass materials and photoresist, reduce the production cost, avoid the use of photoresist or isopropyl alcohol, effectively improve the environmental protection of the production process, avoid the use of high-VOC materials, and has the characteristics of simple process and high production efficiency.
[0038] S60. Prepare a low-temperature oxidation film.
[0039] In this step, a low-temperature oxide film 80 is deposited by LPCVD (Low Pressure Chemical Vapor Deposition), where the temperature is 450 ± 50 °C, the reaction time is 20 - 40 minutes, the reaction source gases are: silane:oxygen in a ratio of 2:1, and the film thickness is 4000 ± 2000 Å.
[0040] S70. Prepare the first electrode and the second electrode.
[0041] In this step, a lead hole is formed using photoresist, and the residual low-temperature oxide film 80 in the lead hole is removed by wet etching. Finally, a layer of metal such as titanium nickel silver, tin copper alloy, or nickel gold alloy is covered on the upper surface of the first doping layer 20 and the lower surface of the second doping layer 30 by PVD, electroplating, or electroless plating to form the first electrode 40 and the second electrode 50. Among them, the first electrode 40 partially covers the upper surface of the first doping layer 20, and the second electrode 50 covers the lower surface of the second doping layer 30.
[0042] Example 2
[0043] As Figure 4 shown, the chip with the novel glass passivation structure in this example has the same substrate and the structure above the substrate as in Example 1. The difference is that the second doping layer 30 in this example is P-type doped. At this time, a second PN junction 31 is formed between the second doping layer 30 and the substrate 10, so that a PNP structure is formed among the first doping layer 20, the substrate 10, and the second doping layer 30. Utilizing the reverse cut-off characteristics of the first PN junction 21 and the second PN junction 31, the two-way protection function of the chip can be realized.
[0044] As Figure 4As shown, a second trench 61 is respectively provided at both lower edge ends of the substrate 10. The structure of the second trench 61 is symmetrical to that of the first trench 60, and it is connected to the end of the second PN junction 31 for passivation protection of the second PN junction 31. In this embodiment, the second PN junction 31 is connected to the ramp area of the first trench 60. A glass passivation film 70 and a low-temperature oxidation film 80 are provided on the lower surface of the second trench 61. Specifically, the glass passivation film 70 covers part of the lower surface of the second doping layer 30 and the ramp area of the second trench 61. The negative ion centers in the glass passivation film 70 can effectively capture metal ions to avoid the contamination of the second PN junction 31 by metal ions, thereby reducing leakage current and making the high-temperature performance of the chip more stable. The low-temperature oxidation film 80 covers part of the lower surface of the second doping layer 30, the lower surface of the glass passivation film 70, and the flat area of the second trench 61, and its film thickness is 4000 ± 2000 Å. The low-temperature oxidation film 80 can effectively avoid the effect of thermal expansion and contraction on the glass during the solidification of the solder during the welding process. In this embodiment, since the glass passivation film 70 covers the ramp area of the second trench 61, it can passivate and protect the second PN junction 31, while only the low-temperature oxidation film 80 covers the flat area of the second trench 61 without the glass passivation film 70, which can not only achieve the passivation protection of the chip but also ensure that no adverse effect is produced on the chip during dicing, thereby making the performance of the product stable and reliable.
[0045] As Figure 4 shown, a second electrode 50 is provided on the lower surface of the second doping layer 30, and the second electrode 50 covers part of the lower surface of the second doping layer 30. Before manufacturing the second electrode 50, a lead hole can be formed through a photoresist, and the remaining low-temperature oxidation film 80 in the lead hole can be removed by wet etching. Since the low-temperature oxidation film 80 is provided between both end portions of the second electrode 50 and the glass passivation film 70, there is no glass in the lead hole area, and no adverse effect will be caused to the quality of the chip due to the stress generated by the glass when making the lead hole, further improving the quality of the chip.
[0046] In summary, for the chip with the novel glass passivation structure of the present utility model, by respectively providing a first trench 60 at both upper edge ends of the substrate 10 and arranging a glass passivation film 70 in the first trench 60, the chip can be passivated and protected. At the same time, the glass passivation film 70 only covers the ramp area of the first trench 60, and only the low-temperature oxidation film 80 covers the flat area of the first trench 60, which not only plays a good passivation and protection role but also ensures that there is no glass structure at the edge of the chip, so that the glass will not be cut during dicing, and it is possible to avoid the adverse effect of the stress generated by the glass during dicing on the reliability of the chip from the root cause, making the performance of the chip stable and reliable.
[0047] On the other hand, a low-temperature oxide film 80 is provided between both end portions of the first electrode 40 and the glass passivation film 70. Therefore, there is no glass in the lead hole region, and the quality of the chip will not be adversely affected by the stress generated by the glass when the lead hole is fabricated, further improving the quality of the chip.
[0048] Although the present utility model has been disclosed through the above embodiments, the protection scope of the present utility model is not limited thereto. Without departing from the concept of the present utility model, deformations, substitutions, etc. made to the above components will all fall within the scope of the claims of the present utility model.
Claims
1. A new type of glass passivation structure chip, characterized in that: The chip includes a substrate, a first doping layer arranged on the upper surface of the substrate, a second doping layer arranged on the lower surface of the substrate, a first electrode arranged on the upper surface of the first doping layer, and a second electrode arranged on the lower surface of the second doping layer. A first groove is respectively provided on the two end edges of the upper part of the substrate, and a glass passivation film and a low-temperature oxidation film are provided on the upper surface of the first groove. The glass passivation film covers a portion of the upper surface of the first doping layer and a portion of the inner wall of the first groove, and the low-temperature oxidation film covers a portion of the upper surface of the first doping layer, the upper surface of the glass passivation film, and the edge of the inner wall of the first groove.
2. The chip with a novel glass passivation structure as claimed in claim 1, characterized in that: The substrate is N-type <111> crystal direction, its thickness is 250 to 350 microns, and its resistivity is 0.002 to 3.0 Ω·cm.
3. The chip with a novel glass passivation structure as claimed in claim 1, characterized in that: The first doping layer is P-type doped, a first PN junction is formed between the first doping layer and the substrate, and two ends of the first PN junction are respectively connected to two first trenches.
4. The chip with a novel glass passivation structure as claimed in claim 1, characterized in that: The second doping layer is a high-concentration N-type doping layer formed by diffusion of phosphorus.
5. The chip with a novel glass passivation structure as claimed in claim 1, characterized in that: The second doping layer is P-type doped, and a second PN junction is formed between the second doping layer and the substrate.
6. The chip with a novel glass passivation structure as claimed in claim 5, characterized in that: A second groove is respectively formed at the two end edges of the lower part of the substrate, and the two ends of the second PN junction are respectively connected to the two second grooves.
7. The chip with a novel glass passivation structure as claimed in claim 6, characterized in that: The cross-section of the first groove is "C"-shaped, including a slope area extending from the upper part of the substrate to the edge of the first doping layer and a flat area located at the edge of the substrate. The glass passivation film covers the slope area of the first groove, and the low-temperature oxidation film covers the flat area of the first groove. The structure of the second groove is symmetrical to that of the first groove.
8. The chip with a novel glass passivation structure as claimed in claim 1, characterized in that: The first electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy or nickel-gold alloy, and covers a portion of the upper surface of the first doped layer.
9. The chip with a novel glass passivation structure as claimed in claim 4, characterized in that: The second electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy or nickel-gold alloy, and covers the lower surface of the second doped layer.
10. The chip with a novel glass passivation structure as claimed in claim 6, characterized in that: The second electrode is a metal electrode made of titanium-nickel-silver, tin-copper alloy or nickel-gold alloy, and covers a portion of the lower surface of the second doped layer.