Integrated circuit chip packaging device and lead frame used therein

Abstract

The utility model provides an integrated circuit chip packaging device and a lead frame used therein. The lead frame used in the integrated circuit chip packaging device comprises a plurality of pins and at least one slide holder, and the at least one slide holder is provided with a plane which sinks relative to the plane where the plurality of pins are located. And at least one of the plurality of pins is widened relative to other pins to form a widened pin and is connected with one of the at least one slide holder.

Description

Technical Field

[0001] The utility model relates to the field of semiconductors, and particularly to an integrated circuit chip packaging device and a lead frame used therein. Background Art

[0002] The manufacturing process of integrated circuit chips mainly includes the following stages: the design stage of integrated circuit chips, the manufacturing stage of integrated circuit chips, the packaging stage of integrated circuit chips, and the testing stage of integrated circuit chips. After the integrated circuit chips are manufactured, there are usually multiple pads on the integrated circuit chips. In the packaging stage of the integrated circuit chips, the integrated circuit chips are generally connected to the lead frame by an adhesive (conductive or insulating), solder paste, wire bonding, or a ball mounting method, so that the pads of the integrated circuit chips are electrically connected to the corresponding contacts of the lead frame, thereby realizing the electrical connection of the integrated circuit chips inside the packaging structure.

[0003] With the increasing use of power integrated circuit chips, how to achieve the packaging of integrated circuit chips with miniaturization, high integration, and high heat dissipation performance has become a common concern in the semiconductor industry. Summary of the Utility Model

[0004] In view of one or more of the above problems, there is provided an integrated circuit chip packaging device and a lead frame used therein according to an embodiment of the present utility model.

[0005] The lead frame used in the integrated circuit chip packaging device according to an embodiment of the present utility model includes a plurality of pins and at least one carrier stage, wherein: at least one carrier stage has a plane that is concave and sunken relative to the plane where the plurality of pins are located, and at least one of the plurality of pins is widened to form a widened pin and is connected to one of the at least one carrier stage.

[0006] In some embodiments, one or more of the plurality of pins are provided with glue locking holes.

[0007] In some embodiments, the edges of one or more of the at least one carrier stage are provided with glue locking holes.

[0008] In some embodiments, the widened pins are provided with glue locking holes.

[0009] In some embodiments, a silver plating area is provided on a part of the surface of one or more of the at least one carrier stage.

[0010] In some embodiments, at least one end of the widened pin is provided with a wire bonding pin for wire bonding connection between the widened pin and the pin outside the plastic package of the integrated circuit chip packaging device.

[0011] An integrated circuit chip packaging device according to an embodiment of the present invention includes one or more integrated circuit chips, a plastic package body, and the above-mentioned lead frame.

[0012] In some embodiments, the integrated circuit chip packaging device further includes one or more surface-mounted discrete devices, and any one of the one or more surface-mounted discrete devices is disposed on the carrier stage of the lead frame by overlapping or tiling with one or more integrated circuit chips.

[0013] In some embodiments, the one or more integrated circuit chips include a power integrated circuit chip and a control integrated circuit chip. The power integrated circuit chip is directly disposed on the carrier stage of the lead frame, and the control integrated circuit chip is disposed on the power integrated circuit.

[0014] In some embodiments, the one or more integrated circuit chips include a power integrated circuit chip and a control integrated circuit chip, and the power integrated circuit chip and the control integrated circuit chip are tiled on the carrier stage of the lead frame. Description of the Drawings

[0015] The present invention can be better understood from the following description of the specific embodiments of the present invention in conjunction with the drawings, wherein:

[0016] Figure 1A A top view of a lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention is shown.

[0017] Figure 1B Shows Figure 1A A cross-sectional view of the shown lead frame along line A-A.

[0018] Figure 2A Shows including Figure 1A And Figure 1B A top view of an integrated circuit chip packaging device of the shown lead frame.

[0019] Figure 2B Shows Figure 2A A cross-sectional view of the shown integrated circuit chip packaging device along line B-B.

[0020] Figure 3 A top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention is shown.

[0021] Figure 4 A top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention is shown.

[0022] Figure 5Shows a top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention.

[0023] Figure 6 Shows a top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention.

[0024] Figure 7 Shows a top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention.

[0025] Figure 8 Shows a top view of the internal packaging structure of an integrated circuit chip packaging device according to an embodiment of the present invention.

[0026] Figure 9 Shows a top view of another internal packaging structure of an integrated circuit chip packaging device according to an embodiment of the present invention.

[0027] Figure 10 Shows a top view of another power integrated circuit chip packaging device according to an embodiment of the present invention. Detailed implementation manners

[0028] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the following detailed description, many specific details are set forth in order to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present invention by showing examples of the present invention. The present invention is in no way limited to any specific configuration set forth below, but covers any modification, replacement, and improvement of elements and components without departing from the spirit of the present invention. Well-known structures and technologies are not shown in the drawings and the following description so as to avoid unnecessarily obscuring the present invention. In addition, it should be noted that the term "A is connected to B" used herein may mean "A is directly connected to B" or "A is indirectly connected to B via one or more other elements".

[0029] In order to achieve the packaging of various integrated circuit chips with miniaturization, high integration, and high heat dissipation performance, an integrated circuit chip packaging device and a lead frame used therein according to an embodiment of the present invention are proposed.

[0030] Figure 1A Shows a top view of a lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention. Figure 1B Shows Figure 1A A cross-sectional view of the shown lead frame along line A-A. AsFigure 1A and Figure 1B As shown in Figure 1B , the lead frame 100 includes a plurality of pins (e.g., pin 1, pin 2, pin 3, pin 4, pin 5, etc.) and a carrier stage 102 for carrying an integrated circuit chip. Among them, the carrier stage 102 has a plane that is concave and sunken with respect to the plane where the plurality of pins are located. At least one of the plurality of pins (e.g., pin 5) is widened relative to other pins to form a widened pin and is connected to the carrier stage 102 (the other pins other than the widened pin are not connected to the carrier stage 102).

[0031] When the lead frame 100 is used in an integrated circuit chip packaging device, since the carrier stage 102 is connected to pin 5 and pin 5 itself is widened to form a widened pin, the heat dissipation channel between the integrated circuit chip carried on the carrier stage 102 and the external environment can be expanded. It should be understood that the lead frame 100 may include more than one carrier stage 102, and one or more of the carrier stages 102 may be arranged as described above in combination with Figure 1A and Figure 1B described and / or as described below in combination with Figures 2A to 10 described.

[0032] Figure 2A shows including Figure 1A and Figure 1B a top view of an integrated circuit chip packaging device with the lead frame shown in Figure 1B . Figure 2B shows Figure 2A a cross-sectional view of the integrated circuit chip packaging device shown in Figure 2A along line B - B. As Figure 2A and Figure 2B shown in Figure 2B , the integrated circuit chip packaging device 200 can adopt a patch structure, which can be applicable to both the traditional reflow soldering process in a printed circuit board assembly (PCBA) factory and the traditional wave soldering process for a plug-in structure, and can be manufactured by various assembly processing factories, thereby greatly reducing the assembly cost.

[0033] It should be understood that the integrated circuit chip packaging device 200 may include an integrated circuit chip, a lead frame, and a plastic package. Among them, the integrated circuit chip is carried on the lead frame and encapsulated by the plastic package. In some cases, the integrated circuit chip packaging device 200 may further include one or more surface-mounted discrete devices (e.g., surface-mounted resistors, surface-mounted capacitors, etc.), and any one of the surface-mounted discrete devices may be arranged on the carrier stage of the lead frame in a manner of overlapping or laying flat with the integrated circuit chip.

[0034] When the lead frame 100 is used in the integrated circuit chip packaging device 200, the heat dissipation channel between the integrated circuit chip carried on the carrier stage 102 and the external environment can be further expanded by exposing at least a part of the back surface of the carrier stage 102 (i.e., the side opposite to the concave and sunken plane of the carrier stage 102) to the outside of the integrated circuit chip packaging device 200. That is to say, at least a part of the back surface of the carrier stage 102 can be exposed to the outside of the integrated circuit chip packaging device 200 to form a heat dissipation channel between the integrated circuit chip carried on the carrier stage 102 and the external environment.

[0035] In some embodiments, the size of the carrier stage 102 can be made larger. For example, the area of the carrier stage 102 accounts for 10%-90% (e.g., more than 30%) of the total area of the plastic package of the integrated circuit chip packaging device 200, so that the carrier stage 102 can carry larger-sized integrated circuit chips, and at the same time, a larger heat dissipation area is exposed to the outside of the integrated circuit chip packaging device 200. In some cases, in order to expose the back surface of the carrier stage 102 to the outside of the integrated circuit chip packaging device 200, the thickness of the integrated circuit chip packaging device 200 can be reduced (for example, the thickness of the carrier stage 102 and each lead can be set within the range of 0.125-0.30 mm, and the thickness of the integrated circuit chip packaging device 200 can be set within the range of 1.0-1.5 mm).

[0036] Figure 3 The top view of another lead frame used in the integrated circuit chip packaging device according to an embodiment of the present invention is shown. As Figure 3 shown, the difference between the lead frame 300 and the lead frame 100 is that circular resin locking holes are provided on one or more leads (e.g., lead 1, lead 2, lead 3, lead 4) of the lead frame 300. This setting can increase the bonding force between the plastic package of the integrated circuit chip packaging device and the lead frame, and increase the reliability of the integrated circuit chip packaging device.

[0037] Figure 4 The top view of another lead frame used in the integrated circuit chip packaging device according to an embodiment of the present invention is shown. As Figure 4 shown, the difference between the lead frame 400 and the lead frame 100 is that semi-circular resin locking holes are provided at the edge of the carrier stage 402 of the lead frame 400. This setting can increase the bonding force between the plastic package of the integrated circuit chip packaging device and the lead frame, and increase the reliability of the integrated circuit chip packaging device.

[0038] Figure 5 The top view of another lead frame used in the integrated circuit chip packaging device according to an embodiment of the present invention is shown. As Figure 5As shown, the lead frame 500 is different from the lead frame 100 in that at least one widened pin (e.g., pin 5) of the lead frame 500 is provided with a special-shaped glue-locking hole. This setting can increase the bonding force between the plastic package of the integrated circuit chip packaging device and the lead frame, increasing the reliability of the integrated circuit chip packaging device; at the same time, it can reduce the stress concentration problem of the widened pins and improve the manufacturing feasibility of the integrated circuit chip packaging device.

[0039] Figure 6 Fig. shows a top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention. As Figure 6 shown, the lead frame 600 is different from the lead frame 100 in that a silver-plated area is provided on a part of the surface of the carrier stage 602 of the lead frame 600. This setting can not only meet the requirements of wire bonding but also increase the reliability of the integrated circuit chip packaging device.

[0040] Figure 7 Fig. shows a top view of another lead frame used in an integrated circuit chip packaging device according to an embodiment of the present invention. As Figure 7 shown, the lead frame 700 is different from the lead frame 100 in that at least one end of at least one widened pin (e.g., pin 5) of the lead frame 700 is provided with a wire bonding pin for wire bonding connection between the widened pin and the pin outside the plastic package of the integrated circuit chip packaging device.

[0041] Figure 8 Fig. shows a top view of the internal packaging structure of an integrated circuit chip packaging device according to an embodiment of the present invention. As Figure 8 shown, in the integrated circuit chip packaging device 800, the carrier stage is implemented with a larger size to carry a larger power integrated circuit chip. A smaller control integrated circuit chip can be pasted above the power integrated circuit chip (that is, two or more integrated circuit chips can be arranged on the carrier stage in an overlapping manner); the carrier stage is connected to the widened pins, so that the heat dissipation channel between the power integrated circuit chip and the external environment includes at least one widened pin; at the same time, the back surface of the carrier stage is exposed outside the integrated circuit chip packaging device 800, further expanding the heat dissipation channel between the power integrated circuit chip and the external environment.

[0042] Figure 9 Fig. shows a top view of another internal packaging structure of an integrated circuit chip packaging device according to an embodiment of the present invention. As Figure 9As shown, in the integrated circuit chip packaging device 900, when the power integrated circuit chip is small, the power integrated circuit chip and the control integrated circuit chip are arranged flat on the carrier table (that is to say, two or more integrated circuit chips can be arranged on the carrier table in a flat setting manner); the carrier table is connected to the widened pins, so that the heat dissipation channels between the power integrated circuit chip and the external environment include at least one widened pin; at the same time, the back surface of the carrier table is exposed outside the integrated circuit chip packaging device 900, further expanding the heat dissipation channels between the power integrated circuit chip and the external environment.

[0043] Figure 10 shows a top view of another power integrated circuit chip packaging device according to an embodiment of the present invention. As Figure 10 shown, in the integrated circuit chip packaging device 1000, a lead frame with two widened pins (for example, pin 5 and pin 6) is adopted. This design of the lead frame can reduce the external molding stress and increase the manufacturing feasibility of the integrated circuit chip packaging device.

[0044] As described above, the integrated circuit chip packaging device according to an embodiment of the present invention is applicable to the packaging of power integrated circuit chips (such as power management integrated circuit chips) that are miniaturized, highly integrated, and have heat dissipation requirements.

[0045] In addition, although the above description takes the packaging structure with five pins as an example, it should be understood that the integrated circuit chip packaging device and its lead frame according to an embodiment of the present invention are not limited to including five pins, but may include more or fewer pins.

[0046] The features, structures, or characteristics described above can be combined in any suitable manner in one or more embodiments. In the above description, many specific details are provided to give a full understanding of the embodiments of the present invention. However, those skilled in the art will realize that the technical solutions of the present invention can be practiced without one or more of the specific details, or other methods, components, materials, etc. can be adopted. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical concepts of the present invention.

Claims

1. A lead frame for use in an integrated circuit chip packaging device, characterized in that: The device comprises a plurality of pins and at least one wafer carrier, wherein: The at least one wafer stage has a plane that is recessed and sunken relative to the plane where the plurality of pins are located, and At least one of the plurality of pins is widened relative to the other pins to form a widened pin and is connected to one of the at least one wafer carrier.

2. The lead frame for use in an integrated circuit chip packaging device according to claim 1, characterized in that: One or more of the plurality of pins is provided with a glue locking hole.

3. The lead frame for use in an integrated circuit chip packaging device according to claim 1, characterized in that: The edges of one or more of the at least one wafer carrier are provided with glue locking holes.

4. The lead frame for use in an integrated circuit chip packaging device according to claim 1, characterized in that: The widened pin is provided with a glue locking hole.

5. The lead frame for use in an integrated circuit chip packaging device according to claim 1, characterized in that: A silver-plated area is provided on a partial surface of one or more of the at least one wafer carrier.

6. The lead frame for use in an integrated circuit chip packaging device according to claim 1, characterized in that: At least one end of the widened pin is provided with a bonding pin for bonding the widened pin to a pin outside the plastic package of the integrated circuit chip packaging device.

7. An integrated circuit chip packaging device, characterized in that: The invention comprises one or more integrated circuit chips, a plastic package, and the lead frame according to any one of claims 1 to 6.

8. The integrated circuit chip packaging device according to claim 7, characterized in that: It also includes one or more discrete chip components, any one of which is arranged on the wafer carrier of the lead frame in an overlapping or flat arrangement with the one or more integrated circuit chips.

9. The integrated circuit chip packaging device according to claim 7, characterized in that: The one or more integrated circuit chips include a power integrated circuit chip and a control integrated circuit chip. The power integrated circuit chip is directly arranged on the wafer carrier of the lead frame, and the control integrated circuit chip is arranged on the power integrated circuit.

10. The integrated circuit chip packaging device according to claim 7, characterized in that: The one or more integrated circuit chips include a power integrated circuit chip and a control integrated circuit chip, and the power integrated circuit chip and the control integrated circuit chip are arranged flat on a wafer carrier of the lead frame.

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