PMIC adapter plate

Abstract

The utility model provides a PMIC adapter plate. The PMIC adapter plate comprises an adapter plate body; the micro-processing chip mounting area is arranged in the middle area of the adapter plate body and comprises a plurality of first inner pins; the first connecting area is arranged on the first side of the adapter plate body and comprises a plurality of first outer pins; the second connecting area is arranged on the second side, opposite to the first side, of the adapter plate body and comprises a plurality of second outer pins; the first discrete device mounting area is arranged between the micro-processing chip mounting area and the first connecting area and comprises a plurality of second inner pins corresponding to the plurality of first discrete devices; and the second discrete device mounting area is arranged between the micro-processing chip mounting area and the second connecting area and comprises a plurality of third inner pins corresponding to the plurality of second discrete devices. By optimizing the layout of the adapter plate, simplifying the circuit structure and providing flexible pin configuration, the liquid crystal display module adapts to various liquid crystal panels, the power management efficiency is improved, and the compatibility and the stability of the module are enhanced.

Description

Technical Field

[0001] This application relates to the technical field of liquid crystal displays, and particularly to a PMIC adapter board. Background Art

[0002] TFT-LCD (Thin Film Transistor Liquid Crystal Display) technology has been widely used in various electronic devices. However, with the increasing market demand for high-cost performance display modules, many TFT-LCD panel manufacturers have started to introduce liquid crystal panel products without PMIC circuits. Such products eliminate the traditional PCB (Printed Circuit Board) and directly lead out functional pins through FPC (Flexible Printed Circuit), thus significantly reducing the production and manufacturing costs. However, with the elimination of the PCB, additional considerations need to be given in the design of such liquid crystal panels on how to provide the required driving voltages and functional configuration circuits. Traditional liquid crystal panels usually integrate PMICs and can directly handle various power management requirements. However, in liquid crystal panels without PMIC circuits, due to the lack of built-in power management modules, the driving and functional configuration of the panels become more complex, and in practical applications, the types, specifications of the interfaces, and the arrangement of pins also face higher design requirements. Summary of the Utility Model

[0003] In view of this, this application is committed to providing a PMIC adapter board to solve the power management problem of existing liquid crystal panels without PMIC circuits and provide various driving voltages and functional configurations required by the liquid crystal panels.

[0004] In a first aspect, this application provides a PMIC adapter board, which is characterized by comprising:

[0005] An adapter board body;

[0006] A microprocessor chip installation area, arranged in the middle area of the adapter board body and including a plurality of first inner pins;

[0007] A first connection area, arranged on the first side of the adapter board body and including a plurality of first outer pins;

[0008] A second connection area, arranged on the second side of the adapter board body opposite to the first side and including a plurality of second outer pins;

[0009] A first discrete device installation area, arranged between the microprocessor chip installation area and the first connection area and including a plurality of second inner pins corresponding to a plurality of first discrete devices;

[0010] A second discrete device installation area, arranged between the microprocessor chip installation area and the second connection area and including a plurality of third inner pins corresponding to a plurality of second discrete devices.

[0011] Optionally, the multiple first inner pins of the microprocessing chip installation area include an LX pin, a NAVDD pin, a VGL pin, and a CX1 pin;

[0012] The multiple second inner pins of the first discrete device installation area include a VSN_I pin and a VGL_DC pin. The VSN_I pin is connected to the NAVDD pin and is connected to a voltage regulating module installed in the first discrete device installation area. The VGL_DC pin is connected to the VGL pin and is connected to the voltage regulating module. The voltage regulating module is also connected to the CX1 pin;

[0013] The multiple first outer pins of the first connection area include a VCC1 pin. The VCC1 pin is connected to the LX pin.

[0014] Optionally, a capacitor C11, a diode D11, and a resistor R14 are sequentially connected between the CX1 pin and the VSN_I pin;

[0015] A capacitor C12 and a first diode BAT54S are sequentially connected between the CX1 pin and the VGL_DC pin;

[0016] A resistor R13 is connected between the diode D11 and the resistor R14. One end of the resistor R13 is grounded. A second diode BAT54S is connected between the diode D11 and the capacitor C11; A diode D12 is connected between the capacitor C12 and the first diode BAT54S; A capacitor C13 is connected between the second diode BAT54S and the diode D12. One end of the capacitor C13 is grounded.

[0017] Optionally, an inductor L1 and a resistor R1 are sequentially connected between the LX pin and the VCC1 pin;

[0018] The LX pin is also grounded through the inductor L1 and the capacitor C1 connected in sequence.

[0019] Optionally, the multiple second inner pins of the first discrete device installation area include a VSN pin; A resistor R2 is connected between the VSN pin and the NAVDD pin; One end of a diac D9 is connected between the VSN pin and the resistor R2, and the other end of the diac D9 is grounded;

[0020] The VSN pin is connected to a display through a first protection circuit.

[0021] Optionally, the VSN_I pin is connected between a resistor R2 and the NAVDD pin; capacitors C4, C5, and C6 are provided in the first discrete device mounting area, the capacitors C4, C5, and C6 are connected in parallel, and one end is connected to the VSN_I pin and the other end is grounded.

[0022] Optionally, the multiple first internal pins in the microprocessing chip mounting area further include an LXP pin, and the multiple second internal pins in the first discrete device mounting area further include a VSP_I pin; an inductor L2 is connected between the LXP pin and the VSP_I pin; one end of a capacitor C7 is connected between the inductor L2 and the VSP_I pin, and the other end of the capacitor C7 is grounded.

[0023] Optionally, the multiple first internal pins in the microprocessing chip mounting area further include a PAVDD pin, and the multiple second external pins in the second connection area include a VSP pin;

[0024] A resistor R10 is connected between the VSP pin and the PAVDD pin; one end of a diac D2 is connected between the VSP pin and the resistor R10, and the other end of the diac D2 is grounded; the PAVDD pin is also connected to the VSP_I pin;

[0025] The VSP pin is connected to a display through a second protection circuit.

[0026] Optionally, capacitors C8 and C9 are provided in the second discrete device mounting area, the capacitors C8 and C9 are connected in parallel, and one end is connected to the VSP_I pin and the other end is grounded.

[0027] According to the solution of the present application, by reasonably arranging the microprocessing chip mounting area, the discrete device mounting area, and the connection area on the adapter board body, not only can the circuit design be effectively simplified, but also a flexible pin configuration method is provided. This design can adapt to different liquid crystal panel configuration requirements, while optimizing power management and function configuration, and improving the compatibility and stability of the entire liquid crystal display module.

[0028] Furthermore, by increasing the reasonable configuration of components such as capacitors, resistors, and diodes on the PMIC adapter board, the anti-interference ability of the circuit is enhanced, ensuring the stability of signal transmission. In addition, the introduction of the protection circuit effectively prevents damage to the liquid crystal panel caused by static electricity and overvoltage, and prolongs the service life of the display. These improvements not only enhance the reliability of the entire system, but also enhance the performance of the liquid crystal panel, making it more advantageous in practical applications.

[0029] The above description is only an overview of the technical solution of the present application. In order to better understand the technical means of the present application and be implemented in accordance with the content of the specification, the following describes the preferred embodiments of the present application in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Shows a schematic structural diagram of a PMIC adapter board according to an embodiment of the present application;

[0031] Figure 2 Shows a circuit diagram of a PMIC adapter board according to an embodiment of the present application;

[0032] Figure 3 Shows a circuit diagram of a first protection circuit according to an embodiment of the present application;

[0033] Figure 4 Shows a schematic diagram of some pins of a display part according to an embodiment of the present application;

[0034] Figure 5 Shows a circuit diagram of a second protection circuit according to an embodiment of the present application;

[0035] Figure 6 Shows a circuit diagram of a third protection circuit according to an embodiment of the present application;

[0036] Figure 7 Shows a circuit diagram of a fourth protection circuit according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] In order to make the above objects, features, and advantages of the present application more obvious and understandable, the following will describe the specific embodiments of the present application in detail with reference to the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain the present application, rather than limiting the present application. In addition, it should be noted that for the sake of convenience of description, only parts related to the present application are shown in the drawings, rather than all the structures. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0038] The terms "including" and "having" and any variations thereof in the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include steps or units not listed, or may optionally further include other steps or units inherent to these processes, methods, products, or devices.

[0039] Reference to "embodiments" in this document means that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears at various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0040] Figure 1 Fig. shows a schematic structural diagram of a PMIC adapter board according to an embodiment of the present application. As Figure 1 shown, the microprocessor chip installation area 110 is arranged in the middle area of the adapter board body 100 and includes a plurality of first inner pins. The first connection area 120 is arranged on the left side of the adapter board body 100 and includes a plurality of first outer pins. The second connection area 130 is arranged on the right side of the adapter board body 100 and includes a plurality of second outer pins. A first discrete device installation area 140 is arranged between the microprocessor chip installation area 110 and the first connection area 120 and includes a plurality of second inner pins corresponding to a plurality of first discrete devices. A second discrete device installation area 150 is arranged between the microprocessor chip installation area 110 and the second connection area 130 and includes a plurality of third inner pins corresponding to a plurality of second discrete devices.

[0041] In this embodiment, by reasonably arranging the microprocessor chip installation area, discrete device installation area, and connection area on the adapter board body, not only can the circuit design be effectively simplified, but also a flexible pin configuration method is provided. This design can adapt to different liquid crystal panel configuration requirements, while optimizing power management and function configuration, and improving the compatibility and stability of the entire liquid crystal display module.

[0042] Figure 2 Fig. shows a circuit diagram of a PMIC adapter board according to an embodiment of the present application. As Figure 2 shown, the VSN_I pin and the VGL_DC pin are arranged on the first discrete device installation area 140, the NAVDD pin, the VGL pin, the CX1 pin, and the LX pin are arranged on the microprocessor chip installation area 110, and the VCC1 is arranged on the first connection area 120. The VCC1 pin is connected to the LX pin. The VSN_I pin is connected to the NAVDD pin and is also connected to a voltage regulation module installed in the first discrete device installation area 140. The VGL_DC pin is connected to the VGL pin and is also connected to the above voltage regulation module. The CX1 pin is connected to the voltage regulation module.

[0043] In some embodiments, a capacitor C11, a diode D11, and a resistor R14, which are disposed on the first discrete device setting area 140, are sequentially connected between the CX1 pin and the VSN_I pin. A capacitor C12 and a first diode BAT54S, which are disposed on the first discrete device setting area 140, are sequentially connected between the CX1 pin and the VGL_DC pin. A resistor R13, which is disposed on the first discrete device setting area 140, is connected between the diode D11 and the resistor R14, and one end of the resistor R13 is grounded. A second diode BAT54S, which is disposed on the first discrete device setting area 140, is connected between the diode D11 and the capacitor C11. A diode D12, which is disposed on the first discrete device setting area 140, is connected between the capacitor C12 and the first diode BAT54S. A capacitor C13, which is disposed on the first discrete device setting area 140, is connected between the second diode BAT54S and the diode D12, and one end of the capacitor C13 is grounded.

[0044] The circuit connected between the VSN_I pin and the CX1 pin and the circuit connected between the VGL_DC pin and the CX1 pin form a voltage regulating module. The VSN_I pin is connected to the NAVDD pin, and the VGL_DC pin is connected to the VGL pin. When |VGL| > PAVDD + |NAVDD|, |VGL| can be increased. Since the voltages at VGL and NAVDD are usually negative voltages, the absolute value is used to represent their magnitudes without considering the influence of voltage polarity. That is, when the absolute value of the voltage at VGL is greater than the sum of the absolute values of the voltages at PAVDD and NAVDD, it means that the gate drive voltage is large enough to effectively control the pixels of the liquid crystal panel. If this condition is already met but the display effect of the liquid crystal panel is still not ideal, then it can be considered to further increase the voltage at VGL. This can ensure that the gate voltage is strong enough to further improve the switching efficiency and display quality of the liquid crystal panel.

[0045] R14 is located between the CX1 pin and the VSN_I pin and is connected in series with the diode D11 and the capacitor C11. R14 can control the current passing through this path, affect the charging and discharging time of the capacitor C11, thereby affecting the voltage change rate between the CX1 pin and the VSN_I pin, and further regulating the voltage regulation dynamic response performance of the voltage regulation module. By limiting the current, R14 can also protect circuit components from the impact of sudden current surges, reducing circuit noise and interference. One end of R13 is grounded, and the other end is connected to the cathode of the D11 diode. Its function is to provide a current loop for the D11 diode. The presence of R13 ensures a stable current path when D11 conducts, can control the conduction current of D11, and prevent it from operating in an unstable state. Additionally, when current passes through R13, a voltage drop will be generated, and this voltage drop can affect the voltage on the capacitor C13, thereby regulating the voltage relationship between VGL and CX1. This is very important for regulating the voltage difference between the VGL voltage and PAVDD + NAVDD, ensuring that the voltage regulation module can accurately regulate and maintain the required output voltage.

[0046] In some embodiments, an inductor L1 and a resistor R1 are sequentially connected between the above-mentioned VCC1 pin and the LX pin. The LX pin is also grounded through the inductor L1 and the capacitor C1 connected in sequence. The above-mentioned inductor L1, resistor R1, and capacitor C1 are all arranged on the first discrete device setting area 140. Through the filtering effect of the inductor L1 and the capacitor C1, high-frequency noise and current spikes are effectively suppressed, the voltage is stabilized, electromagnetic interference is reduced, and circuit components are protected. At the same time, it optimizes energy transfer, improves power conversion efficiency, and enhances the stability of the PMIC and the overall reliability of the system. The resistor R1 and the inductor L1 and the capacitor C1 together form a low-pass filter to further suppress high-frequency noise in the power supply and improve the anti-interference ability of the circuit.

[0047] In some embodiments, a VSN pin is also arranged on the first discrete device installation area 140. A resistor R2 installed on the first discrete device installation area 140 is connected between the VSN pin and the NAVDD pin. One end of a diac D9 installed on the first discrete device installation area 140 is connected between the VSN pin and the resistor R2, and the other end is grounded. The VSN pin is also connected to the display through a first protection circuit.

[0048] The resistor R2 is connected between the VSN pin and the NAVDD pin, serving the functions of voltage division and current limiting. By controlling the magnitude of the current, R2 can reduce voltage fluctuations, prevent excessive current from passing through, and protect subsequent circuit components. The bidirectional trigger diode D9 is a protection component, connected between the VSN pin and the resistor R2, with its other end grounded. When the voltage exceeds the set threshold, D9 will conduct, providing a low-impedance path to discharge the excessive voltage or current to the ground, so as to protect the VSN pin and the subsequent circuit from high-voltage impacts.

[0049] Figure 3 The circuit diagram of the first protection circuit according to an embodiment of the present application is shown. Figure 4 The schematic diagram of the pins of the display part according to an embodiment of the present application is shown. As Figure 3 and Figure 4 shown, between the VSN pin in the above-mentioned first protection circuit and the VSN_C pin on the display, a resistor R28 and the parallel-connected capacitors C28 and C25 are sequentially connected, and the other ends of the parallel-connected capacitors C28 and C25 are grounded. The resistor R28 is connected between the VSN pin and the VSN_C pin on the display, serving the function of further current limiting to prevent damage to the VSN pin due to excessive transient current in the display circuit. The capacitors C28 and C25 are connected in parallel after R28, and their other ends are grounded, serving the functions of filtering and stabilizing the voltage. Capacitors can smooth voltage fluctuations, eliminate high-frequency noise, prevent signal interference, and improve the purity of the signal and the anti-interference ability of the system.

[0050] Through the combined setting of the above components, the circuit can not only effectively protect the VSN pin and related circuits from the influence of voltage fluctuations and current impacts, but also improve the stability of the signal and the overall performance of the system.

[0051] In some embodiments, as Figure 2 shown, the VSN_I pin is connected between the resistor R2 and the NAVDD pin. The first discrete device mounting area 140 is provided with capacitors C4, C5, and C6. The capacitors C4, C5, and C6 are connected in parallel, with one end connected to the VSN_I pin and the other end grounded. By connecting the capacitors C4, C5, and C6 in parallel, the power supply filtering effect is effectively enhanced, the stability and anti-interference ability of the signal are improved, and the transient response ability of the power supply current is optimized. In addition, this configuration also reduces the influence of parasitic inductance, ensuring that the circuit can maintain stable and efficient operation under various working conditions.

[0052] In some embodiments, as Figure 2As shown, the multiple first internal pins provided on the microprocessor chip installation area 110 further include LXP pins, and the multiple second internal pins provided on the first discrete device installation area 140 further include VSP_I pins. An inductor L2 installed on the first discrete device installation area 140 is connected between the LXP pins and the VSP_I pins. One end of a capacitor C7 installed on the first discrete device installation area 140 is connected between the inductor L2 and the VSP_I pins, and the other end is grounded. Through the combination of the inductor L2 and the capacitor C7, efficient filtering and voltage regulation are achieved, high-frequency noise and electromagnetic interference are suppressed, and at the same time, the stability of the power supply voltage is enhanced. This not only protects the microprocessor chip and related circuits, but also improves the stability of signal transmission and the overall performance of the system.

[0053] In some embodiments, as Figure 2 shown, the multiple first internal pins provided on the microprocessor chip installation area 110 further include PAVDD pins, and the multiple second external pins of the second connection area 130 include VSP pins. A resistor R10 is connected between the VSP pins and the PAVDD pins. One end of a bidirectional trigger diode D2 is connected between the VSP pins and the resistor R10, and the other end of the bidirectional trigger diode D2 is grounded. The PAVDD pins are also connected to the VSP_I pins. The VSP pins are connected to the display through a second protection circuit. The above resistor R10 and bidirectional trigger diode D2 are both installed on the second discrete device installation area 150.

[0054] Figure 5 The circuit diagram of the second protection circuit according to an embodiment of the present application is shown. As Figure 5 and Figure 4 shown, in the above second protection circuit, a resistor R27 and a parallel connection of a capacitor C26 and a capacitor C27 are sequentially connected between the VSP pins and the VSP_C pins on the display, and the other ends of the parallel connection of the capacitor C26 and the capacitor C27 are grounded. Through the current limiting and voltage dividing effects of the resistor R10, the overvoltage protection of the bidirectional trigger diode D2, the further current limiting of the resistor R27, and the filtering effects of the parallel capacitors C26 and C27, comprehensive protection of the VSP pins and their connected circuits is achieved. It not only improves the anti-interference ability of the circuit, ensures the stability of signal transmission, but also enhances the overall reliability of the system and prevents potential damage to the circuit caused by voltage surges.

[0055] In some embodiments, as Figure 2As shown, a capacitor C8 and a capacitor C9 are mounted on the second discrete device mounting area 150. The capacitor C8 and the capacitor C9 are connected in parallel, with one end connected to the VSP_I pin and the other end grounded. The parallel connection of the capacitor C8 and C9 not only enhances the filtering effect and power supply stability of the VSP_I pin, but also improves the circuit's response ability to transient currents, ensuring the stability and anti-interference ability of the circuit during high-frequency operations, and enhancing the reliability and performance of the overall system.

[0056] Figure 6 The circuit diagram of a third protection circuit according to an embodiment of the present application is shown. Figure 7 The circuit diagram of a fourth protection circuit according to an embodiment of the present application is shown. Refer to Figure 2 , a VGH pin and a VGL pin are provided on the microprocessing chip mounting area 110. As Figure 6 shown, in the third protection circuit, a resistor R26 and a parallel-connected capacitor C23 and capacitor C24 are sequentially connected between the VGH pin and the VGH_C pin on the display. The other ends of the parallel-connected capacitor C23 and capacitor C24 are grounded. The VGH pin is connected to the VGH_C pin on the display through the third protection circuit. Similarly, as Figure 7 shown, in the fourth protection circuit, a resistor R25 and a parallel-connected capacitor C22 and capacitor C21 are sequentially connected between the VGL pin and the VGL_C pin on the display. The other ends of the parallel-connected capacitor C22 and capacitor C21 are grounded. The VGL pin is connected to the VGL_C pin on the display through the third protection circuit. By providing the third and fourth protection circuits between the VGH and VGL pins and the corresponding pins on the display, effective protection of the circuit is achieved. This design can significantly improve the anti-interference ability of the circuit, ensure the stability of the signal during transmission, and reduce the risk of failures caused by voltage fluctuations or interference, thereby enhancing the overall reliability and working stability of the system.

[0057] In some embodiments, as Figure 2As shown, a pull-up resistor module connected in parallel is installed on the second discrete device setting area 150, including resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, and resistor R9. One end of the pull-up resistor module connected in parallel is connected to the DCDC pin, and the other end is respectively connected to the corresponding pins provided on the microprocessor chip installation area 110. Resistor R4 is connected to pin EN, resistor R5 is connected to pin WP, resistor R6 is connected to pin FAULT, resistor R7 is connected to pin RESET, resistor R8 is connected to pin SCL, and resistor R9 is connected to pin SDA. By setting the pull-up resistor module connected in parallel, the circuit can ensure the signal stability of multiple key pins, prevent misoperation, simplify the design, and improve the reliability of I2C communication. This design enhances the anti-interference ability and working reliability of the entire system, and helps to achieve stable and efficient circuit operation.

[0058] According to the above embodiments, the PMIC adapter board of the technical solution of the present application enhances the anti-interference ability of the circuit and ensures the stability of signal transmission by increasing the reasonable configuration of components such as capacitors, resistors, and diodes. In addition, the introduction of the protection circuit effectively prevents damage to the liquid crystal panel caused by static electricity and overvoltage, and extends the service life of the display. These improvements not only enhance the reliability of the entire system, but also improve the performance of the liquid crystal panel, making it more advantageous in practical applications.

[0059] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0060] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A PMIC adapter board, characterized in that: include: Adapter plate body; A microprocessor chip installation area is arranged in the middle area of ​​the adapter board body and includes a plurality of first inner pins; A first connection area is disposed on a first side of the adapter board body and includes a plurality of first external pins; A second connection area is disposed on a second side of the adapter board body opposite to the first side and includes a plurality of second external pins; A first discrete device mounting area is disposed between the microprocessor chip mounting area and the first connection area and includes a plurality of second inner pins corresponding to a plurality of first discrete devices; The second discrete device mounting area is arranged between the microprocessor chip mounting area and the second connection area, and includes a plurality of third inner pins corresponding to a plurality of second discrete devices.

2. The PMIC adapter board according to claim 1, characterized in that: The plurality of first inner pins of the microprocessor chip mounting area include an LX pin, a NAVDD pin, a VGL pin and a CX1 pin; The plurality of second inner pins of the first discrete device mounting area include a VSN_I pin and a VGL_DC pin, the VSN_I pin is connected to the NAVDD pin and is connected to a voltage regulating module mounted in the first discrete device mounting area, the VGL_DC pin is connected to the VGL pin and is connected to the voltage regulating module, and the voltage regulating module is also connected to the CX1 pin; The plurality of first external pins of the first connection area include a VCC1 pin, and the VCC1 pin is connected to the LX pin.

3. The PMIC adapter board according to claim 2, characterized in that: A capacitor C11, a diode D11 and a resistor R14 are sequentially connected between the CX1 pin and the VSN_I pin; A capacitor C12 and a first diode BAT54S are connected in sequence between the CX1 pin and the VGL_DC pin; A resistor R13 is connected between the diode D11 and the resistor R14, and one end of the resistor R13 is grounded. A second diode BAT54S is connected between the diode D11 and the capacitor C11; a diode D12 is connected between the capacitor C12 and the first diode BAT54S; a capacitor C13 is connected between the second diode BAT54S and the diode D12, and one end of the capacitor C13 is grounded.

4. The PMIC adapter board according to claim 2, characterized in that: An inductor L1 and a resistor R1 are sequentially connected between the LX pin and the VCC1 pin; The LX pin is also grounded through the inductor L1 and the capacitor C1 which are connected in sequence.

5. The PMIC adapter board according to claim 2, characterized in that: The plurality of second inner pins of the first discrete device mounting area include a VSN pin; a resistor R2 is connected between the VSN pin and the NAVDD pin; one end of a bidirectional trigger diode D9 is connected between the VSN pin and the resistor R2, and the other end of the bidirectional trigger diode D9 is grounded; The VSN pin is connected to the display through a first protection circuit.

6. The PMIC adapter board according to claim 5, characterized in that: The VSN_I pin is connected between the resistor R2 and the NAVDD pin; the first discrete device mounting area is provided with capacitors C4, C5 and C6, which are connected in parallel, with one end connected to the VSN_I pin and the other end grounded.

7. The PMIC adapter board according to claim 1, characterized in that: The multiple first inner pins of the microprocessor chip mounting area also include an LXP pin, and the multiple second inner pins of the first discrete device mounting area also include a VSP_I pin; an inductor L2 is connected between the LXP pin and the VSP_I pin; one end of a capacitor C7 is connected between the inductor L2 and the VSP_I pin, and the other end of the capacitor C7 is grounded.

8. The PMIC adapter board according to claim 7, characterized in that: The plurality of first inner pins of the microprocessor chip mounting area further include a PAVDD pin, and the plurality of second outer pins of the second connection area include a VSP pin; A resistor R10 is connected between the VSP pin and the PAVDD pin; one end of a bidirectional trigger diode D2 is connected between the VSP pin and the resistor R10, and the other end of the bidirectional trigger diode D2 is grounded; the PAVDD pin is also connected to the VSP_I pin; The VSP pin is connected to the display through a second protection circuit.

9. The PMIC adapter board according to claim 8, characterized in that: The second discrete device mounting area is provided with a capacitor C8 and a capacitor C9. The capacitor C8 and the capacitor C9 are connected in parallel, and one end of the capacitor C8 and the capacitor C9 are connected to the VSP_I pin, and the other end of the capacitor C8 and the capacitor C9 are grounded.

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