Semiconductor device

Abstract

A semiconductor device includes a first source / drain region spaced apart from a second source / drain region in a lateral Y-direction; a fin structure including a semiconductor nanosheet, where the semiconductor nanosheet extends in a lateral Y-direction from a first terminal adjacent to the first source / drain region to a second terminal adjacent to the second source / drain region, where the first terminal defines a first vertical plane, the first vertical plane being perpendicular to the lateral Y-direction; a portion of a gate structure underlying the semiconductor nanosheet and extending from the first termination to the second termination; and an inner spacer underlying the semiconductor nanosheet and abutting the first terminal of the portion of the gate structure, with the first vertical plane passing through the inner spacer.

Description

Technical Field

[0001] The present utility model relates to a semiconductor device and a method for forming the same, and particularly to an inner spacer. Background Art

[0002] The electronics industry has experienced a continuously increasing demand for smaller and faster electronic devices, which can support a larger number of more complex and sophisticated functions simultaneously. Therefore, there is an unceasing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). Currently, these goals have been mostly achieved by reducing the size of semiconductor integrated circuits (e.g., the minimum feature size), thereby improving mass production efficiency and reducing related costs. However, such size reduction also increases the complexity of the semiconductor manufacturing process. Thus, the continuous evolution in semiconductor integrated circuits and devices has also driven similar evolution in semiconductor manufacturing processes and technologies. Summary of the Utility Model

[0003] The purpose of the present utility model is to provide a semiconductor device to solve at least one of the above problems.

[0004] A semiconductor device includes: a first source / drain region separated from a second source / drain region in a transverse Y direction; a fin structure including semiconductor nanosheets, wherein the semiconductor nanosheets extend from a first terminal to a second terminal in the transverse Y direction, the first terminal is adjacent to the first source / drain region, and the second terminal is adjacent to the second source / drain region, wherein the first terminal defines a first vertical plane perpendicular to the transverse Y direction; a portion of a gate structure located under the semiconductor nanosheets and extending from the first terminal to the second terminal; and an inner spacer located under the semiconductor nanosheets and abutting the first terminal of the portion of the gate structure, wherein the first vertical plane passes through the inner spacer.

[0005] According to one embodiment of the present utility model, the inner spacer includes a core.

[0006] According to one embodiment of the present utility model, the core has a transverse width of 1 nm to 4 nm, and the core has a vertical height of 1 nm to 3 nm.

[0007] According to one embodiment of the present utility model, the inner spacer extends from an inner terminal to an outer terminal; the inner terminal abuts the first terminal of the portion of the gate structure; the outer terminal is separated from the first vertical plane by a maximum transverse spacing; and the maximum transverse spacing is 0.5 nm to 3 nm.

[0008] According to one embodiment of the present utility model, an outer terminal of the inner spacer is formed by an outer part and a central groove; a maximum lateral spacing is defined at a position on the outer part; a minimum lateral spacing is defined between the first vertical plane and the central groove; and the minimum lateral spacing is from 0 nm to 2 nm.

[0009] According to one embodiment of the present utility model, an inner terminal of the inner spacer is spaced apart from a first terminal of the semiconductor nanosheet by a lateral spacing.

[0010] According to one embodiment of the present utility model, a lateral width of the inner spacer is greater than the lateral spacing.

[0011] According to one embodiment of the present utility model, the lateral spacing is from 4 nm to 7 nm, and the lateral width is from 5 nm to 10 nm.

[0012] According to one embodiment of the present utility model, it further includes a bottom epitaxial region located under the first source / drain region, wherein the bottom epitaxial region is in contact with the inner spacer.

[0013] According to one embodiment of the present utility model, the portion of the gate structure further includes: a metal electrode; and a gate dielectric between the inner spacer and the metal electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The aspects of the embodiments of the present utility model will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present utility model.

[0015] Figure 1 is a perspective view of a semiconductor device during a manufacturing stage according to some embodiments.

[0016] Figure 2 is a cross-sectional schematic view of a semiconductor device during Figure 1 the manufacturing stage shown according to some embodiments.

[0017] Figure 3 is a focused cross-sectional schematic view of a semiconductor device showing an inner spacer according to some embodiments. Figure 2 according to some embodiments.

[0018] Figure 4 is a cross-sectional schematic view of a semiconductor device during Figure 1 the manufacturing stage shown according to some embodiments.

[0019] Figure 5 is a cross-sectional schematic view of a semiconductor device during Figure 4The semiconductor device shows a focused cross-sectional schematic diagram of an inner spacer.

[0020] Figure 6 According to some embodiments, it is a flowchart showing a forming method.

[0021] Figures 7 to 11 According to some embodiments, it is a perspective view of the structure of a semiconductor device during a continuous manufacturing stage.

[0022] Figure 12 According to some embodiments, the semiconductor device is in Figure 11 A cross-sectional schematic diagram of the structure.

[0023] Figure 13 According to some embodiments, it is a perspective view of the structure of a semiconductor device during a continuous manufacturing stage.

[0024] Figure 14 According to some embodiments, the semiconductor device is in Figure 13 A cross-sectional schematic diagram of the structure.

[0025] Figures 15 to 23 According to some embodiments, it is a cross-sectional schematic diagram of a partial structure of a semiconductor device during a continuous manufacturing stage.

[0026] Figure 24 According to some embodiments, it is a cross-sectional schematic diagram of the structure of a semiconductor device during a subsequent manufacturing stage.

[0027] The reference numerals are as follows:

[0028] 6-6: Line segment

[0029] 7-7: Line segment

[0030] 100: Substrate

[0031] 201: First terminal

[0032] 202: Second terminal

[0033] 210: Table portion

[0034] 212: Epitaxial stack

[0035] 214: Epitaxial layer

[0036] 216: Epitaxial layer

[0037] 217: Mask layer

[0038] 218: First mask layer

[0039] 219: Second mask layer

[0040] 220: Fin

[0041] 220a: Portion

[0042] 221: Isolation component

[0043] 222: Sacrificial gate structure

[0044] 223: Sacrificial gate dielectric

[0045] 224: Sacrificial gate electrode

[0046] 225: Mask layer

[0047] 226: Mask layer

[0048] 227: Mask layer

[0049] 230: Spacer

[0050] 231: Liner

[0051] 232: Main spacer layer

[0052] 233: Bottom gap surface

[0053] 234: Gap

[0054] 235: Fin segment

[0055] 236: Cavity

[0056] 238: First inner spacer material layer

[0057] 262: Gap sidewall

[0058] 270: Semiconductor material

[0059] 278: Second inner spacer material layer

[0060] 280: Semiconductor material

[0061] 290: Semiconductor nanosheet

[0062] 291: Nanosheet

[0063] 292: Nanosheet

[0064] 293: Nanosheet

[0065] 299: Vertical plane

[0066] 301: First terminal

[0067] 302: Second terminal

[0068] 336: Etched surface

[0069] 400: Inner spacer

[0070] 410: Inner terminal

[0071] 420: Outer terminal

[0072] 421: Exterior

[0073] 422: Central groove

[0074] 450: Core

[0075] 455: Inner wall

[0076] 500: Source / drain region

[0077] 501: First source / drain region

[0078] 502: Second source / drain region

[0079] 510: Epitaxial layer

[0080] 520: Epitaxial layer

[0081] 530: Epitaxial layer

[0082] 550: Bottom epitaxial region

[0083] 560: Bottom dielectric layer

[0084] 700: Spacer structure

[0085] 750: Interlayer dielectric

[0086] 800: Metal gate

[0087] 801: Terminal

[0088] 802: Terminal

[0089] 810: Gate dielectric

[0090] 820: Metal electrode

[0091] 900: Method

[0092] 1000: Semiconductor device

[0093] 2381: Remaining part

[0094] 2781: Remaining part

[0095] D1: Maximum lateral spacing

[0096] D2: Minimum lateral spacing

[0097] D3: Lateral spacing

[0098] D4: Lateral spacing

[0099] D5: Lateral spacing

[0100] D6: Lateral spacing

[0101] H1: Vertical height

[0102] S902: Operation

[0103] S904: Operation

[0104] S906: Operation

[0105] S908: Operation

[0106] S910: Operation

[0107] S912: Operation

[0108] S914: Operation

[0109] S916: Operation

[0110] S918: Operation

[0111] S920: Operation

[0112] S922: Operation

[0113] S924: Operation

[0114] S926: Operation

[0115] S928: Operation

[0116] S930: Operation

[0117] S932: Operation

[0118] S934: Operation

[0119] S936: Operation

[0120] W1: Lateral width Detailed implementation manner

[0121] Numerous different embodiments or examples are provided below for implementing different components of a transaction. Specific examples of components and configurations are described below to simplify the embodiments of the present utility model. Of course, these are merely examples and are not intended to limit the embodiments of the present utility model. For example, when it is described that the first component is formed on the second component, it may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components are formed between the first and second components such that the first and second components are not in direct contact. As used herein, "directly above" means the vertical alignment of components such that when the upper component is directly above the lower component, the vertical axis passes through both components. In addition, the present utility model may repeat reference symbols and / or letters in various examples. Such repetition is for the purpose of simplification and clarity and does not itself dictate the relationship between the various embodiments and / or configurations being discussed.

[0122] Furthermore, spatially relative terms such as "directly above", "above", "over", "higher than", "top", "below", "beneath", "under", "lower than", "bottom", "side", "positive slope", "negative slope", and similar terms may be used herein to describe the relationship between one element or component and other elements or components, as shown in the drawings. Spatially relative terms are intended to cover different orientations of an element in use or operation in addition to the orientation depicted in the drawings. When the device is turned to other orientations (rotated 90° or other orientations), the spatially relative descriptions used herein may be interpreted accordingly with respect to the rotated orientation.

[0123] All numbers representing materials, physical properties of materials, and / or amounts and ratios used herein should be understood to be modified by the term "about" unless otherwise explicitly indicated. When modifying a numerical value in the specification or claims of the invention, "about" indicates an interval of accuracy that is familiar or acceptable to those skilled in the art. Generally, such an interval of accuracy is ±10%. Thus, "about 10" means 9 to 11.

[0124] In a specific embodiment herein, a "material layer" is a film layer comprising at least 50 weight percent of an identified material, such as at least 60 weight percent of the identified material, or at least 75 weight percent of the identified material, or at least 90 weight percent of the identified material; and a film layer that is a "material" comprising at least 50 weight percent of the identified material, such as at least 60 weight percent of the identified material, at least 75 weight percent of the identified material, or at least 90 weight percent of the identified material. For example, in a specific embodiment, each of the titanium nitride layer and the titanium nitride film layer is a film layer of at least 50 weight percent, at least 60 weight percent, at least 75 weight percent, or at least 90 weight percent titanium nitride.

[0125] For simplicity, well-known techniques related to semiconductor device manufacturing may not be described in detail herein. Furthermore, the various operations and processes described herein may be incorporated into more comprehensive steps or processes that have additional functionality not described herein. In particular, the various processes in semiconductor device manufacturing are well known, and thus, for simplicity, many of the processes will only be briefly mentioned herein or will be completely omitted without providing well-known process details. Those skilled in the art will readily recognize, after reading this utility model, that the structures and various techniques disclosed herein can be employed and incorporated into various semiconductor devices and products. In addition, it should be noted that semiconductor device structures include various numbers of components, and a single component shown in the examples may represent multiple components.

[0126] The specific embodiments herein generally relate to multi-gate transistors. The gate structure of the multi-gate transistor is formed on at least two sides of the channel region. These multi-gate devices may include multi-gate devices of P-type metal-oxide semiconductor (MOS) or N-type metal-oxide semiconductor. Specific examples may be presented herein and may be referred to as gate all around (GAA) devices. A gate all around device includes any device having such a gate structure or a portion thereof, the gate structure of which is formed on four sides of the channel region (e.g., surrounding a portion of the channel region).

[0127] The structures presented herein also include embodiments having a channel region in the shape of a nanosheet. The term "nanosheet" represents any portion of material having nanoscale or even micron-scale dimensions, and regardless of whether this portion has an elongated shape in any cross-section. Thus, this term denotes an elongated material portion with a circular or substantially circular cross-section (e.g., a nanowire), as well as a columnar or strip-shaped material portion (including, for example, a cylinder or a substantially rectangular cross-section).

[0128] The embodiments presented herein may have one or more channel regions associated with a single or continuous gate structure. However, those skilled in the art should understand that this teaching can be applied to a single channel region or any number of channel regions. Those skilled in the art can understand that other examples of semiconductor devices may benefit from the concepts of this utility model.

[0129] As described herein, methods are performed to increase the lateral thickness of the inner spacer. Additionally, methods are performed to form an inner spacer that extends through the terminal of the channel region, such as through the terminal of a semiconductor nanosheet and into the source / drain region. In some embodiments, an inner spacer can be provided to increase the alternating current (AC) gain of the device. For example, the inner spacer can be used in a gate-all-around device to increase the AC gain. In some embodiments, an inner spacer can be provided to reduce the effective capacitance value (C eff ) of the device.

[0130] Furthermore, specific embodiments herein provide for forming a low-k dielectric core or air gap within the inner spacer. The presence of the low-k dielectric core or air gap within the inner spacer can reduce the effective capacitance value.

[0131] It should be noted that although the structure of the gate-all-around device is described herein and in the figures, it is contemplated that the methods described herein can be used to fabricate other device types, and the devices described herein can be other types of devices.

[0132] For the purposes of the discussion below, Figures 1 to 5 a portion of a semiconductor device 1000 is shown in accordance with the method described herein. Figure 1 Perspective views are shown of two inner spacer embodiments, such as an inner spacer without an internal core or air gap, and an inner spacer with an internal core or air gap. Figure 2 For Figure 1 a schematic cross-sectional view of a device with an inner spacer that does not have an internal core or air gap. Figure 3 For Figure 2 a focused view of the inner spacer of Figure 4 For Figure 1 a schematic cross-sectional view of a device with an inner spacer that has an internal core or air gap. Figure 5 For Figure 4 a focused view of the inner spacer of

[0133] As Figure 1 , Figure 2 , and Figure 4 shown, the semiconductor device 1000 includes a substrate 100, such as a semiconductor substrate.

[0134] In some embodiments, the substrate 100 may be formed of silicon (Si) and include silicon. Alternatively or additionally, the substrate 100 includes another elemental semiconductor, such as germanium (Ge); compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); alloy semiconductors, including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP). In another aspect, the substrate 100 is a semiconductor on insulator (SOI). The plurality of conductive and non-conductive thin films may include insulating or conductive materials. For example, the conductive materials include metals (such as aluminum (Al), copper (Cu), tungsten (W), nickel (Ni), titanium (Ti), platinum (Pt), or their alloys), other conductive substances (such as nitrides (e.g., titanium nitride (TiN) or tantalum nitride (TaN)) and carbides (e.g., titanium carbide (TiC) or tantalum carbide (TaC))). The insulating materials may include silicon oxide (SiO) or silicon nitride (SiN).

[0135] Such as Figure 1 , Figure 2 , and Figure 4As shown, the semiconductor device 1000 further includes fins 220. The fins 220 extend in the Y direction and are spaced apart from each other in the X direction. The fins 220 can be formed from the substrate 100. For example, the fins 220 can include a mesa portion 210 formed from the substrate 100. In addition, the fins 220 can include semiconductor nanosheets 290, including nanosheet 291, nanosheet 292, and nanosheet 293. Although Figure 1 three semiconductor nanosheets are shown, the fins 220 of the semiconductor device 1000 can include any suitable number of semiconductor nanosheets 290. Each fin 220 can include a lowest nanosheet 291 spaced apart from the mesa portion 210 in the vertical Z direction, and nanosheets 292 and 293 spaced apart from the lowest nanosheet 291 in the vertical Z direction.

[0136] During Figure 1 the manufacturing stage, an epitaxial layer 214 (sacrificial layer) is located above and below the semiconductor nanosheets 290. An example of the epitaxial layer 214 (sacrificial layer) is a semiconductor that can be selectively etched. For example, the semiconductor nanosheets 290 can be silicon, and the epitaxial layer 214 can be silicon germanium.

[0137] As Figures 1 to 5 shown, the semiconductor device 1000 also includes inner spacers 400. During Figures 1 to 5 the manufacturing stage, the inner spacers 400 are located at each terminal of each epitaxial layer 214 (sacrificial layer). The inner spacers 400 can be formed with or without a core 450 (or air gap). As used herein, an "air gap" is a volume that does not include solid components, but can include a gas (such as the ambient gas during formation). In some embodiments, the ambient gas is air.

[0138] The semiconductor device 1000 further includes source / drain regions 500. As used herein, "source / drain regions" can individually or collectively refer to a source region or a drain region, depending on the context. The source / drain regions 500 can include multiple film layers, such as multiple epitaxial layers 510, epitaxial layer 520, and epitaxial layer 530, and the source / drain regions 500 can be formed of the desired materials for n-type field effect transistors (NFETs) or p-type field effect transistors (PFETs).

[0139] As Figure 2 further shown, a bottom epitaxial region 550 can be located under the source / drain regions 500. In addition, a bottom dielectric layer 560 can be located between the bottom epitaxial region 550 and the source / drain regions 500 and extend between the inner spacers 400 on both sides.

[0140] During Figures 1 to 5During the manufacturing stage, a sacrificial gate structure 222 is located on the stack of each semiconductor nanosheet 290 and the epitaxial layer 214 (sacrificial layer).

[0141] In addition, a spacer structure 700 is adjacent to the sacrificial gate structure 222.

[0142] Referring Figures 2 to 5 , the semiconductor device 1000 includes a first source / drain region 501 and a second source / drain region 502, which are spaced apart in the lateral Y direction. In addition, the semiconductor device 1000 includes fins 220, which include semiconductor nanosheets 290. Each semiconductor nanosheet 290 extends from a first terminal 201 to a second terminal 202 in the lateral Y direction, with the first terminal 201 adjacent to the first source / drain region 501 and the second terminal 202 adjacent to the second source / drain region 502.

[0143] In Figures 2 to 5 , the epitaxial layer 214 (sacrificial layer) is located under the semiconductor nanosheets 290 and extends from a first terminal 301 to a second terminal 302. In addition, inner spacers 400 are located under the semiconductor nanosheets 290. Each inner spacer 400 abuts against the first terminal 301 or the second terminal 302 of the epitaxial layer 214 (sacrificial layer).

[0144] As shown, the vertical stack of each first terminal 201 (and the vertical stack of each second terminal 202) is aligned and defines a vertical plane 299, which is perpendicular to the lateral Y direction. As shown, the vertical plane 299 passes through each inner spacer 400 that abuts against the first terminal 301 of the epitaxial layer 214 (sacrificial layer). At the opposite terminal, a vertical plane (not labeled) passes through each inner spacer 400 that abuts against the second terminal 302 of the epitaxial layer 214.

[0145] As Figure 3 shown, each inner spacer 400 extends from an inner terminal 410 to an outer terminal 420. Thus, each inner spacer 400 terminates at the outer terminal 420. During Figures 1 to 5 the manufacturing stage, the inner terminal 410 abuts against the first terminal 301 of the epitaxial layer 214 (sacrificial layer). The outer terminal 420 abuts against the source / drain region 500.

[0146] In some embodiments, the outer terminal 420 is formed to have an exterior 421 and a central groove 422.

[0147] Each inner spacer 400 has a maximum width, e.g., a maximum lateral spacing D1 from the inner terminal 410 to the terminal position on the outer 421 of the outer terminal 420. In some embodiments, the maximum width is 4.5 nm to 10 nm. For example, the maximum width can be at least 4.5 nm, at least 5 nm, at least 5.5 nm, at least 6 nm, at least 6.5 nm, at least 7 nm, at least 7.5 nm, at least 8 nm, at least 8.5 nm, at least 9 nm, or at least 9.5 nm. Additionally, the maximum width can be at most 10 nm, at most 9.5 nm, at most 9 nm, at most 8.5 nm, at most 8 nm, at most 7.5 nm, at most 7 nm, at most 6.5 nm, at most 6 nm, at most 5.5 nm, or at most 5 nm.

[0148] Each inner spacer 400 has a minimum width, e.g., a minimum lateral spacing D2 from the inner terminal 410 to the central groove 422 of the outer terminal 420. In some embodiments, the minimum width is 4 nm to 7 nm. For example, the minimum width can be at least 4 nm, at least 4.5 nm, at least 5 nm, at least 5.5 nm, at least 6 nm, or at least 6.5 nm. Additionally, the minimum width can be at most 7 nm, at most 6.5 nm, at most 6 nm, at most 5.5 nm, at most 5 nm, or at most 4.5 nm.

[0149] Individual vertical planes 299 pass through each inner spacer 400. As Figure 3 shown, each inner spacer 400 extends from the inner terminal 410 through the vertical plane 299 to the outer terminal 420 (and particularly to the outer 421 of the outer terminal 420). Thus, each inner spacer 400 extends through the vertical plane 299 by a lateral spacing D3 from the vertical plane 299 to the outer 421. In some embodiments, the lateral spacing D3 is 0.5 nm to 3 nm. For example, the lateral spacing D3 can be at least 0.5 nm, at least 1 nm, at least 1.5 nm, at least 2 nm, or at least 2.5 nm. Additionally, the lateral spacing D3 can be at most 3 nm, at most 2.5 nm, at most 2 nm, at most 1.5 nm, or at most 1 nm.

[0150] Thus, the inner terminal 410 can be spaced from the vertical plane 299 by a lateral spacing D4. In some embodiments, the lateral spacing D4 is 4 nm to 7 nm. For example, the lateral spacing D4 can be at least 4 nm, at least 4.5 nm, at least 5 nm, at least 5.5 nm, at least 6 nm, or at least 6.5 nm. Additionally, the lateral spacing D4 can be at most 7 nm, at most 6.5 nm, at most 6 nm, at most 5.5 nm, at most 5 nm, or at most 4.5 nm.

[0151] The central groove 422 can be aligned with the individual vertical plane 299 such that the lateral spacing D5 defined between the central groove 422 and the vertical plane 299 can be 0. In some embodiments, the inner spacer 400 can extend through the vertical plane 299 to the central groove 422 such that the lateral spacing D5 is greater than 0. For example, the lateral spacing D5 can be from 0 nm to 2 nm. For example, the lateral spacing D5 can be at least 0.5 nm, at least 1 nm, or at least 1.5 nm. Additionally, the lateral spacing D5 can be at most 2 nm, at most 1.5 nm, at most 1 nm, or at most 0.5 nm. The lateral spacing D5 can represent the maximum lateral spacing between the vertical plane 299 and the central groove 422.

[0152] Figure 4 and Figure 5 shows the inner spacer 400, which includes a core 450 (or air gap). A porous film layer that can include a low dielectric constant dielectric material is filled into the core 450. As Figure 5 shown, the core 450 is confined or encapsulated by the inner walls 455 of the inner spacer 400. The core 450 has a lateral width W1 that extends between opposite sides of the inner walls 455 and a vertical height H1 that extends between opposite ends of the inner walls 455. In some embodiments, the lateral width W1 is from 1 nm to 4 nm. For example, the lateral width W1 can be at least 1 nm, at least 1.5 nm, at least 2 nm, at least 2.5 nm, at least 3 nm, or at least 3.5 nm. Additionally, the lateral width W1 can be at most 4 nm, at most 3.5 nm, at most 3 nm, at most 2.5 nm, at most 2 nm, or at most 1.5 nm. In some embodiments, the vertical height H1 is from 1 nm to 3 nm. For example, the vertical height H1 can be at least 1 nm, at least 1.5 nm, at least 2 nm, or at least 2.5 nm. Additionally, the vertical height H1 can be at most 3 nm, at most 2.5 nm, at most 2 nm, or at most 1.5 nm. In some embodiments, the volume of the core 450 (or air gap) is from 20% to 60% of the total volume of the individual inner spacer 400.

[0153] Due to the dimensions of the inner spacer 400 and the core 450 (or air gap) within the inner spacer 400, the AC gain of the device can be improved by 110% to 120%. Additionally, the effective capacitance value of the device can be reduced by 2% to 10%.

[0154] Referring Figure 6 to, in accordance with various aspects of the present invention, structures are shown in a flowchart (such as in accordance with Figures 1 to 5Method 900 for forming a multi-gate semiconductor device 1000 of an embodiment. As used herein, the term "multi-gate semiconductor device" is used to describe a semiconductor device (e.g., a transistor) having at least some gate material disposed on multiple sides of at least one channel. In some examples, the multi-gate semiconductor device may be referred to as a fully wrapped gate semiconductor device, which has gate material disposed on four sides of at least one channel member of the semiconductor device. The channel member may be referred to as a "nanosheet".

[0155] will Figure 6 be Figures 7 to 24 described in conjunction with Figures 7 to 24 which is some embodiments of method 900 according to the present utility model, showing the semiconductor device 1000 at various manufacturing stages. Method 900 is only an example and is not intended to limit the present utility model beyond what is specifically recited in the claims. Additional steps may be provided before, during, and after method 900, and some of the steps described may be moved, replaced, or eliminated for additional embodiments of method 900. Additional components may be added to the semiconductor device shown in the drawings, and some of the components described below may be replaced, modified, or removed in other embodiments of the semiconductor device.

[0156] Regarding other method embodiments and example semiconductor devices discussed herein, it should be understood that portions of the semiconductor device 1000 may be fabricated through general semiconductor technology process flows, and thus some processes are only briefly described herein. Additionally, the example semiconductor device may include various other devices and components, such as other types of devices (e.g., additional transistors, bipolar junction transistors (BJTs), resistors, capacitors, inductors, diodes, fuses, and / or other logic devices), but are simplified for a better understanding of the perspective of the present utility model. In some embodiments, the example device includes multiple semiconductor devices (e.g., transistors), which may include P-type field effect transistors, N-type field effect transistors, or other similar devices, and which may be interconnected. Furthermore, it should be noted that the process steps of method 900, including any descriptions provided with reference to the drawings, as well as the remaining methods and example drawings provided by the present utility model, are only exemplary and are not intended to limit beyond what is specifically recited in the following claims.

[0157] In operation S902, method 900 ( Figure 6 ) provides a substrate 100, such as Figure 7As shown. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 may include various film layers (including conductive or insulating layers) formed on the semiconductor substrate. The substrate 100 may include various doping configurations depending on design requirements well known in the art. For example, different doping profiles (such as P-type wells or N-type wells) may be formed in predetermined regions of different device types (such as N-type field effect transistors or P-type field effect transistors) on the substrate 100. Suitable doping may include ion implantation of dopants and / or diffusion processes, such as boron (B) for P-type wells and phosphor (P) for N-type wells. In some embodiments, the substrate 100 includes a single crystal semiconductor layer at least on the surface portion of the substrate 100. The substrate 100 may include single crystal semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaSbAs), and indium phosphide, but not limited thereto. Alternatively, the substrate 100 may include compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, the substrate 100 is formed of crystalline silicon.

[0158] As Figure 7 shown, in operation S904, method 900 ( Figure 6 ) forms one or more epitaxial layers on the substrate 100. In some embodiments, an epitaxial stack 212 is formed on the substrate 100. The epitaxial stack 212 includes epitaxial layers 214 of a first composition inserted between epitaxial layers 216 of a second composition. The first composition and the second composition may be different. Embodiments are possible where the first composition and the second composition have different oxidation rates and / or etch selectivities. In one embodiment, the epitaxial layer 214 is silicon germanium and the epitaxial layer 216 is silicon. In embodiments where the epitaxial layer 214 includes silicon germanium and the epitaxial layer 216 includes silicon, the silicon oxidation rate is less than the silicon germanium oxidation rate. It should be noted that Figure 7 shows three epitaxial layers 214 and three epitaxial layers 216, which are for illustrative purposes only and are not intended to limit beyond what is specifically recited in the claims. It should be understood that any number of epitaxial layers may be formed in the epitaxial stack 212; the number of film layers depends on the desired number of channel regions of the semiconductor device 1000. In some embodiments, the number of epitaxial layers 216 is between 2 and 10, such as 6 or 7.

[0159] In some embodiments, the epitaxial layer 214 has a thickness in the range of 5 nm to 15 nm. The thickness of the epitaxial layer 214 can be substantially uniform. In some embodiments, the epitaxial layer 216 has a thickness in the range of 5 nm to 15 nm. In some embodiments, the thickness of the epitaxial layer 216 can be substantially uniform. As will be described in detail below, the epitaxial layer 216 can serve as the channel region of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. The epitaxial layer 214 can serve to define the gap between adjacent channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations.

[0160] For example, the epitaxial growth of the epitaxial stack 212 can be performed by a molecular beam epitaxy (MBE) process, a metal organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial grown film layer (such as the epitaxial layer 216) includes the same material as the substrate 100. In some embodiments, the epitaxial layer 214 and the epitaxial layer 216 include materials different from the substrate 100. As described above, in at least some examples, the epitaxial layer 214 includes an epitaxially grown silicon germanium layer (Si 1-x Ge x , where x is from 0.10 to 0.55), and the epitaxial layer 216 includes an epitaxially grown silicon layer. Alternatively, in some embodiments, the epitaxial layer 214 or the epitaxial layer 216 can include other materials (such as germanium), compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide indium), or combinations thereof. As described, the materials of the epitaxial layer 214 and the epitaxial layer 216 can be selected based on providing different oxidation and etch selectivity properties. In various embodiments, the epitaxial layer 214 and the epitaxial layer 216 are substantially dopant-free (for example, having an extrinsic doping concentration of 0 cm -3 to 1×10 17 cm -3 ), for example, no intentional doping is performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 212 are silicon germanium layers (not shown). In alternative embodiments, the bottom layer of the epitaxial stack 212 is a silicon layer, and the top layer of the epitaxial stack 212 is a silicon germanium layer (not shown).

[0161] As Figure 8 shown, in operation S906, method 900 ( Figure 6)Patterning the epitaxial stack 212 to form semiconductor fins 220. In some embodiments, operation S906 includes forming a mask layer 217 on the epitaxial stack 212, as Figure 7 shown. The mask layer 217 includes a first mask layer 218 and a second mask layer 219. An example of the first mask layer 218 is a pad oxide layer formed of silicon oxide, and the first mask layer 218 can be formed by thermal oxidation. An example of the second mask layer 219 is formed of silicon nitride and can be formed by chemical vapor deposition (CVD) (including low-pressure chemical vapor deposition (LPCVD) and plasma-enhanced chemical vapor deposition (PECVD)), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. The mask layer 217 is patterned into a mask pattern by using patterning operations (including lithography and etching).

[0162] As Figure 8 shown, operation S906 then patterns the epitaxial stack 212 through the openings defined in the patterned mask layer 217 in an etching process, such as dry etching (e.g., reactive ion etch (RIE)), wet etching, and / or other suitable processes. The stacked epitaxial layers 214 and 216 are thus patterned into fins 220. Although Figure 8 shows the formation of one fin 220, any suitable number of fins 220 can be formed. Trenches are etched between adjacent fins 220.

[0163] In various embodiments, each fin 220 includes an upper portion (interleaved epitaxial layers 214 and 216) and a lower portion (or the mesa portion 210 formed by the etched substrate 100). Each fin 220 protrudes upward from the substrate 100 in the Z direction and extends in the length direction in the Y direction. The sidewalls of each fin 220 can be straight or inclined (not shown). In Figure 3 , additional fins can be spaced apart along the X direction. The fins 220 can have the same width or different widths.

[0164] As Figure 9 shown, in operation S908, method 900 ( Figure 6)An isolation component 221 (also referred to as a shallow trench isolation (STI) component) is formed of a dielectric layer in a trench adjacent to each fin 220. The isolation component 221 can be formed by first filling the trench surrounding each fin 220 with a dielectric material layer to cover the top surface and sidewalls of the fin 220 (not shown). The dielectric material layer can include one or more dielectric materials. Suitable dielectric materials for the dielectric layer can include silicon oxide, silicon nitride, silicon carbide, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited by any suitable technique, including thermal growth, flowable chemical vapor deposition (FCVD), high-density plasma chemical vapor deposition (HDP-CVD), physical vapor deposition, atomic layer deposition, and / or spin-on coating techniques. Then, the dielectric material layer is planarized by using, for example, chemical mechanical planarization (CMP) until the top surface of the mask layer 217 is exposed, and the dielectric material layer is etched to form the isolation component 221 (also referred to as the shallow trench isolation component), as Figure 4 shown. In the illustrated embodiment, the isolation component 221 is formed on the substrate 100. Any suitable etching technique can be used to etch the isolation component 221, including dry etching (such as reactive ion etching), wet etching, and / or other etching methods, and in the exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation component 221 without etching the fin 220. The mask layer 217 (shown in Figure 8 ) can also be removed before, during, and / or after etching the isolation component 221. In some embodiments, the mask layer 217 is removed by performing a chemical mechanical planarization process before etching the isolation component 221. In some embodiments, the mask layer 217 is removed by the etchant used to etch the isolation component 221.

[0165] As Figure 10 shown, in operation S910, method 900 ( Figure 6)Form a sacrificial (dummy) gate structure 222. The sacrificial gate structure 222 is formed on the portion of the fin 220 that is to be the channel region. The sacrificial gate structure 222 may extend over several adjacent fins (not shown). The sacrificial gate structure 222 is directly laid on and defines the channel region of the all-around gate device to be formed. Each sacrificial gate structure 222 includes a sacrificial gate dielectric 223 and a sacrificial gate electrode 224 on the sacrificial gate dielectric 223. As shown, the sacrificial gate structures 222 extend in the length direction in the X direction and are spaced apart in the Y direction.

[0166] First, the sacrificial gate structure 222 is formed by blanket depositing a sacrificial gate dielectric layer on the fin 220. Then, a sacrificial gate electrode layer is blanket deposited on the sacrificial gate dielectric layer and on the fin 220. The sacrificial gate dielectric layer includes silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from 100 nm to 200 nm. The sacrificial gate electrode layer includes silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from 1 nm to 5 nm. In some embodiments, a planarization operation is performed on the sacrificial gate electrode layer. Chemical vapor deposition (including low-pressure chemical vapor deposition and plasma-assisted chemical vapor deposition), physical vapor deposition, atomic layer deposition, or other suitable processes are used to deposit the sacrificial gate dielectric layer and the sacrificial gate electrode layer. A mask layer 225 is formed on the sacrificial gate electrode layer. The mask layer 225 may include a mask layer 226 (such as silicon oxide) and a mask layer 227 (such as silicon nitride). Subsequently, the mask layer 225 is patterned to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into the sacrificial gate structures 222 (including the sacrificial gate dielectric 223 and the sacrificial gate electrode 224).

[0167] As shown, portions of the fin 220 are exposed between the sacrificial gate structures 222 and on both sides of the sacrificial gate structures 222, thereby defining the source / drain regions. As used herein, "source / drain region" may refer to the source region or the drain region individually or collectively, depending on the context.

[0168] Continuing to refer to Figure 10 , in operation S912, method 900 ( Figure 6)By depositing a spacer material and then performing an etch, spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and on the sidewalls of the fins 220. The spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and / or combinations thereof. In some embodiments, each spacer 230 includes a plurality of film layers, such as a liner layer 231 and a main spacer layer 232 on the sidewalls of the liner layer 231.

[0169] For example, the spacers 230 may be formed by using, for example, a sub-atmospheric chemical vapor deposition (SACVD) process, a flowable chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or other suitable processes to deposit the spacer material (including a liner material layer and a dielectric material layer on the sacrificial gate structure 222).

[0170] As Figure 11 and Figure 12 shown, after depositing the liner material layer and the dielectric material layer, an (e.g., anisotropic) etch-back process is then performed in operation S914 to expose (and remove) a portion 220a (e.g., a source / drain region) of the fin 220 adjacent to and not covered by the sacrificial gate structure 222. In particular, method 900 ( Figure 6 ) recesses the portion of the fin 220 not covered by the sacrificial gate structure 222 to form a gap 234 (e.g., a cavity or a groove) in the source / drain region. It should be noted that Figure 11 only one sacrificial gate structure 222 and an adjacent portion of the fin 220 are shown, such that the source / drain region between the etched Figure 10 sacrificial gate structures 222 can be more clearly presented. Figure 12 For Figure 11 the structure is a cross-sectional schematic view along line 6-6, but similar to Figure 10 and Figure 12 shows two sacrificial gate structures 222 and fins 220 adjacent to the two sacrificial gate structures 222.

[0171] The liner material layer and the dielectric material layer may remain on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230, and on the sidewalls of the fins 220 as fin sidewall spacers 230. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multi-step etch process, and / or a combination thereof. The spacer 230 may have a thickness of 5 nm to 20 nm.

[0172] As is more clearly shown in Figure 12 , the stacked epitaxial layers 214 and 216 are etched downward in the source / drain regions, and the upper portion of the substrate 100 forming the fins 220. As a result, a bottom gap surface 233 is formed in the fins 220. In some embodiments, operation S914 forms the gap 234 by a suitable etch process (such as a dry etch process, a wet etch process, or a combination thereof). As a result of the etch process, the fin segments 235 at the upper portion of the fins 220 are defined and separated by the gap 234.

[0173] As Figure 13 and Figure 14 shown, in operation S916, method 900 ( Figure 6 ) etches the lateral termination of the epitaxial layer 214 in the Y direction to a recessed surface 336, thereby forming a cavity 236. For example, operation S916 may etch the epitaxial layer 214 to a lateral spacing D6. In an exemplary embodiment, the lateral spacing D6 is less than the maximum lateral spacing D1. In some embodiments, the lateral spacing D6 is 4 nm to 9.5 nm. For example, the lateral spacing D6 may be at least 4 nm, at least 4.5 nm, at least 5 nm, at least 5.5 nm, at least 6 nm, at least 6.5 nm, at least 7 nm, at least 7.5 nm, at least 8 nm, at least 8.5 nm, or at least 9 nm. Additionally, the lateral spacing D6 may be at most 9.5 nm, at most 9 nm, at most 8.5 nm, at most 8 nm, at most 7.5 nm, at most 7 nm, at most 6.5 nm, at most 6 nm, at most 5.5 nm, at most 5 nm, or at most 4.5 nm.

[0174] It should be noted that, similar to Figure 11 , Figure 13 , only one sacrificial gate structure 222 and an adjacent portion of the fins 220 are shown such that the source / drain regions between the etched sacrificial gate structures 222 can be presented.

[0175] Figure 14 For Figure 13 the structure is a cross-sectional schematic view along line segment 7-7, but similar to Figure 10 and Figure 12 , two sacrificial gate structures 222 and the fins 220 adjacent to the two sacrificial gate structures 222 are shown.

[0176] In some embodiments, the etch amount of the epitaxial layer 214 ranges from 3 nm to 8 nm, such as 4 nm to 7 nm. The epitaxial layer 214 can be selectively etched by using a wet etchant, such as ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), potassium hydroxide (KOH), hydrofluoric acid (HF), ozone (O3), hydrogen peroxide (H2O2), or hydrochloric acid (HCl) solution, but not limited thereto. Alternatively, operation S916 can first selectively oxidize the lateral terminals of the epitaxial layer 214 (which are exposed in the gap 234) to increase the etch selectivity between the epitaxial layer 214 and the epitaxial layer 216. In some examples, the all-around gate semiconductor device 1000 can be exposed to a wet oxidation process, a dry oxidation process, or a combination thereof to perform the oxidation process.

[0177] Figures 15 to 23 Focus on the gap 234 located between the fin segments 235 to further describe the method 900. As Figure 15 shown, the epitaxial layer 214 and the epitaxial layer 216 are staggered to form the gap sidewalls 262 on both sides. In addition, a bottom gap surface 233 is formed in the fin 220.

[0178] As Figure 16 shown, the method 900 ( Figure 6 ) can continue to operation S918, which forms a first inner spacer material layer 238 in the gap 234. In particular, the first inner spacer material layer 238 is deposited on the gap sidewalls 262 in the gap 234, including on the lateral terminals of the epitaxial layer 214, on the terminals, top surfaces, and bottom surfaces of the epitaxial layer 216, and on the bottom gap surface 233. The first inner spacer material layer 238 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or other suitable dielectric materials. In some embodiments, the first inner spacer material layer 238 is deposited as a conformal film layer. The first inner spacer material layer 238 can be formed by atomic layer deposition or any other suitable method. The first inner spacer material layer 238 can have a thickness in the range of 1 nm to 5 nm, such as 1 nm to 4 nm, 1 nm to 3 nm, or 1 nm to 2 nm.

[0179] As Figure 17 shown, the method 900 ( Figure 6)It can continue to operation S920, which trims the first inner spacer material layer 238. In some embodiments, the first inner spacer material layer 238 is removed by the first terminal 201 and the second terminal 202 of the epitaxial layer 216, and by the bottom gap surface 233, while the remaining portion 2381 of the first inner spacer material layer 238 remains on the first terminal 301 and the second terminal 302 of the epitaxial layer 214 (sacrificial layer), and on the top and bottom surfaces of the epitaxial layer 216.

[0180] Partial removal of the first inner spacer material layer 238 can be performed by an etching process, such as an anisotropic etching process, for example, a dry etching process. In some embodiments, the dry etching process uses an etchant including a fluorine-containing gas (such as sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), and / or hexafluoroethane (C2F6)), a chlorine-containing gas (such as chlorine (Cl2)), a bromine-containing gas (such as hydrogen bromide (HBr) and / or tribromomethane (CHBr3)), an oxygen-containing gas (such as oxygen (O2)), a helium-containing gas (such as helium (He)), an argon-containing gas (such as argon (Ar)), other suitable gases, or a combination thereof. Through this etching, the first inner spacer material layer 238 substantially remains within the cavity 236 due to the narrow space of the cavity 236. Generally speaking, plasma dry etching etches the film layer in a wide and flat area faster than in recesses (such as holes, notches, grooves, and / or cracks). Therefore, the first inner spacer material layer 238 can remain within the cavity 236.

[0181] As Figure 18 shown, method 900 ( Figure 6 ) can continue to operation S922, which selectively grows a semiconductor material 270 on the first terminal 201 and the second terminal 202 of the epitaxial layer 216, and on the bottom gap surface 233. For example, undoped silicon can be grown as the semiconductor material 270 on the semiconductor material formed by the epitaxial layer 216 and the bottom gap surface 233.

[0182] As Figure 18 shown, method 900 ( Figure 6) It can continue to operation S924, which forms a second inner spacer material layer 278 in the gap 234. In particular, the second inner spacer material layer 278 is deposited on the first inner spacer material layer 238 and on the semiconductor material 270. The second inner spacer material layer 278 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and / or other suitable dielectric materials. The thickness of the second inner spacer material layer 278 can be greater than the thickness of the first inner spacer material layer 238. For example, the second inner spacer material layer 278 can have a thickness of 4 nm to 12 nm, such as at least 5 nm, at least 6 nm, at least 7 nm, or at least 8 nm, and a maximum of 11 nm, a maximum of 10 nm, a maximum of 9 nm, or a maximum of 8 nm.

[0183] As shown, operation S924 can include forming a core 450 (or air gap). In particular, due to the overhanging profile of the semiconductor material 270 formed on the terminal of the epitaxial layer 216, a core 450 (or air gap) can be formed at the interface between the first inner spacer material layer 238 and the second inner spacer material layer 278 (as shown on the right side of Figure 19 ), or within the second inner spacer material layer 278.

[0184] Thus, in some embodiments, the core 450 filled with air is encapsulated by the second inner spacer material layer 278, or encapsulated by the first inner spacer material layer 238 and the second inner spacer material layer 278. In other embodiments, a low dielectric constant dielectric material (such as silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, silicon oxynitride) can be deposited to form the core 450. In some embodiments, the core 450 is at least partially encapsulated by the second inner spacer material layer 278. In some embodiments, the core 450 is porous.

[0185] As Figure 20 shown, the method 900 ( Figure 6 ) can continue to operation S926, which trims the second inner spacer material layer 278. In some embodiments, the second inner spacer material layer 278 is removed by the portions of the semiconductor material 270 on the first terminal 201 and the second terminal 202, and by most of the bottom gap surface 233, while the remaining portion 2781 of the second inner spacer material layer 278 remains covering the first inner spacer material layer 238.

[0186] The partial removal of the second inner spacer material layer 278 can be performed by an etching process (such as an anisotropic etching process, for example, a dry etching process). In some embodiments, the dry etching process uses an etchant including a fluorine-containing gas (such as sulfur hexafluoride, carbon tetrafluoride, trifluoromethane, difluoromethane, and / or hexafluoroethane), a chlorine-containing gas (such as chlorine gas), a bromine-containing gas (such as hydrogen bromide and / or bromoform), an oxygen-containing gas (such as oxygen gas), a helium-containing gas (such as helium gas), an argon-containing gas (such as argon gas), other suitable gases, or a combination thereof. Through this etching, the second inner spacer material layer 278 substantially fills the cavity 236. Generally speaking, plasma dry etching etches the film layer in a wide and flat area faster than in recesses (such as holes, notches, grooves, and / or cracks). Therefore, the second inner spacer material layer 278 remains within the cavity 236.

[0187] As a result of trimming the second inner spacer material layer 278, the inner spacer 400 is defined. Each inner spacer 400 is formed by the remaining portion 2381 of the first inner spacer material layer 238, the remaining portion 2781 of the second inner spacer material layer 278, and the core 450 (if present).

[0188] As Figure 21 shown, the method 900 ( Figure 6 ) can continue to operation S928, which etches the semiconductor material 270 grown in operation S922. In particular, a process of selectively etching undoped silicon can be performed to remove the semiconductor material 270. As a result, the semiconductor material 270 on the first terminal 201 and the second terminal 202 of the epitaxial layer 216 can be completely removed, and the first terminal 201 and the second terminal 202 of the epitaxial layer 216 can be exposed. In addition, the semiconductor material 270 on the bottom gap surface 233 can be recessed, as shown.

[0189] As Figure 22 shown, the method 900 ( Figure 6 ) can continue to operation S930, which selectively grows the semiconductor material 280 on the semiconductor material 270 and the bottom gap surface 233. As shown, the semiconductor material 280 does not grow on the first terminal 201 and the second terminal 202 of the epitaxial layer 216. The semiconductor material 280 can contact and extend between the lowest two inner spacers 400. Overall, the semiconductor material 270 and the semiconductor material 280 can form the bottom epitaxial region 550.

[0190] As Figure 23 shown, the method 900 ( Figure 6)It can continue to operation S932, which forms the bottom dielectric layer 560 on the bottom epitaxial region 550. For example, a dielectric material can be deposited and trimmed to form the bottom dielectric layer 560. As shown, the bottom dielectric layer 560 contacts and extends between the lowest two side inner spacers 400.

[0191] In addition, as Figure 23 shown, method 900( Figure 6 ) can continue to operation S934, which grows epitaxial material in the gap 234 to form the source / drain region 500. It should be noted that the source / drain region 500 can be formed by successively formed film layers. Additionally, the source / drain region 500 can be formed by a selected film layer for an N-type field-effect transistor or a P-type field-effect transistor. The source / drain region 500 can be formed by an epitaxial growth method (using chemical vapor deposition, atomic layer deposition, or molecular beam epitaxy). The source / drain region 500 can include silicon germanium for a P-type field-effect transistor and silicon for an N-type field-effect transistor.

[0192] At Figure 24 , method 900( Figure 6 ) can continue to the subsequent process of operation S936. For example, an interlayer dielectric (ILD) 750 can be formed between the source / drain region 500 and the spacer structure 700. In addition, the sacrificial gate structure 222 (including the sacrificial gate dielectric 223 and the sacrificial gate electrode 224), and the epitaxial layer 214 (sacrificial layer) are removed and replaced in a gate replacement process. For example, a metal gate 800 can be formed, including a gate dielectric 810 and a metal electrode 820. After removing the epitaxial layer 214 (sacrificial layer) and forming the metal gate 800, the remaining epitaxial layer 216 can be referred to as the semiconductor nanosheet 290. As shown, the gate dielectric 810 can be formed around the semiconductor nanosheet 290, and the metal electrode 820 can be deposited on the gate dielectric 810 to form the metal gate 800. As shown, the metal gate 800 abuts the inner terminal 410 of the inner spacer 400. In particular, the metal gate 800 extends from terminal 801 to terminal 802. Terminal 801 abuts the inner spacer 400, and terminal 802 abuts the inner spacer 400.

[0193] In a specific embodiment, according to some embodiments, the gate replacement process can include a line release process to form vertically spaced nanosheets. The line release process steps can also be referred to as sheet release process steps, sheet formation process steps, nanosheet formation process steps, or line formation process steps. In one embodiment, a wet etching process can be used to remove the epitaxial layer 214, which selectively removes the material of the epitaxial layer 214 (such as silicon germanium) without significantly removing the material of the epitaxial layer 216 (such as silicon). However, any suitable removal process can be utilized.

[0194] For example, in one embodiment, an etchant (such as hot hydrochloric acid) can be used to selectively remove the material (such as silicon germanium) of the epitaxial layer 214 without substantially removing the material (such as silicon) of the epitaxial layer 216. Additionally, the wet etching process can be carried out at a temperature of 400 °C to 600 °C (such as about 560 °C) for a time of 100 seconds to 600 seconds (such as about 300 seconds). However, any suitable etchant, process parameters, and time can be utilized.

[0195] According to some embodiments, the gate dielectric 810 includes a high-k (high dielectric constant) material (such as a material having a dielectric constant greater than or equal to 9), such as tantalum oxide (Ta2O5), aluminum oxide (Al2O3), hafnium (Hf) oxide, tantalum (Ta) oxide, titanium oxide, zirconium (Zr) oxide, aluminum oxide, lanthanum (La) oxide (such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO2), titanium oxide (TiO2)), combinations thereof, or other similar materials, and the gate dielectric 810 is deposited by atomic layer deposition, chemical vapor deposition, or other similar methods. In some embodiments, the gate dielectric 810 includes forming a nitrogen-doped oxide dielectric before forming a high-k (such as a dielectric constant greater than 13) dielectric material of the metal component. The gate dielectric 810 can be deposited to a thickness of 1 nm to 3 nm, although any suitable material and thickness can be utilized.

[0196] According to some embodiments, a plurality of film layers are used to form the metal electrode 820, and each film layer is sequentially deposited adjacent to each other using a high-conformity deposition process (such as atomic layer deposition), although any suitable deposition process can be utilized. According to some embodiments, a capping layer, a barrier layer, an N-type metal work function layer, a P-type metal work function layer, and a filling material can be provided.

[0197] A capping layer can be formed adjacent to the gate dielectric 810 and can be formed of a metal material such as tantalum nitride, titanium, titanium aluminum nitride (TiAlN), titanium aluminum (TiAl), platinum, tantalum carbide, tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium, titanium nitride, ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations thereof, or other similar materials. The metal material can be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or other similar methods, although any suitable deposition process can be used.

[0198] A barrier layer can be formed adjacent to the capping layer and the barrier layer can be formed of a metal material different from the capping layer. For example, the barrier layer can be formed of a metal material in one or more film layers such as titanium nitride, tantalum nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, ruthenium, molybdenum, tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations thereof, or other similar materials. The barrier layer can be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, or other similar methods, although any suitable deposition process can be used.

[0199] An N-type metal work function layer can be formed adjacent to the barrier layer. In one embodiment, the material of the N-type metal work function layer is tungsten, copper, aluminum copper (AlCu), titanium aluminum carbide (TiAlC), titanium aluminum nitride, titanium aluminum, platinum, titanium, titanium nitride, tantalum, tantalum nitride, cobalt (Co), nickel, silver (Ag), aluminum, tantalum aluminum, tantalum aluminum carbide, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, other suitable N-type work function materials, or combinations thereof. For example, the N-type metal work function layer can be deposited using an atomic layer deposition process, a chemical vapor deposition process, or other similar methods. However, any suitable materials and processes can be used to form the N-type metal work function layer.

[0200] A P-type metal work function layer can be formed adjacent to an N-type metal work function layer. In one embodiment, the material of the P-type metal work function layer is tungsten, aluminum, copper, titanium nitride, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum, tantalum nitride, cobalt, nickel, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, tantalum silicide (TaSi2), nickel silicide (NiSi2), manganese, zirconium, zirconium silicide (ZrSi2), tantalum nitride, ruthenium, aluminum copper, molybdenum, molybdenum disilicide (MoSi2), tungsten nitride, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicates, zirconium aluminates, combinations thereof, or other similar materials. Additionally, a deposition process (such as atomic layer deposition, chemical vapor deposition, or other similar methods) can be used to deposit the P-type metal work function layer, although any suitable deposition process can be used.

[0201] After forming the P-type metal work function layer, a filling material is deposited to fill the remaining openings. In one embodiment, the material of the filling material can be tungsten, aluminum, copper, aluminum copper, titanium, titanium aluminum nitride, titanium aluminum, platinum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, manganese, zirconium, titanium nitride, tantalum, tantalum nitride, cobalt, nickel, combinations thereof, or other similar materials, and a deposition process (such as plating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, combinations thereof, or other similar methods) can be used to form the filling material. However, any suitable material can be utilized.

[0202] After the openings left by removing the sacrificial gate structure 222 are filled, the materials of the metal electrode 820 and the gate dielectric 810 can be planarized to remove any material outside the openings, which are left by removing the sacrificial gate structure 222. In a particular embodiment, a planarization process (such as chemical mechanical planarization) can be used for the removal, although any suitable planarization and removal process can be utilized. According to some embodiments, the metal gate 800 can be formed to a vertical height of 70 nm to 85 nm in the Z direction. However, any suitable height can be used.

[0203] Subsequent processes can include forming and patterning additional dielectric and conductive layers, and general backend of line (BEOL) processes.

[0204] As described herein, embodiments provide inner spacers with a greater lateral width that extends across the inner terminals of the nanosheets and into the source / drain regions. Additionally, such inner spacers can be formed with an internal low dielectric constant core or air gap.

[0205] According to some embodiments of the present utility model, a method for forming a semiconductor device includes: etching a cavity in a vertical direction into a fin structure, the fin structure including at least one semiconductor nanosheet above a sacrificial layer, wherein forming the cavity has sidewalls; etching the sacrificial layer to a lateral spacing to an etched surface; forming an inner spacer laterally adjacent to the etched surface of the sacrificial layer, wherein a lateral width of the inner spacer is greater than the lateral spacing; and growing epitaxial material in the cavity to form source / drain regions laterally adjacent to the inner spacer.

[0206] In some embodiments, the lateral spacing is from 4 nm to 7 nm, and wherein the lateral width is from 5 nm to 10 nm. In some embodiments, forming the inner spacer has an inner core, and air or a low dielectric constant material is filled into the inner core. In some embodiments, the inner core has a lateral width of from 1 nm to 4 nm, and the inner core has a vertical height of from 1 nm to 3 nm. In some embodiments, the etched surface is laterally spaced from a terminal of the semiconductor nanosheet; the terminal of the semiconductor nanosheet defines a vertical plane; and the vertical plane passes through the inner spacer. In some embodiments, the terminal of the semiconductor nanosheet defines a vertical plane; the inner spacer extends laterally from the etched surface to an outer terminal; the outer terminal is laterally spaced from the vertical plane by a maximum lateral spacing; and the maximum lateral spacing is from 0.5 nm to 3 nm. In some embodiments, an outer terminal of the formed inner spacer has an outer and a central groove; a position on the outer defines the maximum lateral spacing; a minimum lateral spacing is defined between the vertical plane and the central groove; and the minimum lateral spacing is from 0 nm to 2 nm.

[0207] According to other embodiments of the present utility model, a method for forming a semiconductor device includes: etching a cavity in a vertical direction into a fin structure, the fin structure including semiconductor nanosheets above a sacrificial layer; performing a lateral etching process to etch the sacrificial layer in a lateral direction perpendicular to the vertical direction, wherein forming the sacrificial layer has an etched surface; depositing a first inner spacer layer in the cavity, wherein the first inner spacer layer is adjacent to the semiconductor nanosheets and on the etched surface of the sacrificial layer; removing the first inner spacer layer from the semiconductor nanosheets, wherein a remaining portion of the first inner spacer layer remains on the etched surface of the sacrificial layer; growing semiconductor material on the semiconductor nanosheets; depositing a second inner spacer layer in the cavity, wherein the second inner spacer layer is adjacent to the semiconductor material and the remaining portion of the first inner spacer layer; and removing the second inner spacer layer from the semiconductor material, wherein a remaining portion of the second inner spacer layer remains on the remaining portion of the first inner spacer layer.

[0208] In some embodiments, the method of forming a semiconductor device further includes removing semiconductor material from a semiconductor nanosheet. In some embodiments, the method of forming a semiconductor device further includes selectively growing additional semiconductor material at the bottom of a cavity. In some embodiments, the method of forming a semiconductor device further includes: forming a dielectric layer on the additional semiconductor material at the bottom of the cavity; and growing an epitaxial material on the dielectric layer in the cavity to form source / drain regions. In some embodiments, the remaining portions of the first inner spacer layer and the second inner spacer layer form an inner spacer; the semiconductor nanosheet terminates at a terminal that abuts the source / drain region; the terminal defines a vertical plane; and the vertical plane passes through the inner spacer. In some embodiments, the remaining portions of the first inner spacer layer and the second inner spacer layer form an inner spacer; the semiconductor nanosheet terminates at a terminal that abuts the cavity; and the inner spacer extends laterally past the terminal of the semiconductor nanosheet and into the cavity. In some embodiments, depositing the second inner spacer layer in the cavity includes trapping an air pocket within the second inner spacer layer. In some embodiments, the air pocket has a lateral width of 1 nm to 4 nm, and the air pocket has a vertical height of 1 nm to 3 nm.

[0209] According to other embodiments of the present invention, a semiconductor device includes: a first source / drain region, separated from a second source / drain region in a lateral Y direction; a fin structure including a semiconductor nanosheet, wherein the semiconductor nanosheet extends from a first terminal to a second terminal in the lateral Y direction, the first terminal being adjacent to the first source / drain region and the second terminal being adjacent to the second source / drain region, wherein the first terminal defines a first vertical plane perpendicular to the lateral Y direction; a portion of a gate structure located under the semiconductor nanosheet and extending from the first terminal to the second terminal; and an inner spacer located under the semiconductor nanosheet and abutting the first terminal of the portion of the gate structure, wherein the first vertical plane passes through the inner spacer.

[0210] In some embodiments, the inner spacer includes a dielectric material surrounding a core formed of air or a low dielectric constant dielectric material. In some embodiments, the core has a lateral width of 1 nm to 4 nm, and the core has a vertical height of 1 nm to 3 nm. In some embodiments, the inner spacer extends from an inner terminal to an outer terminal; the inner terminal abuts the first terminal of the portion of the gate structure; the outer terminal is spaced from the first vertical plane by a maximum lateral spacing; and the maximum lateral spacing is 0.5 nm to 3 nm. In some embodiments, the outer terminal of the inner spacer is formed by an outer and a central groove; a position on the outer defines the maximum lateral spacing; a minimum lateral spacing is defined between the first vertical plane and the central groove; and the minimum lateral spacing is 0 nm to 2 nm.

[0211] The foregoing outlines the features of several embodiments so that those skilled in the art can better understand the viewpoints of the embodiments of the present utility model. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present utility model to achieve the same purposes and / or advantages as those introduced herein. Those skilled in the art should also understand that such structures with similar effects do not depart from the spirit and scope of the present utility model, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present utility model.

Claims

1. A semiconductor device, characterized in that: include: a first source / drain region separated from a second source / drain region in a lateral Y direction; A fin structure, comprising a semiconductor nanosheet, wherein the semiconductor nanosheet extends from a first terminal to a second terminal in the lateral Y direction, the first terminal is adjacent to the first source / drain region, and the second terminal is adjacent to the second source / drain region, wherein the first terminal defines a first vertical plane, and the first vertical plane is perpendicular to the lateral Y direction; a portion of a gate structure disposed below the semiconductor nanosheet and extending from the first terminal to the second terminal; and An inner spacer is located below the semiconductor nanosheet and abuts the first terminal of the portion of the gate structure, wherein the first vertical plane passes through the inner spacer.

2. The semiconductor device according to claim 1, wherein The inner spacer includes a core.

3. The semiconductor device according to claim 2, wherein: The core has a lateral width of 1 nm to 4 nm, and the core has a vertical height of 1 nm to 3 nm.

4. The semiconductor device according to claim 1, wherein The inner spacer extends from an inner terminal end to an outer terminal end; The inner terminal abuts the first terminal of the portion of the gate structure; The outer terminal end is spaced from the first vertical plane to a maximum lateral spacing; and The maximum lateral spacing is 0.5 nm to 3 nm.

5. The semiconductor device according to claim 4, wherein: forming the outer terminal end of the inner spacer with an outer portion and a central recess; A position on the outer portion defines the maximum lateral spacing; defining a minimum lateral spacing between the first vertical plane and the central recess; and The minimum lateral spacing is 0 nm to 2 nm.

6. The semiconductor device according to claim 4, wherein: The inner terminal of the inner spacer is spaced apart from the first terminal of the semiconductor nanosheet by a lateral distance.

7. The semiconductor device according to claim 6, wherein: A lateral width of the inner spacer is greater than the lateral spacing.

8. The semiconductor device according to claim 7, wherein: The lateral spacing is 4 nm to 7 nm, and the lateral width is 5 nm to 10 nm.

9. The semiconductor device according to claim 1, wherein: The invention also includes a bottom epitaxial region located below the first source / drain region, wherein the bottom epitaxial region contacts the inner spacer.

10. The semiconductor device according to claim 1, wherein The portion of the gate structure further includes: a metal electrode; and A gate dielectric is between the inner spacer and the metal electrode.

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