Silicon carbide MOSFET
By setting the P-Well region and diode region in the center area of the epitaxial layer of the silicon carbide MOSFET, and setting the interlaced P-Sic and N-Sic at the margin of the epitaxial layer, the risk of high temperature failure in the SiCMOSFET chip when the junction temperature in some areas does not reach the limit is solved, and the uniformity of the overall temperature of the chip and the improvement of the reverse bias leakage current are achieved.
Patent Information
- Application Number
- CN202421771356.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-25
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-07-25
AI Technical Summary
Existing SiCMOSFET chips have the risk of high temperature failure when the junction temperature in some areas does not reach the limit, especially in the central and peripheral areas, high temperatures are prone to accumulate.
The P-Well region and the diode region are provided in the central area of the epitaxial layer of the silicon carbide MOSFET, and the interlaced P-Sic and N-Sic are provided at the margins of the epitaxial layer, so as to utilize the effect of applying high voltage and high temperatures in the P-Sic and N-Sic at different times.
It effectively reduces the junction temperature in the center of the chip, so that the overall chip can show a relatively uniform temperature, improves the device's long-term high temperature, and reduces the reverse bias leakage current.
Smart Images
Figure CN223040477U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a silicon carbide MOSFET. Background Art
[0002] MOSFET is one of the most widely used device structures in power devices. Due to the absence of charge storage effect, silicon carbide MOSFET has better switching characteristics and lower switching losses compared with bipolar devices. And the devices made of the third-generation semiconductor materials represented by silicon carbide have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance. As a representative of SiC devices, SiCMOSFET has many excellent characteristics such as low on-resistance, fast switching speed, and high operating frequency, and has been gradually popularized and used in application scenarios such as electric vehicles, charging piles, new energy power generation, industrial control, and flexible DC power transmission. Existing SiCMOSFETs generally have difficulty in withstanding high junction temperatures, resulting in a risk of high-temperature failure of SiCMOSFET chips even when the junction temperatures in some areas do not reach the limit, and this part of the high temperature often accumulates in the central area and the periphery. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a silicon carbide MOSFET to solve the problems existing in the background art.
[0004] Technical solution of the utility model: A silicon carbide MOSFET includes an N-type substrate, an epitaxial layer disposed thereon, and a drain below. A P-Well region and a diode region are provided in the central region of the epitaxial layer. The P-Well region is wrapped around the periphery of the diode region. A side P-type body is provided at the margin of the epitaxial layer. Interlaced P-type-SiC and N-type-SiC are provided on the side P-type body. Both the P-type-SiC and the N-type-SiC penetrate into the side P-type body. One side of both the P-Well region and the diode region away from the side P-type body is close to the margin of the epitaxial layer.
[0005] Preferably, both the P-Well region and the diode region are formed by multiple ion implantations after shallow trench etching, and the depth of the side P-type body is greater than the depth of the P-Well region.
[0006] Preferably, the distance between the P-Well region and the diode region is between 1.1 μm and 8.0 μm.
[0007] Preferably, the interlaced P-type-SiC and N-type-SiC are wound around each other, and the P-type-SiC and the N-type-SiC partially penetrate into each other.
[0008] Preferably, a source electrode is provided at the top of the side P-type body, and an integrated gate electrode is provided at the top of the side P-type body and the diode region.
[0009] Compared with the existing technology, the beneficial effects of the present utility model are as follows: In this solution, a P-Well region and a diode region are provided in the middle of the epitaxial layer. Both are located in the central region of the chip and are set to the maximum width, so the junction temperature in the center of the chip can be effectively reduced. Therefore, the overall temperature of the chip is relatively uniform. And then, in combination with the P-type-Sic and N-type-Sic at the margin of the epitaxial layer, by using the effect of not applying high voltage and high temperature to the P-type-Sic and N-type-Sic simultaneously, the situation of the device being subjected to high temperature for a long time can be improved, and the reverse bias leakage current situation can also be improved. Description of the Drawings
[0010] Figure 1 FIG. is a schematic structural diagram of a silicon carbide MOSFET proposed by the present utility model;
[0011] Figure 2 FIG. is a top view structural diagram of a silicon carbide MOSFET proposed by the present utility model.
[0012] Reference Numerals: 1, drain electrode; 2, N-type substrate; 3, epitaxial layer; 4, P-Well region; 5, diode region; 6, side P-type body; 7, P-type-Sic; 8, N-type-Sic; 9, gate electrode; 10, source electrode. Detailed Embodiments
[0013] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments.
[0014] Refer to the attached Figure 1-2 As shown in the figure, a silicon carbide MOSFET includes an N-type substrate 2 and an epitaxial layer 3 provided thereon, as well as a drain electrode 1 below. A P-Well region 4 and a diode region 5 are provided in the central region of the epitaxial layer 3. The P-Well region 4 is in a wrapped shape around the diode region 5. A side P-type body 6 is provided at the margin of the epitaxial layer 3. Interleaved P-type-Sic 7 and N-type-Sic 8 are provided on the side P-type body 6. Both the P-type-Sic 7 and N-type-Sic 8 penetrate into the side P-type body 6. The sides of the P-Well region 4 and the diode region 5 away from the side P-type body 6 are both close to the margin of the epitaxial layer 3. A source electrode 10 is provided at the top of the side P-type body 6, and an integrated gate electrode 9 is provided at the top of the side P-type body 6 and the diode region 5.
[0015] In this embodiment, specifically, both the P-Well region 4 and the diode region 5 are formed by multiple ion implantations after shallow trench etching. The distance between the P-Well region 4 and the diode region 5 is between 1.1 μm and 8.0 μm, and the depth of the side P-type body 6 is greater than the depth of the P-Well region 4. In this embodiment, the P-Well region 4 is formed by ion implantation erosion by expanding outward from the central region of the epitaxial layer 3, and then the installation region of the diode region 5 is eroded in this way. Moreover, the margins of the P-Well region 4 and the diode region 5 gradually approach the margin of the epitaxial layer 3, making it have a larger range. Then, combined with the side P-type bodies 6 on both sides, it is stably rectangular, and specifically...
[0016] Furthermore, in this embodiment, an external mask is required during ion implantation, so that an n+ region is formed in the source region within the P-Well region 4. It should be noted that the minimum width range of the n+ region is: 0.2 μm - 2.0 μm; the ion implantation depth of the n+ region is 0.3 μm - 0.8 μm; the ion impurity concentration of the n+ region is 1×10^12 cm^-3 - 1×10^13 cm^-3. With such a setting, the integrated diode p region and the Pwell region are increased within the maximum range from the edge to the central region of the silicon carbide MOSFET chip, enhancing the conduction performance and the surge current resistance ability of the diode. Since both are located in the central region of the chip and the width is set to the maximum, the junction temperature in the center of the chip can be effectively reduced. Therefore, the overall chip shows a relatively uniform temperature.
[0017] It should also be noted that in this embodiment, the staggered P-type - Sic7 and N-type - Sic8 are wound around each other, and the P-type - Sic7 and N-type - Sic8 partially penetrate each other. The P-type - Sic7 and N-type - Sic8 diffuse into the P-type body to form different source regions, and both are polycrystalline structures. When operating, since the P-type - Sic7 and N-type - Sic8 are not simultaneously subjected to high temperature and high pressure, the high temperature and high pressure in this region are relatively small during the same period. And in this solution, there is also a mutually penetrating part between the P-type - Sic7 and N-type - Sic8, which will relieve a part of the high temperature and high pressure received.
[0018] In this solution, by setting the P-Well region and the diode region in the middle of the epitaxial layer, since both are located in the central region of the chip and the width is set to the maximum, the junction temperature in the center of the chip can be effectively reduced. Therefore, the overall chip shows a relatively uniform temperature. And then, in cooperation with the P-type - Sic and N-type - Sic at the margin of the epitaxial layer, by using the effect of not applying high voltage and high temperature to the P-type - Sic and N-type - Sic simultaneously, the situation of the device being subjected to high temperature for a long time can be improved, and the situation of reverse bias leakage current can also be improved.
[0019] The above are only the preferred specific embodiments of the present utility model, but the protection scope of the present utility model is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present utility model, according to the technical solution of the present utility model and its inventive concept, making equivalent replacements or changes should be covered within the protection scope of the present utility model.
Claims
1. A silicon carbide MOSFET, comprising an N-type substrate (2), an epitaxial layer (3) disposed thereon, and a drain (1) thereunder, characterized in that: A P-Well region (4) and a diode region (5) are provided in the central region of the epitaxial layer (3); the P-Well region (4) is located in a wrapped shape outside the diode region (5); a side P-type body (6) is provided at the edge of the epitaxial layer (3); staggered P-type-Sic (7) and N-type-Sic (8) are provided on the side P-type body (6); the P-type-Sic (7) and the N-type-Sic (8) are both infiltrated into the side P-type body (6); and the sides of the P-Well region (4) and the diode region (5) away from the side P-type body (6) are both close to the edge of the epitaxial layer (3).
2. A silicon carbide MOSFET according to claim 1, characterized in that: The P-Well region (4) and the diode region (5) are both formed by shallow trench etching followed by multiple ion implantations, and the depth of the side P-type body (6) is greater than the depth of the P-Well region (4).
3. A silicon carbide MOSFET according to claim 2, characterized in that: The distance between the P-Well region (4) and the diode region (5) is between 1.1 μm and 8.0 μm.
4. The silicon carbide MOSFET according to claim 1, characterized in that: The staggered P-type-Sic (7) and the N-type-Sic (8) are intertwined with each other, and the P-type-Sic (7) and the N-type-Sic (8) partially penetrate each other.
5. The silicon carbide MOSFET according to claim 1, characterized in that: A source electrode (10) is provided on the top of the side P-type body (6), and an integrated gate electrode (9) is provided on the top of the side P-type body (6) and the diode region (5).