Semiconductor device with groove structure
By setting multiple groove structures in the dielectric layer and setting a metal field plate structure thereon, the one-time formation of multi-layer field plates is achieved, solving the problems of high cost and low efficiency of multi-layer field plate production process in the prior art, and improving the reliability and production efficiency of the device.
Patent Information
- Application Number
- CN202422207069.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-06-27
- Estimated Expiration
- 2034-09-10
AI Technical Summary
When making multi-layer field plates, existing gallium nitride power devices have high process and time costs and low production efficiency.
By providing multiple independent groove structures with different depths and widths in the dielectric layer, it is only necessary to provide a metal field plate structure on these groove structures to form a multi-layer field plate at one time, reducing the lithography and etching steps.
It reduces process cost and time, improves production efficiency, reduces the number of deposition and etching of media and metals, reduces the possibility of etching damage, and improves the reliability of the device.
Smart Images
Figure CN223040480U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and specifically relates to a semiconductor device with a groove structure. Background Art
[0002] With the development of science and technology, semiconductor devices are increasingly widely used in various fields. Among them, gallium nitride high electron mobility transistors (GaN HEMT, GaN High Electron Mobility Transistors, hereinafter referred to as gallium nitride power devices), as representatives of wide bandgap (WBG, Wide Bandgap) power semiconductor devices, have great potential in high-frequency power applications.
[0003] In the design of gallium nitride power devices, the breakdown voltage capability of the device is a very important performance parameter. To improve the breakdown voltage capability of the device, the prior art generally weakens the electric field spikes originally present near the gate and modulates the electric field distribution by setting multiple field plates in the device, thereby improving the breakdown voltage of the device.
[0004] However, in the research and practice of the prior art, the inventors of this application found that in the process of manufacturing the device, in order to implement multiple field plates, it is often necessary to perform etching of multiple dielectrics and metals and multiple photolithographies. For example, in some common structures in the industry, for each additional field plate, at least one additional photolithography and etching step are required. Therefore, as the number of field plates increases, the process cost and time cost will also increase significantly. That is, the prior art not only has a high process cost but also a low manufacturing efficiency. Summary of the Invention
[0005] An embodiment of this application provides a semiconductor device with a groove structure, which can reduce the process cost and time of manufacturing multiple field plates and improve the manufacturing efficiency.
[0006] The semiconductor device includes:
[0007] A substrate;
[0008] An epitaxial layer disposed on the substrate;
[0009] A source metal and a drain metal disposed on the epitaxial layer;
[0010] A dielectric layer disposed on the epitaxial layer, the source metal, and the drain metal; wherein, the dielectric layer includes a plurality of independent groove structures with different depths and widths;
[0011] A gate metal disposed on the groove structure with the maximum depth;
[0012] A metal field plate structure is disposed on other groove structures except the groove structure with the maximum depth.
[0013] In addition, an embodiment of the present application further provides another semiconductor device with a groove structure, including:
[0014] A substrate;
[0015] An epitaxial layer disposed on the substrate;
[0016] A source metal, a drain metal, and a gate metal disposed on the epitaxial layer;
[0017] A dielectric layer disposed on the epitaxial layer, the source metal, the drain metal, and the gate metal; wherein, the dielectric layer includes a plurality of independent groove structures with different depths and widths;
[0018] A metal field plate structure disposed on the groove structure.
[0019] Optionally, in some embodiments of the present application, the semiconductor device further includes a fourth interconnect metal;
[0020] Since the dielectric layer of the semiconductor device with a groove structure according to the embodiment of the present application includes a plurality of independent groove structures with different depths and widths, therefore, by only disposing a metal field plate structure on these groove structures with different depths, a multi-layer field plate can be formed at one time, that is to say, by only adjusting the depth and number of the groove structures, the effect of any multi-layer field plate can be achieved, without the need for layer-by-layer processing of the field plate. Compared with the existing solution where at least one additional photolithography and etching step is required for each additional layer of the field plate, the process cost and time can be greatly reduced, and the manufacturing efficiency can be improved; moreover, since the multi-layer field plate is formed at one time, the number of depositions and etchings of the dielectric and metal can also be reduced, and the possibility of etching damage can be greatly reduced, making the quality of the dielectric under the field plate higher, which is beneficial to improving the reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.
[0022] Figure 1 It is a schematic structural diagram of a semiconductor device with a groove structure provided by an embodiment of the present application;
[0023] Figure 2It is another schematic structural diagram of the semiconductor device with a groove structure provided by the embodiments of the present application;
[0024] Figure 3 It is a process example diagram of the semiconductor device with a groove structure provided by the embodiments of the present application;
[0025] Figure 4 It is another schematic structural diagram of the semiconductor device with a groove structure provided by the embodiments of the present application;
[0026] Figure 5 It is another schematic structural diagram of the semiconductor device with a groove structure provided by the embodiments of the present application;
[0027] Figure 6 It is another schematic structural diagram of the semiconductor device with a groove structure provided by the embodiments of the present application. Detailed implementation manners
[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.
[0029] The embodiments of the present application provide a semiconductor device with a groove structure. The following will be described in detail respectively.
[0030] A semiconductor device with a groove structure includes a substrate, an epitaxial layer, a source ohmic metal, a drain ohmic metal, a dielectric layer (also referred to as a dielectric layer), a gate ohmic metal, and a metal field plate structure; wherein:
[0031] The epitaxial layer is disposed on the substrate; the source ohmic metal and the drain ohmic metal are disposed on the epitaxial layer, and the dielectric layer is disposed on the epitaxial layer, the source ohmic metal, and the drain ohmic metal (the dielectric layer may include a gate dielectric layer 109, a first dielectric layer 108, and a second dielectric layer 105, and the material of the gate dielectric layer 109 is denser than the materials of the first dielectric layer 108 and the second dielectric layer 105); wherein, the dielectric layer includes a plurality of independent groove structures with different depths and widths, the gate ohmic metal is disposed on the groove structure with the maximum depth, and the metal field plate structure is disposed on the other groove structures except the groove structure with the maximum depth.
[0032] Optionally, the semiconductor device may further include a first metal layer and a second metal layer, where:
[0033] The first metal layer is disposed on the groove structure with the maximum depth to form a gate metal; the second metal layer is disposed on the other groove structures except the groove structure with the maximum depth to form a metal field plate structure.
[0034] For example, specifically, the first metal layer may be deposited on the deepest groove structure to obtain the gate metal, and the second metal layer may be deposited on the other groove structures except the groove structure with the maximum depth, such as depositing the field plate metal, so that the second metal layers deposited on the groove structures with different heights can serve as field plates of different layers. Then, by photolithography and metal etching of the second metal layer, a multi-layer metal field plate structure can be obtained.
[0035] Among them, the material selection of the first metal layer and the second metal layer can be determined according to the requirements of the actual device and process conditions. For example, metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or nickel (Ni) can be used, or their alloys or compounds can also be used, etc., which are not limited herein.
[0036] Among them, the groove structure closest to the gate metal has the deepest depth, and the groove structures farther away from this groove structure have shallower depths; the width of the step structure closest to the gate metal is the smallest, and the width of the step structures farther away from the gate metal is larger.
[0037] For example, as Figure 1 shown, taking the production of the gate metal at the groove structure G3 as an example, the depth of the groove structure G3 is the deepest. On the right side of G3, the depth of the groove structure G4 is the second deepest, the groove structure G5 is shallower than G4, the groove structure G6 is shallower than G5, and since the groove structure G7 is the farthest from G3, its depth is the shallowest; similarly, on the left side of G3, the depths of the groove structures from deep to shallow are G2 and G1 in turn.
[0038] Optionally, the substrate material of the semiconductor device can be selected according to the required semiconductor material and device performance. For example, the substrate material may include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or gallium oxide (GaO), etc.
[0039] Optionally, the metal field plate structure can be disposed on both sides of the gate metal, or the metal field plate structure can also be disposed between the gate metal and the source metal.
[0040] For example, as Figure 2As shown, the semiconductor device may include a substrate 101, an epitaxial layer 102 disposed on the substrate 101, a source metal 103 and a drain metal 104 disposed on the epitaxial layer 102, and a dielectric layer disposed on the epitaxial layer 102, the source metal 103, and the drain metal 104. Among them, the dielectric layer includes a plurality of independent groove structures with different depths and widths. The gate metal 106 is disposed on the groove structure with the maximum depth, while the metal field plate structure 107 is disposed on the other groove structures except the groove structure with the maximum depth and on both sides of the gate metal 106.
[0041] For another example, as Figure 3 shown, the semiconductor device may include a substrate 101, an epitaxial layer 102 disposed on the substrate 101, a source metal 103 and a drain metal 104 disposed on the epitaxial layer 102, and a dielectric layer disposed on the epitaxial layer 102, the source metal 103, and the drain metal 104. Among them, the dielectric layer includes a plurality of independent groove structures with different depths and widths. The gate metal 106 is disposed on the groove structure with the maximum depth, while the metal field plate structure 107 is disposed on the other groove structures except the groove structure with the maximum depth and between the gate metal 106 and the source metal 103.
[0042] Optionally, whether the gate metal 106 and the metal field plate structure 107 are connected can be determined according to the requirements of actual applications.
[0043] For example, if a gate field plate is needed, the gate metal 106 can be connected to the metal field plate structure 107.
[0044] Among them, there are various ways to connect the gate metal 106 and the metal field plate structure 107. For example, as Figure 2 and Figure 3 shown, during deposition, the gate metal 106 and the metal field plate structure 107 can be directly connected through deposited metal layers (such as the first metal layer and the second metal layer); for another example, as Figure 4 shown, if the gate metal 106 and the metal field plate structure 107 are not connected through deposited metal layers, the gate metal 106 and the metal field plate structure 107 can be connected through an interconnect metal; that is to say, the semiconductor device may further include a first interconnect metal, where the first interconnect metal is used to connect to the gate metal 106 and the metal field plate structure 107 respectively.
[0045] Similarly, if a source field plate is needed, the source metal 103 can be connected to the metal field plate structure 107.
[0046] Among them, there are also various ways to connect the source metal 103 to the metal field plate structure 107. For example, as Figure 2 and Figure 3 shown, if the gate metal 106 and the metal field plate structure 107 are already connected by a deposited metal layer during deposition, then during metal etching, the gate metal 106 and the metal field plate structure 107 can be disconnected, and then, an interconnect metal connecting the source metal 103 and the metal field plate structure 107 can be fabricated on the dielectric layer. Another example is, as Figure 4 shown, if the gate metal 106 and the metal field plate structure 107 are not connected by a deposited metal layer during deposition, then at this time, an interconnect metal connecting the source metal 103 and the metal field plate structure 107 can be directly fabricated on the dielectric layer 105. That is to say, the semiconductor device may further include a second interconnect metal, where the second interconnect metal is used to connect to the source metal 103 and the metal field plate structure 107 respectively.
[0047] Optionally, the source metal 103 of the semiconductor device can be disposed in a preset first region on the epitaxial layer. For example, referring to Figure 2 , Figure 3 and Figure 4 , specifically, a metal electrode can be prepared on the first region of the epitaxial layer 102 such that the metal electrode forms an ohmic contact with the epitaxial layer 102 to obtain the source metal 103.
[0048] Similarly, the drain metal 104 can be disposed in a preset second region on the epitaxial layer 102. For example, specifically, a metal electrode can be prepared on the second region of the epitaxial layer 102 such that the metal electrode forms an ohmic contact with the epitaxial layer 102 to obtain the drain metal 104.
[0049] Among them, an ohmic contact refers to a very small contact resistance between a metal and a semiconductor, which can be almost ignored, thereby ensuring that there is no significant voltage drop in the current at the contact surface. The process of fabricating a metal electrode in a specific region (such as the source, drain, or gate) to form an ohmic contact is called the ohmic metal process.
[0050] After the ohmic metal process is completed, specifically, a second dielectric layer 105 can be formed on the epitaxial layer 102, the source metal 103, and the drain metal 104 by depositing a dielectric. The first dielectric layer 108 is formed before fabricating the metal electrode.
[0051] Optionally, the groove structure included in the dielectric layer can be fabricated by setting photolithography windows with different widths by using the load effect of dry etching.
[0052] For example, a photolithography mask can be specifically set on the dielectric layer. Among them, the photolithography mask has photolithography windows with various widths. Then, the dielectric layer provided with the photolithography mask is dry-etched, and corresponding groove structures can be formed at the photolithography windows.
[0053] Among them, the pattern of the photolithography mask can be determined according to the needs of actual applications. For example, the pattern of the photolithography mask can be: between the source metal and the drain metal, photolithography windows with various widths are set. Among them, the width of the middle photolithography window is the largest, and the widths on both sides gradually become narrower in turn.
[0054] Optionally, the width size and arrangement of the photolithography windows can also be set according to the needs of actual applications. For example, refer to Figure 1 , the photolithography window with the largest width can also be set at a position closer to the source metal, and the widths of other photolithography windows gradually become narrower as the distance from the "photolithography window with the largest width" increases. For example, in Figure 1 , the width of the photolithography window W3 is the largest, and the widths of the photolithography windows on both sides of the photolithography window W3 gradually decrease. For example, their width sizes are: W3>W2>W1, W3>W4>W5>W6>W7, and so on.
[0055] Among them, due to the loading effect of dry etching, the depth and width of the groove structure are proportional to the width of the corresponding photolithography window. That is to say, at the position where the photolithography window is wider, the etching width is wider and the etching depth is deeper, while at the position where the photolithography window is narrower, the etching width is narrower and the etching depth is shallower. For example, specifically refer to Figure 1 From Figure 1 , it can be seen that as the width of the photolithography window gradually decreases, the width and depth of the corresponding groove structure also gradually become smaller, specifically as follows:
[0056] Since the width of the photolithography window W3 is the largest, therefore, the width of the groove structure G3 corresponding to it is the largest and the depth is the deepest. Among the other photolithography windows on the right side of W3, since the width of the photolithography window W4 is narrower than W3, therefore, the width of the groove structure G4 corresponding to the photolithography window W4 is also narrower than G3 and the depth is shallower than G3; similarly, since the width of the photolithography window W5 is narrower than W4 and the width of the photolithography window W6 is narrower than W5, therefore, the width of the groove structure G5 corresponding to the photolithography window W5 is also narrower than G4 and the depth is shallower than G4, and the width of the groove structure G6 corresponding to the photolithography window W6 is also narrower than G5 and the depth is shallower than G5; and so on. Since the width of the photolithography window W7 is the narrowest, therefore, the width of the groove structure G7 corresponding to the photolithography window W7 is the narrowest and the depth is also the shallowest. Similarly, among the other photolithography windows on the left side of W3, the width of the groove structure G1 corresponding to W1 is less than the width of the groove structure G2 corresponding to W2, and G2 is less than G3, and so on.
[0057] Optionally, a dielectric layer with a certain thickness can be reserved between the bottom of the deepest step structure and the epitaxial layer as the gate dielectric (which can be called the gate dielectric layer) for subsequent fabrication of the gate metal. The material of the gate dielectric layer is denser than that of the upper dielectric layers (the first dielectric layer and the second dielectric layer), so the wet etching rate on the gate dielectric layer can be effectively slowed down.
[0058] Through wet etching, the morphology of the groove structure can be made continuous and smooth, so as to ensure better filling effect and better modulation effect on the electric field during subsequent fabrication of the gate metal.
[0059] The so-called loading effect of dry etching here refers to the phenomenon that when the size or shape of the etching area changes, the etching rate also changes accordingly, that is, the etching rate depends on the amount of the material on the etched surface. This loading effect generally includes three types: macroloading, microloading, and aspect ratio dependent etching (ARDE). Among them, ARDE mainly appears in the etching of high aspect ratio structures, such as deep holes or deep grooves. In these structures, it is difficult for the etching material to enter the deep part, and at the same time, it is difficult for the reaction products to overflow, resulting in a decrease in the etching rate at the bottom. The loading effect will affect the accuracy of the shape and size of the structure, so it is generally suppressed as much as possible. However, in this application, this characteristic is utilized to fabricate groove structures with different widths and depths, making a phenomenon that was originally harmful become a factor beneficial to the process.
[0060] Optionally, the semiconductor device fabricated in this embodiment can be a MIS-HEMT, a P-GaN HEMT (P-type gate enhanced GaN HEMT), or a recessed gate HEMT (High Electron Mobility Transistors). The materials of the semiconductor device include but are not limited to GaN, SiC, GaAs, or GaO, which will not be elaborated here.
[0061] As can be seen from the above, since the dielectric layer of the semiconductor device with a groove structure in this embodiment includes a plurality of independent groove structures with different depths and widths, therefore, by simply setting a metal field plate structure on these groove structures with different depths, the gate metal and multiple layers of field plates can be formed at one time. That is to say, by simply adjusting the depth and number of the groove structures, the effect of any number of layers of field plates can be achieved without the need for layer-by-layer processing of the field plates. Compared with the existing solution where at least one additional photolithography and etching step is required for each additional layer of the field plate, the process cost and time can be greatly reduced, and the manufacturing efficiency can be improved. Moreover, since the multiple layers of field plates are formed at one time, the number of depositions and etching of the dielectric and metal can also be reduced, greatly reducing the possibility of etching damage, making the quality of the dielectric under the field plate higher, which is beneficial to improving the reliability of the device.
[0062] Optionally, in some embodiments of the present application, the gate metal and the metal field plate structure can be fabricated together or separately. That is, the embodiments of the present application also provide another semiconductor device with a groove structure, which includes a substrate, an epitaxial layer, a source metal, a drain metal, a gate metal, a dielectric layer, and a metal field plate structure; wherein:
[0063] The epitaxial layer is disposed on the substrate; the source metal, the drain metal, and the gate metal are disposed on the epitaxial layer; and the dielectric layer is disposed on the epitaxial layer, the source metal, the drain metal, and the gate metal. Wherein, the dielectric layer includes a plurality of independent groove structures with different depths and widths, and the metal field plate structure is disposed on the groove structures.
[0064] For example, specifically, a field plate metal can be deposited on each groove structure, so that the field plate metals deposited on the groove structures with different heights can be used as different layers of field plates. Then, photolithography and metal etching are performed on the field plate metal to obtain a multi-layer metal field plate structure.
[0065] Among them, the selection of the field plate metal can be determined according to the requirements of the actual device and process conditions. For example, metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or nickel (Ni) can be used, or their alloys or compounds can also be used, etc., which are not limited herein.
[0066] Among them, the groove structure closest to the gate metal has the deepest depth, and the groove structure farther away from the gate metal has a shallower depth. The width of the step structure closest to the gate metal is the smallest, and the width of the step structure farther away from the gate metal is larger; for example, specifically, refer to Figure 6 .
[0067] Optionally, the substrate material of the semiconductor device can be selected according to the required semiconductor material and device performance. For example, the substrate material can include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), gallium oxide (GaO), etc.
[0068] Optionally, the metal field plate structure can be disposed on both sides of the gate metal, or the metal field plate structure can also be disposed between the gate metal and the source metal.
[0069] For example, taking the case of being disposed between the gate metal and the source metal as an example, refer to Figure 6 , the semiconductor device can include a substrate 201, an epitaxial layer 202 disposed on the substrate 201, a source metal 203, a drain metal 204, and a gate metal 206 disposed on the epitaxial layer 202, and a dielectric layer (including a second dielectric layer 205 and a first dielectric layer 209) disposed on the epitaxial layer 202, the source metal 203, the drain metal 204, and the gate metal 206. Among them, the dielectric layer 205 includes a plurality of independent groove structures with different depths and widths. The groove structures are located between the gate metal 206 and the source metal 203, and the metal field plate structure 207 is disposed on the groove structures.
[0070] Optionally, whether the gate metal 206 and the metal field plate structure 207 are connected can be determined according to the requirements of actual applications.
[0071] For example, if a gate field plate is required, the gate metal 206 can be connected to the metal field plate structure 207.
[0072] Among them, there are various ways to connect the gate metal 206 and the metal field plate structure 207. For example, the gate metal 206 and the metal field plate structure 207 can be connected through an interconnect metal; that is, the semiconductor device can further include a third interconnect metal, where the third interconnect metal is used to connect to the gate metal 206 and the metal field plate structure 207 respectively.
[0073] Similarly, if a source field plate is required, the source metal 203 can be connected to the metal field plate structure 207. For example, the source metal 203 and the metal field plate structure 207 can be connected through an interconnect metal; that is, the semiconductor device can further include a fourth interconnect metal, where the fourth interconnect metal is used to connect to the source metal 203 and the metal field plate structure 207 respectively.
[0074] Optionally, the source metal 203 of the semiconductor device can be disposed in a preset first region on the epitaxial layer. For example, refer to Figure 6, specifically, the source metal 203 can be obtained by fabricating a metal electrode on the first region of the epitaxial layer 202 such that the metal electrode forms an ohmic contact with the epitaxial layer 202.
[0075] Similarly, the drain metal 204 can be disposed on a preset second region of the epitaxial layer 202. For example, specifically, the drain metal 204 can be obtained by fabricating a metal electrode on the second region of the epitaxial layer 202 such that the metal electrode forms an ohmic contact with the epitaxial layer 202.
[0076] Similarly, the gate metal 206 can be disposed on a preset third region of the epitaxial layer 202. For example, specifically, the drain metal 206 can be obtained by fabricating a metal electrode on the third region of the epitaxial layer 202 such that the metal electrode forms an ohmic contact with the epitaxial layer 202.
[0077] Similar to the previous embodiment, optionally, the groove structures included in the dielectric layer can be fabricated by utilizing the loading effect of dry etching and by setting photolithography windows with different widths. For details, please refer to the previous embodiment and will not be elaborated here.
[0078] Optionally, the semiconductor device fabricated in this embodiment can be a MIS-HEMT, a P-GaN HEMT, or a grooved gate HEMT. The materials of the semiconductor device include but are not limited to GaN, SiC, GaAs, or GaO, which will not be elaborated here.
[0079] As can be seen from the above, since the dielectric layer of the semiconductor device with groove structures in this embodiment includes multiple independent groove structures with different depths and widths, therefore, only by setting metal field plate structures on these groove structures with different depths, multiple layers of field plates can be formed at one time. That is to say, only by adjusting the depth and number of the groove structures, the effect of any number of layers of field plates can be achieved without the need for layer-by-layer processing of the field plates. Compared with the existing solution where at least one additional photolithography and etching step is required for each additional layer of the field plate, the process cost and time can be greatly reduced, and the manufacturing efficiency can be improved. Moreover, since the multiple layers of field plates are formed at one time, the number of depositions and etching of the dielectric and metal can also be reduced, greatly reducing the possibility of etching damage and making the quality of the dielectric under the field plate higher, which is beneficial to improving the reliability of the device.
[0080] The above has introduced in detail a semiconductor device with a groove structure provided by an embodiment of the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.
Claims
1. A semiconductor device having a groove structure, characterized in that: include: substrate; an epitaxial layer, disposed on the substrate; A source metal and a drain metal are disposed on the epitaxial layer; A dielectric layer is disposed on the epitaxial layer, the source metal and the drain metal; wherein the dielectric layer includes a plurality of independent groove structures with different depths and widths; The gate metal is arranged on the groove structure with the greatest depth; The metal field plate structure is arranged on the other groove structures except the groove structure with the greatest depth.
2. The semiconductor device with a groove structure according to claim 1, characterized in that: Also comprising a first metal layer and a second metal layer; The first metal layer is disposed on the groove structure with the largest depth to form a gate metal; The second metal layer is disposed on the other groove structures except the groove structure with the greatest depth to form a metal field plate structure.
3. The semiconductor device with a groove structure according to claim 1, characterized in that: The metal field plate structure is arranged on both sides of the gate metal; or, The metal field plate structure is disposed between the gate metal and the drain metal.
4. The semiconductor device with a groove structure according to any one of claims 1 to 3, characterized in that: The metal field plate structure is connected to the gate metal.
5. The semiconductor device with a groove structure according to any one of claims 1 to 3, characterized in that: The groove structure closest to the gate metal has the deepest depth, and the groove structure farther away from the gate metal has a shallower depth; The width of the step structure closest to the gate metal is the smallest, and the width of the step structure farther from the gate metal is larger.
6. The semiconductor device with a groove structure according to any one of claims 1 to 3, characterized in that: Also included is a second interconnect metal; The second interconnect metal is connected to the metal field plate and the source metal respectively.
7. The semiconductor device with a groove structure according to any one of claims 1 to 3, characterized in that: The semiconductor device is a MIS-HEMT, a P-GaN HEMT or a recessed gate HEMT, and the material of the semiconductor device includes but is not limited to GaN, SiC, GaAs or GaO.
8. A semiconductor device having a groove structure, characterized in that: include: substrate; an epitaxial layer, disposed on the substrate; A source metal, a drain metal and a gate metal are disposed on the epitaxial layer; A dielectric layer is disposed on the epitaxial layer, the source metal, the drain metal and the gate metal; wherein the dielectric layer includes a plurality of independent groove structures with different depths and widths; The metal field plate structure is arranged on the groove structure.
9. The semiconductor device with a groove structure according to claim 8, characterized in that: Also included is Fourth Interconnect Metal; The fourth interconnection metal is connected to the metal field plate and the source metal respectively.
10. The semiconductor device with a groove structure according to claim 8 or 9, characterized in that: The groove structure closest to the gate metal has the deepest depth, and the groove structure farther away from the gate metal has a shallower depth; The width of the step structure closest to the gate metal is the smallest, and the width of the step structure farther from the gate metal is larger.