Array substrate, display panel and display device

Abstract

The embodiment of the utility model provides an array substrate, a display panel and a display device, relates to the technical field of display, and aims to solve the problem of poor display under an outdoor environment condition. The array substrate comprises a plurality of sub-pixels, and at least one sub-pixel in the plurality of sub-pixels comprises a first transistor; the array substrate further comprises a substrate, a gate layer, an active layer and a shading conductive layer, the gate layer comprises a gate pattern of the first transistor, and the active layer comprises an active layer pattern of the first transistor; the shading conductive layer comprises a first pattern and a second pattern, and the orthographic projection of the active layer pattern of the first transistor on the substrate is located in the orthographic projection of the first pattern on the substrate. The distance between the orthographic projection boundary of the first pattern on the substrate and the orthographic projection boundary of the active layer pattern of the first transistor on the substrate is within a set interval range; the transmittance of the first pattern is smaller than or equal to that of the second pattern; the second pattern is connected to the gate pattern of the first transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to an array substrate, a display panel, and a display device. Background Art

[0002] Liquid Crystal Display (LCD) has the characteristics of small volume, low power consumption, lightness, thinness, and no radiation, and has been widely used in the display field. With the development of display technologies, its display quality has been continuously improved with the progress of manufacturing process technologies. Summary of the Utility Model

[0003] The purpose of the embodiments of the present disclosure is to provide an array substrate, a display panel, and a display device, which are used to improve the display defect problem under outdoor environmental conditions and enhance the display effect of the display device.

[0004] To achieve the above purpose, the embodiments of the present disclosure provide the following technical solutions:

[0005] On the one hand, an array substrate is provided. The array substrate includes a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes a first transistor; the array substrate includes a substrate, a gate layer, an active layer, and a light-shielding conductive layer. Among them, the gate layer is disposed on one side of the substrate, and the gate layer includes a gate pattern of the first transistor; the active layer is disposed on the side of the gate layer away from the substrate, and the active layer includes an active layer pattern of the first transistor; the light-shielding conductive layer is disposed on the side of the active layer away from the substrate, and the light-shielding conductive layer includes a light-shielding conductive pattern, the light-shielding conductive pattern includes a first pattern and a second pattern, the orthographic projection of the active layer pattern of the first transistor on the substrate is located within the orthographic projection of the first pattern on the substrate, and the distance between the boundary of the orthographic projection of the first pattern on the substrate and the boundary of the orthographic projection of the active layer pattern of the first transistor on the substrate is within a set pitch range; the transmittance of the first pattern is less than or equal to the transmittance of the second pattern; the second pattern is connected to the gate pattern of the first transistor.

[0006] By providing a light-shielding conductive pattern, performing a dual-gate design and a light-shielding design on the first transistor, it is possible to prevent the active pattern of the first transistor from reacting under the action of light, while increasing the on-state current of the first transistor, reducing the leakage current, improving the threshold voltage shift of the first transistor, and alleviating the specific degradation of the first transistor, thereby increasing the operating voltage range of the gate-off voltage.

[0007] In some embodiments, the light-shielding conductive layer includes a first sub-layer, and the first pattern and the second pattern are located on the first sub-layer; the material of the second pattern is a transparent conductive oxide, and the material of the first pattern is a blackened transparent conductive oxide; the blackened transparent conductive oxide is obtained by blackening the transparent conductive oxide. Among them, the process conditions for weakening the light transmittance are that the source power range is 5 kW to 7 kW, the hydrogen flow rate is 70,000 to 80,000 sccm, the working pressure range is 900 to 1200 mt, and the processing time range is 10 to 20 S.

[0008] In some embodiments, the light-shielding conductive layer includes a first sub-layer, and the first pattern and the second pattern are located on the first sub-layer; the materials of the first pattern and the second pattern are metals, and the transmittance of the first pattern is equal to the transmittance of the second pattern.

[0009] In some embodiments, the light-shielding conductive layer includes a first sub-layer, and the first pattern and the second pattern are located on the first sub-layer; the material of the second pattern is a transparent conductive oxide, and the material of the first pattern is a metal or an organic light-shielding material.

[0010] In some embodiments, the light-shielding conductive layer includes a first sub-layer and a second sub-layer, and the second sub-layer is located on the side of the first sub-layer away from the substrate; the transmittance of the second sub-layer is less than the transmittance of the first sub-layer; the first pattern includes a first sub-pattern located on the first sub-layer and a second sub-pattern located on the second sub-layer, and the second pattern is located on the first sub-layer.

[0011] In some embodiments, the material of the first sub-layer is a transparent conductive oxide, and the material of the second sub-layer is a metal or an organic light-shielding material.

[0012] In some embodiments, the set spacing range is 1 μm to 2.5 μm.

[0013] In some embodiments, the sub-pixel further includes a pixel electrode and a common electrode; the light-shielding conductive layer includes a first sub-layer, and the first sub-layer further includes a pixel electrode pattern; the gate layer further includes a common electrode pattern and a common signal line, the material of the common electrode pattern is a transparent conductive material, and the common signal line is connected to the common electrode pattern; the pixel electrode pattern overlaps with the common signal line.

[0014] In some embodiments, the gate layer includes a gate line, and the gate pattern of the first transistor is the part of the gate line that overlaps with the active layer pattern of the first transistor; the second pattern is connected to the gate line.

[0015] In some embodiments, the array substrate includes a gate driving circuit, and the gate driving circuit includes at least one second transistor and a storage capacitor; the gate layer further includes a gate control line, and the gate control line includes a gate pattern of the second transistor; the active layer further includes an active layer pattern of the second transistor; the array substrate further includes a source-drain metal layer disposed on a side of the active layer away from the substrate, the source-drain metal layer is in contact with the active layer, and the source-drain metal layer includes a first plate pattern of the storage capacitor; the light-shielding conductive layer further includes a conductive pattern, the conductive pattern overlaps with the active layer pattern of the second transistor and also overlaps with the first plate pattern of the storage capacitor; the conductive pattern is connected to the gate control line; the gate control line overlaps with the first plate pattern of the storage capacitor.

[0016] In some embodiments, the distance between the first plate pattern of the storage capacitor and the conductive pattern is equal to the distance between the first plate pattern of the storage capacitor and the gate control line.

[0017] On the other hand, a display panel is provided, including the array substrate according to any one of the above embodiments in one aspect.

[0018] The above display panel has the same structure and beneficial technical effects as the array substrate provided in the above some embodiments, and will not be described in detail herein.

[0019] In some embodiments, the display panel further includes: a color filter substrate disposed on the array substrate and at least one spacer disposed between the array substrate and the color filter substrate; the spacer includes a first spacer, and the first spacer is disposed on one side of the second pattern and is in contact with the second pattern.

[0020] In some embodiments, the spacer includes a second spacer, and the height of the first spacer is higher than the height of the second spacer; the second spacer is disposed on one side of the second pattern.

[0021] In yet another aspect, a display device is provided, including: the display panel according to any one of the above embodiments in the above another aspect, and a backlight module; the display panel includes a display side and a non-display side, the backlight module is disposed on the non-display side of the display panel, and the backlight module is configured to provide a backlight source.

[0022] The above display device has the same structure and beneficial technical effects as the display panel provided in the above some embodiments, and will not be described in detail herein. Description of the Drawings

[0023] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings required for some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, the actual timings of the signals, etc.

[0024] Figure 1 It is a plan view structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0025] Figure 2A It is a structure diagram of a sub-pixel provided according to some embodiments of the present disclosure;

[0026] Figure 2B It is a stacked structure diagram of a light-shielding conductive layer and an active layer in a sub-pixel provided according to some embodiments of the present disclosure;

[0027] Figure 3A It is a cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0028] Figure 3B It is a cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0029] Figure 3C It is a characteristic curve diagram of indium tin oxide transmittance and hydrogen flow rate provided according to some embodiments of the present disclosure;

[0030] Figure 3D It is a structure diagram of an electron microscope test of an array substrate provided according to some embodiments of the present disclosure;

[0031] Figure 3E It is a flowchart of the formation steps of a first pattern and a second pattern provided according to some embodiments of the present disclosure;

[0032] Figure 4A It is a cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0033] Figure 4B It is a cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0034] Figure 5A It is a cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0035] Figure 5B It is a cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0036] Figure 6A A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0037] Figure 6B A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0038] Figure 7A A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0039] Figure 7B A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0040] Figure 8A A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0041] Figure 8B A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0042] Figure 9A A plan view structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0043] Figure 9B A cross-sectional structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0044] Figure 9C A circuit structure diagram of an array substrate provided according to some embodiments of the present disclosure;

[0045] Figure 10A A band structure diagram of a double-gate transistor in a non-powered state provided according to some embodiments of the present disclosure;

[0046] Figure 10B A band structure diagram of a double-gate transistor in an on state provided according to some embodiments of the present disclosure;

[0047] Figure 10C A band structure diagram of a bottom-gate transistor in an on state provided according to some embodiments of the present disclosure;

[0048] Figure 10D A band structure diagram of a double-gate transistor in an off state provided according to some embodiments of the present disclosure;

[0049] Figure 10E A band structure diagram of a bottom-gate transistor in an off state provided according to some embodiments of the present disclosure;

[0050] Figure 11AA plan view structure diagram of a display panel provided according to some embodiments of the present disclosure;

[0051] Figure 11B A cross-sectional structure diagram of a display panel provided according to some embodiments of the present disclosure;

[0052] Figure 12A A plan view structure diagram of a display panel provided according to some embodiments of the present disclosure;

[0053] Figure 12B A cross-sectional structure diagram of a display panel provided according to some embodiments of the present disclosure;

[0054] Figure 13A A structure diagram of a spacer being deflected under an external force provided according to some embodiments in the prior art;

[0055] Figure 13B A structure diagram of a spacer being deflected under an external force provided according to some embodiments of the present disclosure;

[0056] Figure 14 A cross-sectional structure diagram of a display panel provided according to some embodiments of the present disclosure;

[0057] Figure 15 A plan view structure diagram of a display device provided according to some embodiments of the present disclosure;

[0058] Figure 16 A structure diagram of a display device provided according to some embodiments of the present disclosure. Detailed implementation manners

[0059] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0060] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third-person singular form "comprises" and the present participle form "comprising" are interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example", or "some examples", etc. are intended to indicate that the specific features, structures, materials, or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0061] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0062] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" may be a fixed connection, a detachable connection, or integrated; it may be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0063] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0064] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0065] As used herein, and depending on context, the term "if" is optionally construed to mean "when" or "upon" or "in response to determining" or "in response to detecting". Similarly, depending on context, the phrase "if it is determined that..." or "if [stated condition or event] is detected" is optionally construed to mean "when it is determined that..." or "in response to determining that..." or "when [stated condition or event] is detected" or "in response to detecting [stated condition or event]".

[0066] As used herein, the use of "is adapted to" or "is configured to" means open and inclusive language, which does not exclude devices that are adapted to or configured to perform additional tasks or steps.

[0067] Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0068] As used herein, "about", "substantially", or "approximately" includes the stated value and an average within an acceptable deviation range of the particular value, where the acceptable deviation range is determined as would be understood by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0069] As used herein, "parallel", "perpendicular", "equal" include the stated situation and situations similar to the stated situation, where the range of the similar situations is within an acceptable deviation range, and the acceptable deviation range is determined as would be understood by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, where the acceptable deviation range for approximate parallelism can be, for example, within 5° deviation; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, where the acceptable deviation range for approximate perpendicularity can also be, for example, within 5° deviation. "Equal" includes absolute equality and approximate equality, where the acceptable deviation range for approximate equality can be, for example, the difference between the two equal values is less than or equal to 5% of either one.

[0070] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can be that the layer or element is directly on the other layer or substrate, or there can also be an intermediate layer between the layer or element and the other layer or substrate.

[0071] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include shape deviations caused by, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0072] The display device includes a plurality of sub-pixels, a plurality of gate lines, and a gate driving circuit. The gate driving circuit is connected to the plurality of gate lines, and the gate driving circuit outputs gate signals to the plurality of gate lines. The plurality of gate lines are connected to the plurality of sub-pixels, and the gate lines transmit the gate signals to control the sub-pixels connected thereto to turn on or off. When the sub-pixels are turned on, data signals are written, and the sub-pixels emit light, thereby enabling the display device to achieve display. The gate signals output by the gate driving circuit have a gate-on voltage VGH and a gate-off voltage VGL. When the voltage values of the gate-on voltage VGH and the gate-off voltage VGL satisfy the operating voltage range, the sub-pixels can be normally turned on or off under the control of the gate signals, and the display device can display normally. If the voltage values of the gate-on voltage VGH and the gate-off voltage VGL do not satisfy the operating voltage range, the sub-pixels cannot be normally turned on or off under the control of the gate signals, thereby affecting the normal display of the display device and possibly resulting in display defects.

[0073] As display devices are increasingly widely used outdoors, including in applications such as electronic signage, monitors, and multimedia displays, there are common usage requirements such as wide temperature range, high brightness, and continuous operation. Currently, after long-term outdoor use, existing display devices frequently exhibit problems such as flash screen defects and crosstalk problems that are visible to the human eye, such as blackening, whitening, and crosstalk in some regions under dark conditions. The reason is that in a more severe outdoor usage environment, such as high and low temperatures, higher backlight brightness, and continuous lighting, the deterioration rate of the characteristics of the display device itself accelerates, thereby causing a change in the operating voltage range of the gate-on voltage VGH and the gate-off voltage VGL, and the voltage values of the gate-on voltage VGH and the gate-off voltage VGL cannot satisfy the operating voltage range under outdoor conditions.

[0074] In view of the above-mentioned frequent problem of splash screen defects, the inventors of the present application conducted research and tests through means such as external voltage injection, oscilloscope testing of gate drive signals, transistor characteristics and stress testing, and SEM (Scanning Electron Microscope) analysis. Finally, it was determined that the positive shift of the threshold voltage of the transistors responsible for output and cascading in the gate drive circuit led to a low output current of the transistors, resulting in a decrease in the gate turn-on voltage VGH of the gate signal output by the gate drive circuit, which could not meet the requirement for normal opening of sub-pixels in the display area. To solve this problem, it is necessary to adjust the process parameters related to transistor characteristics so that the gate turn-on voltage VGH meets the voltage requirement for controlling the normal opening of sub-pixels in the display area.

[0075] On the other hand, in view of the above-mentioned problem of crosstalk that causes blackening, whitening, and being visible to the human eye in some areas under dark conditions, the inventors of the present application conducted research and tests through means such as external voltage injection, transistor characteristics and stress testing, and SEM (Scanning Electron Microscope) analysis. Finally, it was determined that the negative shift of the threshold voltage of the transistors in the sub-pixels led to an increase in leakage current and an increase in the data line voltage fed into the pixel electrode, resulting in the gate turn-off voltage VGL within the original operating voltage range being unable to meet the requirement for turning off the transistors in the sub-pixels in the display area. To solve this problem, it is necessary to adjust the process parameters related to transistor characteristics so that the gate turn-off voltage VGL meets the voltage requirement for controlling the normal turn-off of sub-pixels.

[0076] In summary, it is necessary to optimize the characteristic parameters of the transistors in the display device so that the voltage ranges of the gate turn-on voltage and the gate turn-off voltage can meet the above-mentioned more stringent outdoor use conditions.

[0077] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel, and a display device. By adjusting the structure of some film layers in the array substrate, reasonably setting the light-shielding positions, and simultaneously setting the double-gate structure of the transistors, the problem of defective display generated in a complex environment can be avoided, and at the same time, the operating voltage range of the gate signal voltage can be increased, improving the reliability of the display device.

[0078] The array substrate, display panel, and display device provided by the present disclosure are introduced below.

[0079] Such as Figure 2A 、 Figure 2B and Figure 3AAs shown in the figure, the present disclosure provides various embodiments of an array substrate. To clearly describe the film layer structure of the array substrate, the following first lists each film layer included in the array substrate. The array substrate 10 includes a substrate 101, and a gate layer 102, a first insulating layer 103, an active layer 104, a source-drain metal layer 105, a second insulating layer 106, and a light-shielding conductive layer 107 that are sequentially stacked on the substrate 101.

[0080] Exemplarily, the substrate 101 may be a flexible substrate 101, such as a polyethylene terephthalate (PET) film, a PI (polyimide) film, etc.; or it may be a rigid substrate 101, such as a glass substrate 101.

[0081] Exemplarily, the first insulating layer may be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and may be a single-layer, double-layer or multi-layer structure to achieve the effects of blocking water and oxygen and blocking alkaline ions.

[0082] Exemplarily, the material of the active layer 104 includes any one of low-temperature polysilicon, indium gallium zinc oxide, or low-temperature polycrystalline oxide.

[0083] The array substrates mentioned in the following embodiments all conform to the above film layer arrangement. The following specifically introduces each film layer structure.

[0084] In some embodiments, as Figure 1 shown, the array substrate 10 includes a plurality of sub-pixels PX, and at least one of the plurality of sub-pixels PX includes a first transistor T1.

[0085] Exemplarily, as Figure 1 shown, the array substrate 10 includes a display area AA, wherein a plurality of sub-pixels are provided in the display area AA. As Figure 1 shown, the plurality of sub-pixels PX are arranged in multiple rows and multiple columns in an array, and each sub-pixel PX includes a first transistor T1. The display area AA further includes a plurality of gate lines GT and a plurality of common signal lines COM arranged along the row direction X, and a plurality of data signal lines DT arranged along the column direction. Each sub-pixel PX is electrically connected to one gate line GT, one common signal line COM, and one data signal line DT. Referring to Figure 2A Figure 2A is a structural diagram of a sub-pixel. According to Figure 2A it can be obtained that the sub-pixel PX is correspondingly connected to the gate line GT, the common signal line COM, and the data signal line DT respectively, wherein the gate line GT, the common signal line COM, and the data signal line DT respectively provide a gate signal, a common electrode signal, and a data signal for the sub-pixel PX. ​

[0086] Continue to refer to Figure 1 , each sub-pixel PX includes a liquid crystal capacitor Clc and a storage capacitor Cst. Among them, since the liquid crystal is a capacitive material, its equivalent capacitance is the liquid crystal capacitor Clc, and the size of the liquid crystal capacitor Clc can be 0.1 pF. However, during the operation of each sub-pixel PX, parasitic capacitances will inevitably be generated. For example, the existence of Cpg, Cpd, Cgd, Cgs, etc. will cause certain interference to the transmission of voltage signals, affecting the display. And the liquid crystal capacitor Clc cannot well hold the voltage signal it transmits. Therefore, it is necessary to work with the storage capacitor Cst to better hold the transmitted voltage signal, thereby ensuring the continuous display of the picture.

[0087] Refer to Figures 3A to 8B And in combination with Figure 2B , among which, Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A are cross-sectional structure diagrams obtained by making a cross-section along the cross-section line CC' in Figure 2A in different schemes. Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B are cross-sectional structure diagrams obtained by making a cross-section along the cross-section line DD' in Figure 2A in different schemes. The array substrate 10 includes a substrate 101, a gate layer 102, an active layer 104, and a light-shielding conductive layer 107. Among them, the gate layer 102 is disposed on one side of the substrate 101, the active layer 104 is disposed on the side of the gate layer 102 away from the substrate 101, and the light-shielding conductive layer 107 is disposed on the side of the active layer 104 away from the substrate 101; the gate layer 102 includes a gate pattern 1021 of the first transistor T1, the active layer 104 includes an active layer pattern 1041 of the first transistor T1, the light-shielding conductive layer 107 includes a light-shielding conductive pattern 1071, the light-shielding conductive pattern 1071 includes a first pattern 1071a and a second pattern 1071b, the orthographic projection of the active layer pattern 1041 of the first transistor T1 on the substrate 101 is located within the orthographic projection of the first pattern 1071a on the substrate 101, and the distance between the boundary of the orthographic projection of the first pattern 1071a on the substrate 101 and the boundary of the orthographic projection of the active layer pattern 1041 of the first transistor T1 on the substrate 101 is within the set spacing S range; the transmittance of the first pattern 1071a is less than or equal to the transmittance of the second pattern 1071b; the second pattern 1071b is connected to the gate pattern 1021 of the first transistor T1.

[0088] Exemplarily, the first pattern 1071a has a light blocking function.

[0089] It should be noted that the transmittance of the first pattern 1071a is set to be less than or equal to the transmittance of the second pattern 1071b, that is, the first pattern 1071a and the second pattern 1071b can be prepared by patterning of the same material, and, for the area of ​​the first pattern 1071a, the first pattern 1071a can be obtained by a transmittance reduction treatment, so that the transmittance of the first pattern 1071a is less than the transmittance of the second pattern 1071b; or, the first pattern 1071a and the second pattern 1071b can be prepared by patterning of the same material, and without performing other process treatments, the transmittance of the first pattern 1071a is equal to the transmittance of the second pattern 1071b; or, the first pattern 1071a and the second pattern 1071b can be prepared by patterning of different materials, so that the transmittance of the first pattern 1071a is less than the transmittance of the second pattern 1071b.

[0090] In some embodiments, reference Figure 3A , Figure 3B , Figure 4A and Figure 4B , the light shielding conductive layer 107 includes a first sub-layer 107a, and the first pattern 1071a and the second pattern 1071b are located in the first sub-layer 107a. Figure 3A , Figure 3B , Figure 4A and Figure 4B The light-shielding conductive layer 107 includes a film layer, and the first pattern 1071a and the second pattern 1071b are located in the same layer, that is, the first pattern 1071a and the second pattern 1071b can be made of the same material and prepared by patterning.

[0091] In some embodiments, reference Figure 3A and Figure 3B , the material of the second pattern is a transparent conductive oxide, and the material of the first pattern is a blackened transparent conductive oxide; the transmittance of the first pattern 1071a is less than the transmittance of the second pattern 1071b.

[0092] In some embodiments, the material of the first pattern 1071a is a blackened transparent conductive oxide; the blackened transparent conductive oxide is a transparent conductive oxide obtained by a blackening treatment, wherein the process conditions for reducing light transmittance are a source power range of 5kW to 7kW, a hydrogen flow rate of 70,000 to 80,000 sccm, an operating pressure range of 900 to 1200 mt, and a processing time range of 10 to 20S.

[0093] It should be noted that during the process of preparing the first pattern 1071a under the above process conditions, the blackening treatment has a good effect, and the first pattern 1071a that meets the transmittance requirements of this application can be prepared according to the need of the degree of weakening of light transmittance. Exemplarily, referring to Figure 3C and Figure 3D , Figure 3C shown is the characteristic curve of the transmittance of indium tin oxide (ITO), a transparent conductive oxide, versus the hydrogen flow rate. It can be obtained from the figure that when the hydrogen flow rate is below 70000 sccm, the transmittance of indium tin oxide will increase. That is to say, during the blackening treatment process, the blackening effect will deteriorate sharply. At the same time, combining Figure 3D , Figure 3D which is the electron microscopy test diagram of the hydrogen flow rate exceeding 80000 sccm. As shown in Figure 3D , Figure 3D the film layers stacked from bottom to top in Figure 3D are successively the substrate 101, the gate layer 102, the first insulating layer 103, the second insulating layer 106, and the light-shielding conductive layer 107. Exemplarily, the material of the gate layer 102 is, for example, indium tin oxide. As shown in the circled position in the figure, indium or indium oxide (In / InOx) particles will precipitate on the surface of the gate layer 102 at this time. Continuing to refer to Figure 3D , exemplarily, silicon nitride is provided on the substrate 101. The precipitated indium or indium oxide (In / InOx) particles will corrode the silicon nitride, thereby exposing the substrate 101. Therefore, controlling the process conditions within the above range can include better light transmittance weakening treatment (blackening treatment) effect and will not damage other film layers.

[0094] Exemplarily, the material of the transparent conductive oxide can be but is not limited to ITO (Indium Tin Oxide), FTO (SnO2:F; fluorine-doped tin oxide), ATO (Sn2O:Sb; antimony-doped tin oxide), etc.

[0095] Taking the transparent conductive oxide as an example, the formation steps S1 to S7 of the first pattern 1071a and the second pattern 1071b are introduced as follows. As shown in Figure 3E , specifically:

[0096] S1. First, an initial first sub-layer 107a' of the light-shielding conductive layer 107 is formed on the second insulating layer 106.

[0097] Exemplarily, forming the initial first sub-layer 107a' can be depositing a transparent conductive oxide material on the second insulating layer 106.

[0098] It should be noted that the above initial first sub-layer 107a' is a whole layer of film laid on the second insulating layer 106, and the initial first sub-layer 107a' has not undergone a patterning process.

[0099] S2. Form a photoresist layer on the initial first sub-layer 107a'.

[0100] S3. Use a mask to expose and develop the photoresist layer to obtain a patterned photoresist layer.

[0101] It should be noted that the mask includes a plurality of openings, as well as halftone regions and full-tone regions. The portions of the photoresist layer corresponding to the plurality of openings are removed, and part of the initial first sub-layer 107a' is exposed. The portions corresponding to the halftone regions and full-tone regions are retained to form a patterned photoresist layer. Among them, the thickness of the portion of the patterned photoresist layer corresponding to the halftone region is less than the thickness of the portion corresponding to the full-tone region, and the portion of the patterned photoresist layer corresponding to the halftone region and the portion corresponding to the full-tone region are adjacent to each other.

[0102] The portion of the patterned photoresist layer corresponding to the halftone region covers the active layer of the first transistor and the region within a set spacing range around the active layer of the first transistor.

[0103] S4. Etch the initial first sub-layer 107a' exposed after development of the photoresist layer to form an initial light-shielding conductive pattern 1071'.

[0104] S5. Thin the patterned photoresist layer until the portion of the patterned photoresist layer corresponding to the halftone region is removed, exposing the first part (corresponding to the first pattern) of the initial light-shielding conductive pattern 1071'.

[0105] Exemplarily, wet etching, dry etching or laser etching processes can be used to thin the photoresist layer. In this example, the dry etching process is adopted, which can also be called the ashing process of the photoresist. It is processed in an ECCP (Enhance Cathode Coupling Plasma) dry etching equipment, using NF3 and O2 as working gases. The process conditions are: source power / bias power is 12kW / 10kW, the flow rate of NF3 / O2 is 1500 / 10000sccm, and the working pressure is 40mt.

[0106] It should be noted that since the thickness of the portion of the patterned photoresist layer corresponding to the halftone region is less than the thickness of the portion corresponding to the full-tone region, when the photoresist layer is thinned until the first part of the initial light-shielding conductive pattern 1071' is exposed, there is still photoresist on the second part (corresponding to the second pattern) of the initial light-shielding conductive pattern 1071' to protect the second part of the initial light-shielding conductive pattern during the subsequent light transmittance weakening process, preventing the light transmittance of the second part of the initial light-shielding conductive pattern 1071' from being reduced.

[0107] S6. Perform a light transmittance reduction process on the first part of the initial light-shielding conductive pattern 1071' to form the first pattern 1071a from the first part of the initial light-shielding conductive pattern 1071' and form the second pattern from the second part of the initial light-shielding conductive pattern 1071'.

[0108] Exemplarily, performing a light transmittance reduction process on the first part of the initial light-shielding conductive pattern 1071' can also be referred to as performing a blackening process on the first part of the initial light-shielding conductive pattern 1071'. Since the material of the initial first sub-layer 107a' is a transparent conductive oxide, generally, by performing hydrogen reduction on the transparent conductive oxide, an opaque (black) transparent conductive oxide is generated, and the generation amount of the transparent conductive oxide can be controlled by controlling reaction conditions such as reaction time, temperature, and hydrogen dosage to achieve a reduction in light transmittance, even to the extent of completely blocking light passage. For example, the light transmittance reduction process can be performed in a plasma-enhanced chemical vapor deposition device with H2 as the working gas. The process conditions are that the source power ranges from 5 kW to 7 kW, the hydrogen flow rate is from 70000 to 80000 sccm, the working pressure ranges from 900 to 1200 mt, and the processing time ranges from 10 to 20 S. Exemplarily, the source power is 6 kW, the flow rate of H2 is 80000 sccm, the working pressure is 1000 mt, and the processing time is 15 S. Of course, according to the need for the degree of light transmittance reduction, other processing times can also be used.

[0109] Exemplarily, the first part of the initial light-shielding conductive pattern 1071' can also be subjected to a light transmittance reduction process by laser. By irradiating the transparent conductive oxide in the first part of the initial light-shielding conductive pattern 1071' with a laser, hydrogen will be released from the underlying silicon nitride-based second insulating layer to reduce the transparent conductive oxide. The surface treatment of only the transparent conductive oxide can be achieved by adjusting the laser power without damaging other functional film layers beneath it.

[0110] It can be understood that the transmittance of the first pattern 1071a after the light transmittance reduction process is less than that of the second pattern 1071b, that is, the first pattern 1071a has a light-blocking effect relative to the second pattern 1071b.

[0111] S7. Strip the remaining photoresist.

[0112] Exemplarily, the distance between the orthographic projection boundary of the first pattern 1071a on the substrate 101 and the orthographic projection boundary of the active layer pattern 1041 of the first transistor T1 on the substrate 101 is within the set pitch S. That is to say, the orthographic projection of the first pattern 1071a on the substrate 101 can completely cover the orthographic projection of the active layer pattern 1041 on the substrate 101. That is, most of the light rays emitted from the side of the first pattern 1071a away from the active layer pattern 1041 towards the active layer pattern 1041 can be blocked. While improving the light-shielding effect, it can avoid the influence of light on the characteristics of the first transistor T1.

[0113] Exemplarily, it is set that the orthographic projection of the active layer pattern 1041 of the first transistor T1 on the substrate 101 is located within the orthographic projection of the first pattern 1071a on the substrate 101. That is, the active layer pattern 1041 of the first transistor T1 can be completely blocked by the first pattern 1071a. The first pattern 1071a can provide a light-blocking protection effect for the active layer pattern 1041 of the first transistor T1. That is, the first pattern 1071a can block or reduce the light rays emitted from the side of the first pattern 1071a away from the active layer pattern 1041 of the first transistor T1 towards the active layer pattern 1041 of the first transistor T1. Furthermore, the active layer pattern 1041 of the first transistor T1 does not generate a photoelectric effect, avoiding the accelerated degradation of the characteristics of the first transistor T1, and solving the problem that the photoelectric effect occurs in the active layer pattern 1041 of the first transistor T1 due to light entering the active layer pattern 1041 of the first transistor T1, resulting in a rapid increase in the carrier concentration in the active layer pattern 1041 and prone to off-state leakage phenomenon.

[0114] Exemplarily, it is set that the second pattern 1071b is connected to the gate pattern 1021 of the first transistor T1. And according to the above part, the first pattern 1071a is connected to the second pattern 1071b. That is to say, the part of the first pattern 1071a that overlaps with the active layer pattern 1041 of the first transistor T1 constitutes the top gate of the first transistor T1, and the gate pattern 1021 is the bottom gate of the first transistor T1. That is, the second pattern 1071b and the gate pattern 1021 constitute the double-gate structure of the first transistor T1. With this setting, on the one hand, it can increase the carrier mobility of the organic field-effect first transistor, making the first transistor have a higher current density. That is, the current can be increased, improving the performance of the device; on the other hand, the second pattern 1071b and the gate pattern 1021 jointly control the channel region of the active layer pattern 1041, which can effectively suppress the penetration of the drain-end power line into the channel region, greatly reducing the threshold voltage drift and reducing the short-channel effect, which is beneficial to realizing the reduction of off-state leakage and improving the abnormal signal defect, thereby improving the overall signal output ability of the array substrate 10.

[0115] It should be noted that according to the above description, connecting the second pattern 1071b to the gate pattern 1021 of the first transistor T1, and the orthographic projection of the active layer pattern 1041 of the first transistor T1 on the substrate 101 being located within the orthographic projection of the first pattern 1071a on the substrate 101 can reduce the characteristic degradation of the first transistor T1. After analysis by the inventors of this application, in a harsh outdoor usage environment, such as high temperature, high brightness and other environmental conditions, the characteristics of the first transistor T1 will deteriorate. Exemplarily, the threshold voltage of the first transistor T1 will decrease, and the gate-off voltage VGL has the effect of pulling down the gate voltage of the first transistor T1. Since the threshold voltage of the first transistor T1 decreases and it is in a negative voltage state for a long time, it will cause the phenomenon that the first transistor cannot be turned off. That is to say, due to the characteristic degradation of the first transistor T1, the gate-off voltage VGL within the original operating voltage range cannot ensure the normal turn-off of the first transistor T1, and the operating voltage range of the gate-off voltage VGL needs to be increased.

[0116] The above-mentioned operating voltage range means that within a certain range of the gate-off voltage VGL, it can ensure the normal turn-off of the first transistor T1. Exemplarily, when the first transistor T1 is a bottom-gate transistor, the gate-off voltage VGL can work normally at -5V to -10V, that is, the operating voltage range of the gate-off voltage VGL can be adjusted within 5V to meet the requirement of the normal turn-off of the first transistor T1. And when the first transistor T1 is a double-gate transistor, according to the above content, it can reduce the off-state leakage current, that is to say, the current loss is reduced. At the same time, the required gate-off voltage VGL does not need to be reduced too much to turn off the first transistor T1. For example, the gate-off voltage VGL of -2V can meet the requirement of the normal turn-off of the first transistor T1. At this time, the gate-off voltage VGL can work normally at -2V to -10V, that is, the operating voltage range of the gate-off voltage VGL can be adjusted within 8V to meet the requirement of the normal turn-off of the first transistor T1. Therefore, the adjustment of the operating voltage range of the above-mentioned gate-off voltage VGL has been improved to a certain extent when the first transistor T1 is a double-gate transistor compared with when the first transistor T1 is a bottom-gate transistor.

[0117] In some embodiments, for example, for display products used outdoors, the requirement for the gate-off voltage VGL is higher, and the gate-off voltage VGL needs to be controlled within a certain range. Therefore, in order to achieve precise control of the gate-off voltage VGL, the inventor determines the operating voltage range of the gate-off voltage VGL through a long-term reliability evaluation method. For example, by increasing the gate-off voltage when the first transistor T1 is turned off and observing, recording the critical voltage value of the gate-off voltage at which the display device starts to show abnormal display, and then comparing the difference with the set gate-off voltage value. The larger the difference, the larger the operating voltage range of the gate-off voltage, that is, the adjustment of the operating voltage range has been improved to a certain extent. Specifically, within the first time t1, the characteristic degradation of the first transistor T1 is accelerated. For example, factors such as light and temperature are changed. At the second time t2, the gate-off voltage VGL is increased and observed, and the gate-off voltage VGL when the display device starts to show abnormalities is recorded, and the difference is compared with the set gate-off voltage VGL. The larger the difference, the larger the operating voltage range of the gate-off voltage, and the adjustment of the operating voltage range has been improved to a certain extent. The long-term reliability evaluation method can obtain that the better the characteristics (operating voltage range) of the transistor, the better the performance of the gate-off voltage by changing the characteristics of the transistor and observing the change of the gate-off voltage under corresponding conditions. That is, within a certain range of the characteristic parameters of the transistor, the change range of the gate-off voltage can better meet the outdoor conditions. This evaluation method shows that in a more severe usage environment such as outdoors, when the voltage value of the gate-off voltage VGL is within the adjusted operating voltage range, the normal operation of outdoor products can still be ensured.

[0118] From the above analysis, it can be seen that by setting the light-shielding conductive pattern 1071, performing a dual-gate design on the first transistor, and a light-shielding design, it is possible to prevent the active pattern of the first transistor from reacting under the action of light, while increasing the on-state current of the first transistor, reducing the leakage current, improving the threshold voltage shift of the first transistor T1, and reducing the specific degradation of the first transistor T1, thereby increasing the operating voltage range of the gate-off voltage VGL.

[0119] In some embodiments, such as Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B and Figure 8B as shown, the set spacing S ranges from 1 μm to 2.5 μm.

[0120] It should be noted that the above maximum set spacing is set to 2.5 μm considering the comprehensive aperture ratio and the improvement effect of the gate-off voltage VGL. To increase the aperture ratio, the set spacing range is set smaller. That is to say, when the set spacing is greater than 2.5 μm, the gate-off voltage VGL will also be increased. The above set spacing range S can be 1 μm, 1.5 μm, 2 μm, 2.5 μm, etc.

[0121] As shown in Table 1 below, it is the experimental result of the voltage value of the gate-off voltage VGL improvement corresponding to different values of the set spacing S.

[0122] Table 1

[0123] Value of S 0.8 μm 1.0 μm 1.5 μm 2.0 μm 2.5 μm VGL improvement value 1V 1.4V 1.45V 1.5V 1.45V

[0124] The above experiment can obtain that the set spacing D range is 1 μm to 2.5 μm, which can increase the voltage value of the gate-off voltage VGL by more than 1.5 V. At the same time, the backlight brightness that the display device can withstand is increased by more than 50%.

[0125] In some other embodiments, referring to Figure 4A and Figure 4B , the light-shielding conductive layer 107 includes a first sub-layer 107a, and the first pattern 1071a and the second pattern 1071b are located on the first sub-layer 107a; the materials of the first pattern 1071a and the second pattern 1071b are metals, and the transmittance of the first pattern 1071a is equal to the transmittance of the second pattern 1071b.

[0126] Exemplarily, the metal can be made of one of metals such as silver, copper, aluminum, molybdenum and their alloys. Therefore, the above first pattern 1071a and second pattern 1071b can be obtained by depositing a metal material on the second insulating layer and then through patterning. Since the materials of the first pattern 1071a and the second pattern 1071b are the same and the process steps are also the same, based on this, the transmittance of the obtained first pattern 1071a is equal to the transmittance of the second pattern 1071b.

[0127] In still some other embodiments, referring to Figure 5A , Figure 5B , Figure 6A and Figure 6B , the light-shielding conductive layer 107 includes a first sub-layer 107a, and the first pattern 1071a and the second pattern 1071b are located on the first sub-layer 107a; the material of the second pattern 1071b is a transparent conductive oxide, and the material of the first pattern 1071a is a metal or an organic light-shielding material.

[0128] Exemplarily, Figure 5A , Figure 5B the material of the first pattern 1071a in Figure 6A is a metal,Figure 6B The material of the first pattern 1071a in

[0129] Exemplarily, the organic light-shielding material includes, but is not limited to, one or more of BM (Black matrix) material, RGB Resin material, or BPS (4,4'-dihydroxydiphenyl sulfone) material. Among them, the material of BM can be Cr (chromium), CrOx (chromium oxide), or Black Resin, etc.

[0130] It should be noted that the processes for forming the first pattern 1071a and the second pattern 1071b can refer to the process descriptions in the previous two embodiments, and will not be elaborated here one by one.

[0131] In some embodiments, referring to Figure 7A , Figure 7B , Figure 8A and Figure 8B , the light-shielding conductive layer 107 includes a first sub-layer 107a and a second sub-layer 107b, and the second sub-layer 107b is located on the side of the first sub-layer 107a away from the substrate 101; the transmittance of the second sub-layer 107b is less than that of the first sub-layer 107a; the first pattern 1071a includes a first sub-pattern 10711 located in the first sub-layer 107a and a second sub-pattern 10712 located in the second sub-layer 107b, and the second pattern 1071b is located in the first sub-layer 107a.

[0132] Exemplarily, referring to Figure 7A , Figure 7B , Figure 8A and Figure 8B , the light-shielding conductive layer 107 includes two stacked film layers, and the transmittances of the two film layers are inconsistent. The first pattern 1071a includes a first sub-pattern 10711 and a second sub-pattern 10712. Among them, the first sub-pattern 10711 is located in the first sub-layer 107a, and the second sub-pattern 10712 is located in the second sub-layer 107b. That is to say, the first sub-pattern 10711 and the second sub-pattern 10712 are located in different layers, that is, the first sub-pattern 10711 and the second sub-pattern 10712 should be prepared separately.

[0133] In some embodiments, referring to Figure 7A , Figure 7B , Figure 8A and Figure 8B , the material of the first sub-layer 107a is a transparent conductive oxide, and the material of the second sub-layer 107b is a metal or an organic light-shielding material.

[0134] Exemplarily, the materials of the first sub-pattern 10711 and the second pattern 1071b located in the first sub-layer 107a are transparent conductive oxides, and the material of the second sub-pattern 10712 located in the second sub-layer 107b is a metal or an organic light-shielding material. That is to say, the second sub-pattern 10712 functions to block light, so that the transmittance of the first pattern 1071a is less than that of the second pattern 1071b, that is, the first pattern 1071a has a light-blocking effect relative to the second pattern 1071b, where, Figure 7A , Figure 7B the material of the second sub-pattern 10712 in Figure 8A , Figure 8B is a metal,

[0135] The following describes the formation steps K1 to K8 of the first pattern 1071a and the second pattern 1071b when the light-shielding conductive layer 107 includes the first sub-layer 107a and the second sub-layer 107b. Specifically:

[0136] K1. First, form an initial first sub-layer 107a' of the light-shielding conductive layer 107 on the second insulating layer 106.

[0137] Exemplarily, forming the initial first sub-layer 107a' can be depositing a transparent conductive oxide material on the second insulating layer 106.

[0138] It should be noted that the above initial first sub-layer 107a' is a whole layer of film laid on the second insulating layer 106, and the initial first sub-layer 107a' has not undergone a patterning process.

[0139] K2. Form an initial second sub-layer 107b' on the initial first sub-layer 107a'.

[0140] Exemplarily, forming the initial second sub-layer 107b' can be depositing a metal or an organic light-shielding material on the transparent conductive oxide material.

[0141] It should be noted that the above initial second sub-layer 107b' is a whole layer of film laid on the initial first sub-layer 107a', and the initial second sub-layer 107b' has not undergone a patterning process.

[0142] K3. Form a photoresist layer on the initial second sub-layer 107b'.

[0143] K4. Use a mask to expose and develop the photoresist layer to obtain a patterned photoresist layer.

[0144] It should be noted that the photomask includes a plurality of openings, as well as halftone regions and full-tone regions. The portions of the photoresist layer corresponding to the plurality of openings are removed, and portions of the initial second sub-layer 107b' are exposed, while the portions corresponding to the halftone regions and full-tone regions are retained to form a patterned photoresist layer. Among them, the portions of the patterned photoresist layer corresponding to the halftone regions and the full-tone regions are in contact with each other.

[0145] The portion of the patterned photoresist layer corresponding to the halftone region covers the active layer of the first transistor and the region within a set pitch range around the active layer of the first transistor.

[0146] K5. Etch the initial second sub-layer 107b' of the photoresist layer exposed after development, and at the same time etch the initial first sub-layer 107a' to form an initial light-shielding conductive pattern 1071'.

[0147] K6. Thin the patterned photoresist layer until the portion of the patterned photoresist layer corresponding to the halftone region is removed, exposing the first portion (corresponding to the first pattern) of the initial light-shielding conductive pattern 1071'.

[0148] Exemplarily, wet etching, dry etching or laser etching processes can be used to thin the photoresist layer. In this example, the dry etching process is adopted, which can also be called the ashing process of the photoresist. It is processed in an ECCP (Enhance Cathode Coupling Plasma) dry etching equipment, using NF3 and O2 as working gases. The process conditions are: the source power / bias power is 12kW / 10kW, the flow rate of NF3 / O2 is 1500 / 10000sccm, and the working pressure is 40mt.

[0149] K7. Etch the initial light-shielding conductive pattern 1071' located in the portion of the initial second sub-layer 107b' corresponding to the halftone region to obtain the light-shielding conductive pattern 1071', that is, simultaneously form the second pattern 1071b.

[0150] K8. Strip the remaining photoresist.

[0151] In some embodiments, referring to Figure 2A , the sub-pixel PX further includes a pixel electrode 11 and a common electrode 12; the light-shielding conductive layer 107 includes a first sub-layer 107a, and the first sub-layer 107a further includes a pixel electrode pattern 111; the gate layer 102 further includes a common electrode pattern 121 and a common signal line COM. The material of the common electrode pattern 121 is a transparent conductive material, and the common signal line COM is connected to the common electrode pattern 121; the pixel electrode pattern 111 overlaps with the common signal line COM.

[0152] It should be noted that the first sub-layer 107a further includes a pixel electrode pattern 111, that is, the pixel electrode pattern 111 and the second pattern 1071b are located in the same layer. That is to say, the pixel electrode pattern 111 and the second pattern 1071b are made of the same material. During the preparation process of the pixel electrode pattern 111, the second pattern 1071b can be simultaneously patterned and prepared. Such a setting can further simplify the process.

[0153] Exemplarily, as Figure 2A shown, the common electrode pattern 121 and the common signal line COM overlap in the orthographic projection on the substrate, and the common electrode pattern 121 and the common signal line COM are located in the same film layer, that is, the gate layer 102. That is to say, the common electrode pattern 121 and the common signal line COM are overlapped and connected in the gate layer 102.

[0154] Among them, the pixel electrode pattern 111 and the relatively arranged common electrode pattern 121 can form a capacitor Cst. And the above-mentioned common electrode pattern 121 and the common signal line COM are overlapped and connected, which can increase the capacitance. In addition, the pixel electrode pattern 111 and the common signal line COM are arranged to overlap, and the overlapping part can be used as a compensation capacitor, which can reduce voltage fluctuations, is beneficial to improving the signal transmission effect, and further reduces losses.

[0155] Exemplarily, the common signal line COM is used to transmit a common voltage signal. The material of the common signal line can be metal. Compared with the material of the common electrode layer (indium tin oxide), the resistance is reduced. Using the common signal line COM to transmit the common voltage signal is beneficial to improving the voltage uniformity of the common electrode, improving the signal transmission effect, reducing losses, and further improving the in-plane light uniformity.

[0156] In some embodiments, as Figure 2A 、 Figure 3A and Figure 3B shown, the gate layer 102 includes a gate line GT. The gate pattern 1021 of the first transistor T1 is the part of the gate line GT that overlaps with the active layer pattern 1041 of the first transistor T1; the second pattern 1071b is connected to the gate line GT.

[0157] Exemplarily, referring to Figure 3A and Figure 3B, the gate pattern 1021 of the first transistor T1 is the part of the gate line GT that overlaps with the active layer pattern 1041 of the first transistor T1, that is, the gate pattern 1021 is a part of the gate line GT. The gate pattern 1021 and the gate line GT have the same gate voltage signal. The second pattern 1071b is connected to the gate line GT. Since the material of the second pattern 1071b is a transparent conductive oxide material, it is equivalent to that the second pattern 1071b can receive the gate voltage signal transmitted by the gate line GT. Further, the first pattern 1071a is in contact with the second pattern 1071b. Therefore, the first pattern 1071a and the second pattern 1071b can transmit the same gate voltage signal, and the part of the first pattern 1071a that overlaps with the active layer pattern 1041 can serve as the top gate structure of the first transistor T1, and the gate pattern 1021 of the first transistor T1 serves as the bottom gate structure of the first transistor T1. Thus, the first transistor T1 is a double-gate transistor. The above structure can set the first transistor T1 as a double-gate transistor, which can effectively suppress the penetration of the drain terminal power line into the channel region, greatly reduce the threshold voltage drift, reduce the short-channel effect, is beneficial to realizing the reduction of off-state leakage, improving the abnormal signal defect, and thus improving the overall signal output ability of the array substrate 10.

[0158] In some embodiments, such as Figure 9A and Figure 9B shown, the array substrate 10 includes a gate driving circuit 13. The gate driving circuit 13 includes at least one second transistor T2 and a storage capacitor C; the gate layer 102 further includes a gate control line GK. The gate control line GK includes the gate pattern 1022 of the second transistor T2; the active layer 104 further includes the active layer pattern 1042 of the second transistor T2; the array substrate 10 further includes a source-drain metal layer 105 disposed on the side of the active layer 104 away from the substrate 101. The source-drain metal layer 105 is in contact with the active layer 104. The source-drain metal layer 105 includes the first plate pattern C1 of the storage capacitor C; the light-shielding conductive layer 107 further includes a conductive pattern 1072. The conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2 and also overlaps with the first plate pattern C1 of the storage capacitor C; the conductive pattern 1072 is connected to the gate control line GK; the gate control line GK overlaps with the first plate pattern C1 of the storage capacitor C.

[0159] Exemplarily, referring to Figure 9A , the array substrate 10 further includes a non-display area BB disposed around the display area AA. Among them, the non-display area BB is provided with gate driving circuits 13 located on both sides of the display area AA and in the row direction X and a data driving area 14 disposed on one side of the display area AA along the column direction Y.

[0160] It should be noted that the gate driving circuit 13 is used to output a gate signal to the display area to control each sub-pixel to turn on and input a data signal. Refer to Figure 9A , the gate driving circuit 13 includes a plurality of cascaded shift registers. In two gate driving circuits 13, the same-stage shift registers are electrically connected to the same gate line GT. For example, the first-stage shift registers of the two gate driving circuits 13 are both electrically connected to the first gate line GT, and output a gate scanning signal to the gate line at the same time, that is, bilateral driving is used for display. In this way, the driving efficiency can be improved, the scanning time can be saved, so that a plurality of sub-pixels can be turned on faster, the data signal can be written, and the display effect can be improved. Optionally, this case can also support single-sided driving, that is, a gate driving circuit is provided on one side of the non-display area BB, which is not limited here.

[0161] Exemplarily, refer to Figure 9A , the data driving area 14 may include a driving chip, and the driving chip is connected to a plurality of data signal lines DT. Combining Figure 1 , the plurality of data signal lines DT respectively transmit data voltage signals to a plurality of sub-pixels PX in the display area AA. Among them, the plurality of data signal lines DT extend along the column direction Y, and each data signal line DT is connected to a column of sub-pixels PX.

[0162] Exemplarily, refer to Figure 9B and Figure 9C , Figure 9B is a partial cross-sectional structure diagram of the gate driving circuit. Among them, the gate driving circuit 13 includes a plurality of shift registers. The shift register includes a plurality of transistors and a storage capacitor C. The shift register includes an input end, an output end and a cascade end. The second transistor T2 is a transistor related to the output voltage signal and the pull-up node voltage signal among the plurality of transistors. Exemplarily, there are two second transistors T2. One of the second transistors is connected to the output end, and the other second transistor is connected to the cascade end, and both transistors are connected to the storage capacitor C. The storage capacitor C is located in the gap formed between the two second transistors T2. In this way, the area of the region where the gate driving circuit 13 is located can be fully utilized, so that the area utilization rate of the gate driving circuit 13 is increased, and the area occupied by the original capacitor is reduced. Since the area of the peripheral region of the gate driving circuit 13 in the display area AA is small, a narrow border can be realized.

[0163] In some embodiments, such as Figure 9CAs shown, the shift register further includes an initial gate turn-on voltage input terminal, which is connected to the first pole of the second transistor T2. The second pole of the second transistor T2 is connected to the output terminal Output. The output terminal Output is connected to the gate line GT. The gate line GT is connected to the control pole of the first transistor T1 in the sub-pixel of the display area. The control pole of the second transistor is connected to the pull-up node PU. The initial gate turn-on voltage input terminal is configured to transmit an initial gate turn-on voltage signal. The initial gate turn-on voltage input terminal is, for example, the clock signal terminal CLK. The voltage value of the gate turn-on voltage output from the second pole of the second transistor T2 is related to the initial gate turn-on voltage VGH’, that is, the voltage value of the gate turn-on voltage transmitted from the output terminal Output of the shift register to the display area through the connected gate line GT is related to the initial gate turn-on voltage VGH’.

[0164] Exemplarily, the gate control line GK includes the gate pattern 1022 of the second transistor T2. The gate control line GK is used to provide a gate control signal for the second transistor T2. It is set that the conductive pattern 1072 is connected to the gate control line GK. That is to say, the conductive pattern 1072 can transmit the same gate control signal as the gate control line GK, and the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2. That is, this overlapping part can serve as the top gate of the second transistor T2, while the gate pattern 1022 of the second transistor T2 is the bottom gate of the second transistor T2. It can be understood that the second transistor T2 is a double-gate transistor. With such a setting, on the one hand, it can increase the carrier mobility of the organic field-effect first transistor, so that the second transistor has a higher current density. That is to say, the current can be increased, and the problem of insufficient charging rate caused by the decrease of the current of the second transistor due to long-term use in the outdoor or harsh environment of the display device can be improved, and the performance of the second transistor can be improved; on the other hand, the conductive pattern 1072 and the gate pattern 1022 of the second transistor T2 jointly control the channel region of the active layer pattern 1042 of the second transistor T2, which can effectively suppress the penetration of the drain-side power line into the channel region, greatly reduce the threshold voltage drift, reduce the short-channel effect, is beneficial to realizing the reduction of leakage current, improving the signal abnormality defect, and thus improving the overall signal output ability of the gate driving circuit. Further, it can increase the range of the gate turn-on voltage, and then ensure the normal operation of the outdoor display product and improve the life of the display product.

[0165] It should be noted that according to the above description, connecting the conductive pattern 1072 to the gate control line GK and overlapping the conductive pattern 1072 with the active layer pattern 1042 of the second transistor T2 can improve the degree to which the second transistor T2 can withstand characteristic degradation. After analysis by the inventors of this application, in a harsh outdoor usage environment, such as high temperature, high brightness and other environmental conditions, the characteristics of the second transistor T2 will deteriorate. Exemplarily, the threshold voltage of the second transistor T2 will increase. Since the threshold voltage of the second transistor T2 increases and it is in a positive voltage state for a long time, it will cause the phenomenon of insufficient charging of the second transistor, and then cause the turn-on voltage of the sub-pixels output by the second transistor to the display area to decrease, that is, the gate turn-on voltage decreases. That is to say, due to the characteristic degradation of the second transistor T2, the output gate turn-on voltage VGH decreases and cannot ensure the normal turn-on of the first transistor T1. And since the voltage of the gate turn-on voltage VGH is also related to the initial gate turn-on voltage, if the gate turn-on voltage VGH is to ensure the normal turn-on of the first transistor T1, it is necessary to increase the working voltage range of the initial gate turn-on voltage.

[0166] The above working voltage range means that when the initial gate turn-on voltage VGH’ is within a certain range, it can ensure that the gate turn-on voltage can control the first transistor T1 to turn on normally. Exemplarily, when the second transistor T2 is a bottom-gate transistor, when the initial gate turn-on voltage VGH’ is 25V to 32V, the first transistor T1 can work normally, that is, the working voltage range of the initial gate turn-on voltage VGL’ can be adjusted within 7V to meet the requirements for the normal turn-on of the first transistor T1. And when the second transistor T2 is a double-gate transistor, according to the above content, it can be seen that the current can be increased. That is to say, under the same conditions, the required initial gate turn-on voltage VGH’ decreases. For example, when the initial gate turn-on voltage VGH’ is 22V, the gate turn-on voltage output by the second transistor T2 can meet the requirements for the normal turn-on of the first transistor T1. At this time, the first transistor T1 can work normally when the initial gate turn-on voltage VGH’ is 20V to 32V, that is, the working voltage range of the initial gate turn-on voltage VGH’ can be adjusted within 12V to meet the requirements for the normal turn-on of the first transistor T1. Therefore, the working voltage range of the above initial gate turn-on voltage VGH’ has been expanded to a certain extent when the second transistor T2 is a double-gate transistor compared with when the second transistor T2 is a bottom-gate transistor.

[0167] In some embodiments, for example, for display products used outdoors, the requirement for the initial gate turn-on voltage VGH' is higher, and the initial gate turn-on voltage VGH' needs to be controlled within a certain range. Therefore, in order to achieve precise control of the initial gate turn-on voltage VGH', the inventor judges the initial gate turn-on voltage VGH' through a long-term reliability evaluation method. For example, by observing the initial gate turn-on voltage VGH' when the first transistor T1 is turned on and recording the critical voltage value of the initial gate turn-on voltage VGH' at which the display device starts to show abnormal display. Then, a difference comparison is made with the set initial gate turn-on voltage value. The larger the difference, the larger the operating voltage range of the initial gate turn-on voltage VGH', that is, the adjustment of the operating voltage range has been improved to a certain extent. Specifically, within the first period of time, the characteristics of the second transistor T2 are accelerated to deteriorate, such as factors like light and temperature. Then, within the second period of time, the initial gate turn-on voltage VGH' is lowered for observation, and the initial gate turn-on voltage VGH' when the display device starts to show abnormalities is recorded. A difference comparison is made with the set initial gate turn-on voltage VGH'. The larger the difference, the larger the operating voltage range of the initial gate turn-on voltage VGH', and the adjustment of the operating voltage range has been expanded to a certain extent. The above long-term reliability evaluation method can obtain that the better the characteristics of the transistor, the better the performance of the initial gate turn-on voltage VGH' by observing the change of the initial gate turn-on voltage VGH' under corresponding conditions by changing the characteristics of the transistor. That is, when the characteristic parameters of the transistor are controlled within a certain range, the change range of the initial gate turn-on voltage VGH' can better meet outdoor conditions. This evaluation method shows that in a more severe usage environment such as outdoors, when the voltage value of the initial gate turn-on voltage VGH' is within the adjusted operating voltage range, the normal operation of outdoor products can still be ensured.

[0168] Regarding the above structure in which the second transistor T2 is set as a double-gate transistor, the inventor found through testing that the second transistor T2 being a double-gate transistor can achieve improvement. Furthermore, it can extend the service life of the display device and improve the reliability of the display device.

[0169] Regarding the above structure of the second transistor, the inventor conducted experimental verification. The on-state current and off-state leakage current of the second transistor in the case of a double-gate structure were respectively tested, as well as the on-state current and off-state leakage current of the second transistor in the case of the original bottom-gate structure. The results obtained are shown in Table 2.

[0170] The following shows the experimental data comparison results of the second transistor as a double-gate transistor and a bottom-gate transistor in Table 2.

[0171] Table 2

[0172]

[0173] According to the above table, when the second transistor is a double-gate transistor, the on-state current is higher and the off-state leakage current can be reduced compared to the case where the second transistor is a bottom-gate transistor. That is to say, under harsh environmental conditions, when the second transistor is a double-gate transistor, the characteristic degradation of the second transistor can be reduced compared to when the second transistor is a bottom-gate transistor. Exemplarily, at this time, the operating voltage range of the initial gate turn-on voltage VGH’ can be expanded. For example, when the second transistor is a bottom-gate transistor, an initial gate turn-on voltage VGH’ of 25V to 32V can make the first transistor turn on normally. By setting the second transistor as a double-gate transistor, the on-state current can be increased. According to the characteristic curve of the transistor, the larger the current, the higher the corresponding voltage. That is to say, when the on-state current increases, the corresponding initial gate turn-on voltage VGH’ decreases. For example, at this time, the initial gate turn-on voltage VGH’ is 20V to 32V, that is, the operating voltage range of the initial gate turn-on voltage VGH’ is expanded by 5V. Similarly, by setting the second transistor as a double-gate transistor, the off-state leakage current can be reduced, that is, the current loss can be reduced. According to the characteristic curve of the transistor, the smaller the current, the lower the corresponding voltage, that is, the operating voltage of the initial gate turn-on voltage VGH’ corresponding to the normal operation of the first transistor is reduced. That is to say, the operating voltage range of the initial gate turn-on voltage VGH’ becomes larger and is improved to a certain extent compared to the original normal operating voltage range.

[0174] Through the above analysis, since the conductive pattern 1072 is connected to the gate control line GK and the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2, a double-gate design for the second transistor can increase the carrier mobility of the organic field-effect second transistor, making the second transistor have a higher current density. That is to say, it can simultaneously increase the on-state current of the second transistor, reduce the leakage current, improve the threshold voltage shift of the second transistor T2, alleviate the specific degradation of the second transistor T2, and improve the performance of the second transistor, thereby increasing the operating voltage range of the initial gate turn-on voltage VGH’.

[0175] In some embodiments, referring to Figure 9B , the distance D1 between the first plate pattern C1 of the storage capacitor C and the conductive pattern 1072 is equal to the distance D2 between the first plate pattern C1 of the storage capacitor C and the gate control line GK.

[0176] Exemplarily, since the conductive pattern 1072 overlaps with the active layer pattern 1042 of the second transistor T2 and also overlaps with the first plate pattern C1 of the storage capacitor C, that is, the overlapping portion C21 between the conductive pattern 1072 and the active layer pattern 1042 of the second transistor T2 can be used as part of the second plate pattern C2 of the storage capacitor C. Additionally, the gate control line GK overlaps with the first plate pattern C1 of the storage capacitor C, which means that the overlapping portion C22 between the gate control line GK and the first plate pattern C1 of the storage capacitor C can also be used as part of the second plate pattern C2 of the storage capacitor C. Thus, the second plate pattern C2 of the storage capacitor C includes two parts. Compared with the embodiment where the second plate pattern C2 is only provided in the gate layer 102, the above setting can increase the storage capacitance of the storage capacitor C. Moreover, the distance between the first plate pattern C1 of the storage capacitor C and the conductive pattern 1072 is equal to the distance between the first plate pattern C1 of the storage capacitor C and the gate control line GK. That is to say, the storage capacitor C' at this time is composed of two parts, and the sizes of the two parts of the storage capacitor C are equal. The storage capacitor C' becomes twice the original storage capacitor C. Therefore, on the premise of ensuring the capacitance value of the storage capacitor C, the area of the first plate pattern C1 of the storage capacitor C can be set to be halved. Such a setting can not only ensure the normal use of the storage capacitor but also reduce the area occupied by the storage capacitor C in the gate driving circuit in space, thereby reducing the overall area of the gate driving circuit and realizing the narrow border of the display device.

[0177] The differences between the double-gate transistor and the bottom-gate transistor will be described below in combination with the inventor's verification of the changes in the conduction band and valence band of the transistor under the action of voltage.

[0178] As Figure 10A shown, when the transistor is not powered on, Figure 10A in the energy band diagram shown, the conduction band (E C ) and the valence band (E V ) do not bend, where E F is the Fermi level, located between the conduction band (E C ) and the valence band (E V ). When the gate turn-on voltage VGH is 15V, the transistor can be normally turned on. Referring to Figure 10B , in the case of a double-gate transistor, the surfaces of the active layer pattern 1042 of the transistor close to the first insulating layer 103 and the second insulating layer 106 are both affected by the gate turn-on voltage VGH, and electron accumulation will occur on the surface of the first insulating layer 103 and the surface close to the second insulating layer 106, causing the conduction band to bend downward. As Figure 10C shown, Figure 10CThe transistor shown in is a bottom-gate transistor. The active layer pattern 1042 of the transistor is close to the surface of the first insulating layer 103 and is affected by the gate turn-on voltage VGH. Electrons gather on the surface of the first insulating layer 103, causing the conduction band to bend downward. Figure 10C In the case where the transistor shown is a bottom-gate transistor, in the case where the transistor is a double-gate transistor, and in the on state, the conduction band (E C ) and valence band (E V ) has a lower central energy level in the mobility gap between the two gate transistors, making the electron density of the active layer pattern of the dual-gate transistor greater than that of the bottom-gate transistor, thereby increasing the current. The higher current can give the display product more room for current reduction and can improve the phenomenon of abnormal screen display due to insufficient charging rate of the transistor.

[0179] When the gate-off voltage VGL is -8V, the transistor can be turned off normally. Figure 10D In the case where the transistor is a dual-gate transistor, the surface of the active layer 104 pattern of the transistor close to the first insulating layer 103 and the surface close to the second insulating layer 106 will be affected by the gate-off voltage VGL, and holes will be gathered on the surface of the first insulating layer 103 and the surface close to the second insulating layer 106, causing the conduction band to bend upward. Figure 10E As shown, Figure 10E The transistor shown in is a bottom-gate transistor. The active layer pattern 1042 of the transistor is close to the surface of the first insulating layer 103 and is affected by the gate turn-on voltage VGH. Electrons gather on the surface of the first insulating layer 103, causing the conduction band to bend upward. Figure 10E In the case where the transistor shown is a bottom-gate transistor, in the case where the transistor is a double-gate transistor, and in the off state, the conduction band (E C ) and valence band (E V ) has a higher central energy level in the mobility gap between the top and bottom gate transistors, making the hole density of the active layer pattern of the dual-gate transistor smaller than that of the bottom-gate transistor, thereby reducing the leakage current and improving the undesirable phenomenon such as abnormal output signals caused by excessive leakage of the transistor.

[0180] The above is an analysis of the beneficial effects of setting the transistor as a dual-gate transistor relative to setting the transistor as a bottom-gate transistor, wherein the above transistors are applicable to the first transistor and the second transistor, that is, the first transistor and the second transistor set as dual-gate transistors also have the above-mentioned effects of increasing current and reducing leakage current.

[0181] Reference Figure 11A , Figure 11B , Figure 12A and Figure 12B, embodiments of the present disclosure further provide a display panel 100, which includes the array substrate 10 provided in any of the above embodiments. Therefore, the display panel 100 provided by the present utility model has all the beneficial effects of the array substrate 10 provided in any of the above embodiments, and will not be elaborated herein.

[0182] In some embodiments, referring to Figure 11A and Figure 11B , the display panel 100 further includes a color filter substrate 20 disposed on the array substrate 10, and at least one spacer 30 disposed between the array substrate 10 and the color filter substrate 20; the spacer 30 includes a first spacer 31, and the first spacer 31 is disposed on one side of the second pattern 1071b and in contact with the second pattern 1071b.

[0183] Exemplarily, referring to Figure 11A and Figure 11B , the first spacer 31 may be a red color resist block, a green color resist block, and a blue color resist block. Among them, the first spacer 31 may be formed by stacking two layers of color resist blocks. It should be noted that using color resist blocks to form spacers can reduce the light brightness in the dark state and improve the light contrast during dark state display.

[0184] Exemplarily, referring to Figure 11B and Figure 12B , the color filter substrate 20 may further include a color resist layer 108 disposed on the spacer 30, and a black matrix layer 109 disposed on the side of the color resist layer 108 away from the spacer 30. Among them, the black matrix layer 109 has a light shielding function to prevent the display panel 100 from leaking light, and the color resist layer 108 is used to block part of the color light and has an adjustment effect on light.

[0185] It should be noted that, referring to Figure 11B and Figure 12B , the surface of the spacer 30 away from the array substrate 10 is connected to the surface of the color resist layer 108 close to the array substrate 10. When the color resist layer 108 is displaced, the spacer 30 will be displaced together with the color resist layer 108.

[0186] Exemplarily, referring to Figure 13A and Figure 13B , Figure 13A is a structural diagram of the spacer 30 being displaced under an external force when the second pattern 1071b is not provided, Figure 13B is a structural diagram of the spacer 30 being displaced under an external force when the second pattern 1071b is provided. Among them, the arrow shown in the figure indicates the displacement direction Z of the spacer 30. From the figure, it can be obtained that Figure 13AWhen the first spacer 31 in [it] is deflected under an external force, since the surface of the side of the first spacer 31 away from the array substrate 10 is connected to the surface of the color resist layer 108 on the side close to the array substrate 10, when the color resist layer 108 is deflected, the first spacer 31 will be deflected together with the color resist layer 108. That is to say, the first spacer 31 will be deflected to the corresponding area of the opening of the sub-pixel, and there is liquid crystal provided between the array substrate 10 and the color filter substrate 20 at the opening of the sub-pixel. Resin layers are provided on the surface of the array substrate 10 close to the liquid crystal side and on the surface of the color filter substrate 20 close to one side for protecting the liquid crystal. During the process of the deflected first spacer 31 rebounding under pressure, the surface of its side close to the array substrate 10 is closer to the array substrate 10 during rebounding and is likely to scratch the resin layer on the surface of the array substrate close to the liquid crystal side, thereby causing the liquid crystal alignment to fail and resulting in the defective phenomenon of blue spots. And Figure 13B in [it], the first spacer 31 is arranged on one side of the second pattern 1071b, and the second pattern 1071b can play a role in raising the first spacer 31, and the height of the first spacer 31 can be reduced, that is, the side of the first spacer 31 close to the array substrate 10 is farther from the array substrate 10 when rebounding under pressure. That is to say, during the process of the first spacer 31 rebounding under pressure, the surface of its side close to the array substrate 10 will not scratch the resin layer on the surface of the array substrate close to the liquid crystal side during the rebounding process, and the problem of liquid crystal alignment failure can be avoided, and further the defective phenomenon of blue spots can be avoided; and since the first spacer 31 is arranged on one side of the second pattern 1071b, the second pattern 1071b can play a role in raising the first spacer 31. That is to say, the height of the first spacer 31 can be reduced compared with the spacer arranged in the related art. Furthermore, the width of the black matrix layer 109 correspondingly arranged above the first spacer 31 can be reduced. Refer to Figure 13A and Figure 13B , Figure 13B the width of the black matrix layer 109 in [it] is Figure 13A shorter than the width of the black matrix layer 109 in [it], and further the aperture ratio of the sub-pixel can be improved. Exemplarily, the aperture ratio improvement can be 4%. At the same time, the liquid crystal arrangement is disordered at the position where the first spacer 31 is located, and the phenomenon of light leakage failure is likely to occur. The black matrix layer 109 can avoid the problem of light leakage failure at the corresponding position of the first spacer 31 and affect the display of the display panel.

[0187] In some embodiments, refer to Figure 14 , the spacer 30 includes a second spacer 32, and the height H1 of the first spacer 31 is higher than the height H2 of the second spacer 32; the second spacer 32 is arranged on one side of the second pattern 1071b.

[0188] Exemplarily, refer to Figure 14, the spacer 30 includes a first spacer 31 and a second spacer 32. Among them, referring to Figure 12A and Figure 12B , the second spacer 32 can be any one of a red color resist block, a green color resist block, and a blue color resist block. Referring to Figure 11A and Figure 11B , the first spacer 31 can be formed by stacking two layers of color resist blocks. It can reduce the light brightness in the dark state and improve the light contrast during dark state display.

[0189] It should be noted that the first spacer 31 and the second spacer 32 between the array substrate 10 and the color filter substrate 20 can be arranged in an array. For example, the first spacer 31 and the second spacer 32 are located in the area of the same sub-pixel, or the first spacer 31 and the second spacer 32 are respectively located in the areas of two adjacent sub-pixels and are respectively located on the side of the second pattern in their respective sub-pixels. The two adjacent sub-pixels are, for example, a green sub-pixel and a blue sub-pixel, etc., which are not limited here.

[0190] Exemplarily, referring to Figure 14 , the materials of the first spacer 31 and the second spacer 32 are the same as the material of the second pattern 1071b, and can be formed synchronously when the second pattern 1071b is fabricated, achieving the purpose of simplifying the process. In addition, since the first spacer 31 and the second spacer 32 are arranged in an array on the array substrate 10, the height H1 of the first spacer 31 is set higher than the height H2 of the second spacer 32, so that the first spacer 31 plays a main supporting role. When the pressure is relatively large, the second spacer 32 and the first spacer 31 play a supporting role simultaneously to prevent the liquid crystal from being affected during deflection, resulting in display problems of the display device.

[0191] Exemplarily, referring to Figure 11B and Figure 12B , among them, Figure 11B is the cross-sectional structure diagram of the first spacer, Figure 12B is the cross-sectional structure diagram of the second spacer. Since the height H1 of the first spacer 31 is higher than the height H2 of the second spacer 32 and the first spacer 31 plays a main supporting role, the first spacer 31 is set to be in contact with the second pattern 1071b, and the second spacer 32 is not in contact with the second pattern 1071b. That is to say, when the pressure on the first spacer 31 is relatively large and the height H1 of the first spacer 31 is compressed to the height H2 of the second spacer 32, the second spacer 32 and the first spacer 31 play a supporting role simultaneously.

[0192] Exemplarily, referring to Figure 14, setting the first spacer 31 and the second spacer 32 can ensure that when the display panel 100 is pressed by an external force, the display panel 100 can maintain a certain cell gap. The inventors of the present application found that the transistors will exhibit abnormal characteristics when the cell gap is under pressure, and the greater the pressure, the more obvious the abnormal phenomenon. During the manufacturing process, after cell formation, it is inevitable to experience suction cup adsorption handling or support, etc. When the first spacer 31 and the second spacer 32 are under pressure, the force exerted on the transistors is too large, which poses a risk of transistor performance degradation. Making the materials of the first spacer 31 and the second spacer 32 the same as the material of the second pattern 1071b. Since the material of the second pattern 1071b can be an organic polymer material, it has strong adhesion, that is, it can make the first spacer 31 and the second spacer 32 adhere more firmly to the array substrate, and can prevent the first spacer 31 and the second spacer 32 from falling off or shifting during use.

[0193] Some embodiments of the present disclosure provide a display device 1000, such as Figure 15 shown. The display device can be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), an in-vehicle computer, a wearable display device, etc. The specific form of the display device in the embodiments of the present disclosure is not particularly limited. As Figure 16 shown, the display device 1000 includes the display panel 100 provided in any of the above embodiments. The display panel 100 includes a display side 100a and a non-display side 100b. Therefore, the display device 1000 provided by the present invention has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be elaborated here.

[0194] Exemplarily, as Figure 16 shown, the display device 1000 in the embodiments of the present disclosure is exemplified by a liquid crystal display device. Referring to FIG. 10, in some embodiments, the main structure of the liquid crystal display device 1000 includes a frame 200, a cover plate 300, a display panel 100, a backlight module 400, a circuit board 500, and other electronic components.

[0195] Among them, the frame 200 defines an accommodation space. The display panel 100, the backlight module 400, the circuit board 500, and other electronic components are disposed in the accommodation space. The cover plate 300 is disposed on the open side of the frame 200. The display panel 100 is disposed closer to the cover plate 300 relative to the backlight module 400 and the circuit board 500. The circuit board 500 is disposed farther from the cover plate 300 relative to the display panel 100 and the backlight module 400. The backlight module 400 is disposed on the non-display side 100b of the display panel 100 and is located between the display panel 100 and the circuit board 500. Among them, the backlight module 400 is used to provide a backlight source for the display device 1000.

[0196] Exemplarily, referring to Figure 16 , the display panel 100 includes a liquid crystal layer 50 between the array substrate 10 and the counter substrate 20. The array substrate 10 and the color filter substrate 20 can be adhered together by a sealant 40, thereby defining the liquid crystal layer 50 within the region surrounded by the sealant 40.

[0197] Exemplarily, the liquid crystal layer 50 contains a plurality of liquid crystal molecules. Since the display panel 100 itself cannot emit light, a backlight module 400 needs to be provided. The backlight source provided by the backlight module 400 passes through the liquid crystal layer in the display panel. Since the liquid crystal molecules have the property of rotating the polarization of polarized light, a specific molecular arrangement direction can change the polarization direction of the polarized light. When the arrangement direction of the liquid crystal molecules rotates under the control of the electric field generated between the pixel electrode and the common electrode, the polarization direction of the polarized light passing through the liquid crystal molecules also changes. Thus, the light passing through the liquid crystal layer can be controlled to be emitted, that is, through the deflection of a plurality of liquid crystal molecules, the light is emitted from the display panel, and thus the image to be displayed can be displayed on the display panel 100. Herein, the image to be displayed is the image that the display panel 100 needs to present, for example, the image to be displayed is a black, white, gray, or color image, etc. The two opposite sides of the backlight module 400 are respectively the light-emitting side and the non-light-emitting side. The light emitted by the backlight module 400 is emitted from the light-emitting side. The two opposite sides of the display panel 100 are respectively the display side 100a and the non-display side 100b, and the non-display side 100b of the display panel 100 faces the light-emitting side of the backlight module 400.

[0198] In some embodiments, the above display device 1000 is a liquid crystal display device, and the backlight module 400 uses Mini LED chips or Micro LED chips.

[0199] In the display device 1000 provided by the present utility model, the light-emitting backplane 1 in the backlight module 400 uses Mini LED or Micro LED as the light-emitting device, provides backlight for the display panel 100, and the backlight module 400 is a direct-lit backlight design, and can be made into local dimming, which has better light transmission uniformity, higher contrast ratio (Contrast Ratio t), and more brightness and darkness details compared with the general side-lit backlight. Compared with the OLED display device, the display device 1000 with Mini LED backlight design has better color rendering.

[0200] As Figure 16As shown, some embodiments of the present disclosure provide a display device. The display device provided by the embodiments of the present disclosure may be any device that displays whether it is moving (e.g., video) or stationary (e.g., still image), and whether it is text or image. More specifically, it is expected that the embodiments can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0201] In the description of this specification, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0202] As described above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure, thinking of changes or substitutions, should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. An array substrate, characterized in that: comprising a plurality of sub-pixels, at least one sub-pixel of the plurality of sub-pixels comprising a first transistor; substrate substrate; A gate layer disposed on one side of the base substrate, the gate layer comprising a gate pattern of the first transistor; An active layer disposed on a side of the gate layer away from the base substrate, the active layer comprising an active layer pattern of the first transistor; a light-shielding conductive layer disposed on a side of the active layer away from the base substrate, the light-shielding conductive layer comprising a light-shielding conductive pattern, the light-shielding conductive pattern comprising a first pattern and a second pattern, an orthographic projection of the active layer pattern of the first transistor on the base substrate being located within an orthographic projection of the first pattern on the base substrate, and a distance between an orthographic projection boundary of the first pattern on the base substrate and an orthographic projection boundary of the active layer pattern of the first transistor on the base substrate being within a set spacing range; The transmittance of the first pattern is less than or equal to the transmittance of the second pattern; The second pattern is connected to a gate pattern of the first transistor.

2. The array substrate according to claim 1, characterized in that: The light-shielding conductive layer includes a first sublayer, and the first pattern and the second pattern are located in the first sublayer; The material of the second pattern is a transparent conductive oxide, and the material of the first pattern is a blackened transparent conductive oxide; The blackened transparent conductive oxide is a transparent conductive oxide obtained by blackening treatment, wherein the process conditions for reducing light transmittance are: source power range of 5kW to 7kW, hydrogen flow rate of 70000 to 80000sccm, working pressure range of 900 to 1200mt, and processing time range of 10 to 20S.

3. The array substrate according to claim 1, characterized in that: The light-shielding conductive layer includes a first sublayer, and the first pattern and the second pattern are located in the first sublayer; the material of the first pattern and the second pattern is metal, and the transmittance of the first pattern is equal to the transmittance of the second pattern.

4. The array substrate according to claim 1, characterized in that: The light-shielding conductive layer includes a first sublayer, and the first pattern and the second pattern are located in the first sublayer; the material of the second pattern is a transparent conductive oxide, and the material of the first pattern is a metal or an organic light-shielding material.

5. The array substrate according to claim 1, characterized in that: The light-shielding conductive layer includes a first sublayer and a second sublayer, wherein the second sublayer is located on a side of the first sublayer away from the base substrate; and the transmittance of the second sublayer is less than the transmittance of the first sublayer; The first pattern includes a first sub-pattern located in the first sub-layer and a second sub-pattern located in the second sub-layer, and the second pattern is located in the first sub-layer.

6. The array substrate according to claim 5, characterized in that: The material of the first sub-layer is a transparent conductive oxide, and the material of the second sub-layer is a metal or an organic light-shielding material.

7. The array substrate according to claim 1, characterized in that: The set spacing range is 1 μm to 2.5 μm.

8. The array substrate according to any one of claims 1 to 7, characterized in that: The sub-pixel further includes a pixel electrode and a common electrode; The light-shielding conductive layer includes a first sublayer, and the first sublayer also includes a pixel electrode pattern; The gate layer further comprises a common electrode pattern and a common signal line, the material of the common electrode pattern is a transparent conductive material, and the common signal line is connected to the common electrode pattern; The pixel electrode pattern overlaps with the common signal line.

9. The array substrate according to claim 8, characterized in that: The gate layer includes a gate line, and the gate pattern of the first transistor is a portion of the gate line that overlaps with the active layer pattern of the first transistor; The second pattern is connected to the gate line.

10. The array substrate according to claim 9, characterized in that: The array substrate comprises a gate driving circuit, wherein the gate driving circuit comprises at least one second transistor and a storage capacitor; The gate layer further includes a gate control line, and the gate control line includes a gate pattern of the second transistor; The active layer further includes an active layer pattern of a second transistor; The array substrate further comprises a source-drain metal layer disposed on a side of the active layer away from the base substrate, the source-drain metal layer is in contact with the active layer, and the source-drain metal layer comprises a first electrode pattern of a storage capacitor; The light shielding conductive layer further comprises a conductive pattern, the conductive pattern overlaps with the active layer pattern of the second transistor and also overlaps with the first plate pattern of the storage capacitor; the conductive pattern is connected to the gate control line; The gate control line overlaps with the first plate pattern of the storage capacitor.

11. The array substrate according to claim 10, characterized in that: A distance between the first plate pattern of the storage capacitor and the conductive pattern is equal to a distance between the first plate pattern of the storage capacitor and the gate control line.

12. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 11.

13. The display panel according to claim 12, characterized in that: The display panel further includes: A color filter substrate disposed on the array substrate; At least one spacer is disposed between the array substrate and the color filter substrate; the spacer includes a first spacer, and the first spacer is disposed on one side of the second pattern and contacts the second pattern.

14. The display panel according to claim 13, characterized in that: The spacers include second spacers, the height of the first spacers is higher than the height of the second spacers; and the second spacers are arranged on one side of the second pattern.

15. A display device, characterized in that: include: The display panel according to any one of claims 12 to 14, comprising a display side and a non-display side; A backlight module is arranged on the non-display side of the display panel, and is used to provide a backlight source.

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