Transconductance parameter testing device
By introducing current sampling and driver unit feedback loops into the transconductance parameter test device, the current oscillation problem caused by G-pole grounding in traditional tests is solved, and safety and stability are improved, the test device is simplified and the cost is reduced.
Patent Information
- Application Number
- CN202422021448.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-08-19
AI Technical Summary
In traditional transconductance parameter testing circuits, the G-pole of the field effect tube is grounded, which can easily lead to excessive pressure difference between the G-pole and S-pole, resulting in large current oscillation, resulting in damage to the field effect tube and even the test equipment, and low test safety.
The feedback loop is formed by a voltage source, sampling resistor, current sampling unit and driving unit. The voltage of the third electrode of the device to be tested is adjusted through current sampling to avoid excessive pressure difference between the second electrode and the third electrode of the device to be tested, and negative feedback is formed to stabilize the voltage difference.
It improves the safety of transconductance parameter testing, avoids large current oscillation, simplifies the structure of the test device, reduces the cost of VI source, and improves the stability of the test.
Smart Images
Figure CN223051452U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor testing technologies, and particularly to a transconductance parameter testing device. Background Art
[0002] Transconductance is an important parameter of a field effect transistor, and its magnitude represents the control strength of VGS (the voltage between the gate G and the source S of the field effect transistor) over IDS (the current passing between the drain D and the source S of the field effect transistor). Transconductance has always been one of the key attributes of the field effect transistor and has attracted much attention from design engineers and test engineers.
[0003] A traditional transconductance parameter testing circuit includes a drain voltage source, a source current source, and a common-ground voltage measurement unit. The gate G of the field effect transistor is grounded, the drain voltage source and the source current source are respectively connected to the drain D and the source S of the field effect transistor, a voltage and a current are applied between the drain D and the source S, and the common-ground voltage measurement unit measures the voltage of the source S with respect to the ground. The transconductance parameter of the field effect transistor is calculated based on the collected data. Since the gate G is grounded during testing, it is easy to cause an excessive voltage difference between the gate G and the source S, resulting in large current oscillations, which may damage the field effect transistor or even the testing equipment, and there is a disadvantage of low testing safety. Utility Model Content
[0004] Based on this, it is necessary to provide a transconductance parameter testing device that can improve testing safety for the above problems.
[0005] A transconductance parameter testing device includes:
[0006] A voltage source, the first end of which is connected to the first pole of the device under test, and the second end of which is grounded;
[0007] A sampling resistor, the first end of which is connected to the second pole of the device under test, and the second end of which is grounded;
[0008] A current sampling unit, connected to the first end and the second end of the sampling resistor;
[0009] A driving unit, connected to the third pole of the device under test and the current sampling unit; the current sampling unit and the driving unit form a feedback between the second pole and the third pole of the device under test;
[0010] Wherein, the first pole and the second pole of the device under test are the output poles of the device under test, the third pole of the device under test is the input pole of the device under test, and the voltage difference between the third pole and the second pole of the device under test determines the output characteristics between the first pole and the second pole of the device under test.
[0011] In one embodiment, the voltage source is a DC VI source with inductive remote voltage compensation. The positive output terminal of the voltage source is connected to the first pole of the device under test, the negative output terminal of the voltage source is grounded, and the two feedback terminals of the voltage source are respectively connected to the first pole and the second pole of the device under test.
[0012] In one embodiment, the driving unit includes an error amplification circuit, an integration circuit, and a first driving circuit. The error amplification circuit is connected to the current sampling unit and the integration circuit. The integration circuit is connected to the first driving circuit, and the first driving circuit is connected to the third pole of the device under test;
[0013] The error amplification circuit compares the current sampling signal output by the current sampling unit with the current setting signal, amplifies the obtained signal error, and then outputs it to the integration circuit. The integration circuit processes the received signal and then outputs it to the first driving circuit.
[0014] In one embodiment, the error amplification circuit is an adder circuit. The adder circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, and an operational amplifier U1. The first terminal of the resistor R1 is connected to the current setting signal, the second terminal of the resistor R1 is connected to the first input terminal of the operational amplifier U1. The first terminal of the resistor R2 is connected to the current sampling unit and receives the current sampling signal with a phase opposite to that of the current setting signal. The second terminal of the resistor R2 is connected to the first terminal of the resistor R3, the second terminal of the resistor R3 is connected to the output terminal of the operational amplifier U1, the second input terminal of the operational amplifier U1 is grounded, the output terminal of the operational amplifier U1 is connected to the first terminal of the resistor R4, and the second terminal of the resistor R4 is connected to the integration circuit.
[0015] In one embodiment, the integration circuit includes a resistor R5, a capacitor C1, and an operational amplifier U2. The first input terminal of the operational amplifier U2 is connected to the error amplification circuit and the first terminal of the capacitor C1. The second input terminal of the operational amplifier U2 is grounded. The second terminal of the capacitor C1 is connected to the output terminal of the operational amplifier U2. The output terminal of the operational amplifier U2 is connected to the first terminal of the resistor R5, and the second terminal of the resistor R5 is connected to the first driving circuit.
[0016] In one embodiment, the first driving circuit includes a transistor Q1, a transistor Q2, and a resistor R6. The control terminals of the transistor Q1 and the transistor Q2 are both connected to the integrating circuit. The first terminal of the transistor Q1 is connected to the positive power supply terminal. The second terminal of the transistor Q1 is connected to the first terminal of the transistor Q2 and the first terminal of the resistor R6. The second terminal of the transistor Q2 is connected to the negative power supply terminal. The second terminal of the resistor R6 is connected to the third pole of the device under test.
[0017] In one embodiment, the driving unit includes an analog-to-digital converter, a processor, a digital-to-analog converter, and a second driving circuit. The analog-to-digital converter is connected to the current sampling unit and the processor. The processor is connected to the digital-to-analog converter. The digital-to-analog converter is connected to the second driving circuit. The second driving circuit is connected to the third pole of the device under test;
[0018] The analog-to-digital converter performs analog-to-digital conversion on the current sampling signal output by the current sampling unit to obtain a digital signal and sends it to the processor. The processor processes the digital signal and the current setting signal and then outputs them to the digital-to-analog converter. The digital-to-analog converter performs digital-to-analog conversion on the received signal and outputs an analog signal to the second driving circuit.
[0019] In one embodiment, the driving unit further includes a follower and an amplifying circuit. The analog-to-digital converter is connected to the current sampling unit through the follower. The digital-to-analog converter is connected to the second driving circuit through the amplifying circuit.
[0020] In one embodiment, the amplifying circuit includes a resistor R7, a resistor R8, a resistor R9, and an operational amplifier U7. The first terminal of the resistor R7 is connected to the digital-to-analog converter. The second terminal of the resistor R7 is connected to the first terminal of the resistor R8 and the first input terminal of the operational amplifier U7. The second input terminal of the operational amplifier U7 is grounded. The second terminal of the resistor R8 is connected to the output terminal of the operational amplifier U7. The output terminal of the operational amplifier U7 is connected to the first terminal of the resistor R9. The second terminal of the resistor R9 is connected to the second driving circuit.
[0021] In one embodiment, the second driving circuit includes a transistor Q3, a transistor Q4, and a resistor R10. The control terminals of the transistor Q3 and the transistor Q4 are both connected to the amplifying circuit. The first terminal of the transistor Q3 is connected to the positive power supply terminal. The second terminal of the transistor Q3 is connected to the first terminal of the transistor Q4 and the first terminal of the resistor R10. The second terminal of the transistor Q4 is connected to the negative power supply terminal. The second terminal of the resistor R10 is connected to the third pole of the device under test.
[0022] In the above transconductance parameter testing device, a voltage source is connected to the first pole of the device under test, a sampling resistor is connected to the second pole of the device under test, and feedback between the second pole and the third pole of the device under test is formed through a current sampling unit and a driving unit. The current of the second pole of the device under test is sampled as feedback to adjust the voltage of the third pole of the device under test, avoiding large current oscillations caused by excessive voltage difference between the second pole and the third pole of the device under test, and improving the safety of transconductance parameter testing. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 is a structural block diagram of a transconductance parameter testing device in an embodiment;
[0024] Figure 2 is a structural block diagram of a driving unit in an embodiment;
[0025] Figure 3 is a structural schematic diagram of a driving unit in an embodiment;
[0026] Figure 4 is a structural schematic diagram of a driving unit in another embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0027] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application. It can be understood that "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is an electrical signal or data transmission between the connected circuits, modules, units, etc.
[0029] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / have" etc. specify the presence of the stated features, wholes, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the related listed items.
[0030] In a traditional transconductance parameter test circuit, since the G pole of the field effect transistor is grounded during testing and has no direct connection with the S pole, when an abnormality occurs, such as a break in the loop of the current source feedback, a change in the S pole voltage will not be fed back to the G pole, easily resulting in an excessive voltage difference between the G pole and the S pole. In severe cases, the field effect transistor is fully turned on, and under the combined action of the D pole voltage source and the S pole current source, large current oscillations will occur, leading to damage to the field effect transistor and even the test equipment. Based on this, a transconductance parameter test device provided in this application connects a voltage source to the first pole of the device under test, connects a sampling resistor to the second pole of the device under test, and forms a feedback between the second pole and the third pole of the device under test through a current sampling unit and a driving unit. The current sampling of the second pole of the device under test is used as feedback to adjust the voltage of the third pole of the device under test, avoiding large current oscillations caused by an excessive voltage difference between the second pole and the third pole of the device under test.
[0031] In one embodiment, as Figure 1 shown, a transconductance parameter test device is provided, including a voltage source 110, a sampling resistor Rs, a current sampling unit 120, and a driving unit 130. The first end of the voltage source 110 is connected to the first pole of the device under test DUT, the second end of the voltage source 110 is grounded, the first end of the sampling resistor Rs is connected to the second pole of the device under test DUT, and the second end of the sampling resistor R S s is grounded. The current sampling unit 120 is connected to the first end and the second end of the sampling resistor Rs, the driving unit 130 is connected to the third pole of the device under test DUT and the current sampling unit 120, and the current sampling unit 120 and the driving unit 130 form a feedback between the second pole and the third pole of the device under test DUT.
[0032] Among them, the first pole and the second pole of the device under test DUT are the output poles of the device under test DUT, the third pole of the device under test DUT is the input pole of the device under test DUT, and the voltage difference between the third pole and the second pole of the device under test DUT determines the output characteristics between the first pole and the second pole of the device under test DUT. The device under test DUT can specifically be a voltage-controlled device such as a metal-oxide-semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). When the device under test DUT is a MOSFET, the first pole is the drain (D pole) of the MOSFET, the second pole is the source (S pole) of the MOSFET, and the third pole is the gate (G pole) of the MOSFET; when the device under test DUT is an IGBT, the first pole is the collector (C pole) of the IGBT, the second pole is the emitter (E pole) of the IGBT, and the third pole is the gate (G pole) of the IGBT.
[0033] The voltage source 110 may specifically adopt a VI (voltage-current) source. Only one VI source is needed for the transconductance parameter test, which simplifies the structure of the test device. Moreover, since the VI source only needs to output voltage externally, a single-quadrant VI source can meet the test requirements, reducing the cost of the VI source. Especially in the design of a high-current VI source, the selection of power amplifier transistors required inside the VI source can be simplified. Considering that the current-carrying capacity of N-channel power amplifier transistors is much higher than that of P-channel power amplifier transistors, the single-quadrant VI source can be constructed based on N-channel power amplifier transistors, which simplifies the VI source design. Further, in this embodiment, the voltage source 110 is a DC VI source with Sense (inductive) remote voltage compensation. The positive output terminal of the voltage source 110 is connected to the first pole of the device under test (DUT), the negative output terminal of the voltage source 110 is grounded, and the two feedback terminals of the voltage source 110 are respectively connected to the first pole and the second pole of the DUT, which can keep the voltage difference between the connected positions of the feedback terminals fixed, cancel the voltage drop loss generated by the current flowing through the circuit, and thus keep the voltage across the DUT stable.
[0034] The sampling resistor Rs is used to detect the current in the loop where it is located and convert the current signal into a voltage signal. The sampling resistor Rs can be an independent device or integrated into the voltage source 110 or other devices. The current sampling unit 120 serves as the input stage of the feedback link and is used to capture and convert the voltage signal across the sampling resistor Rs, and output a current sampling signal to the driving unit 130. The current sampling unit 120 can be an independent device or integrated into the voltage source 110 or other devices. The driving unit 130 serves as the output stage of the feedback link. After receiving the current sampling signal output by the current sampling unit 120 and performing signal processing, it outputs a voltage to the third pole of the DUT to adjust the voltage of the third pole.
[0035] In addition, the transconductance parameter test device further includes a differential voltage measurement unit 140. The differential voltage measurement unit 140 is connected to the second pole and the third pole of the DUT and is used to detect the voltage between the second pole and the third pole of the DUT.
[0036] It can be understood that the specific structure of the driving unit 130 is not unique. In one embodiment, such as Figure 2As shown, the driving unit 130 includes an error amplification circuit 131, an integration circuit 132, and a first driving circuit 133. The error amplification circuit 131 is connected to the current sampling unit 120 and the integration circuit 132. The integration circuit 132 is connected to the first driving circuit 133. The first driving circuit 133 is connected to the third pole of the device under test (DUT). The error amplification circuit 131 compares the current sampling signal output by the current sampling unit 120 with the current setting signal, amplifies the obtained signal error, and then outputs it to the integration circuit 132. The integration circuit 132 processes the received signal and then outputs it to the first driving circuit 133. In the driving unit 130, the input current sampling signal is compared with the current setting signal to obtain the signal error between the two. After the signal error is amplified and integrated, it is output by the first driving circuit 133 to the third pole of the device under test (DUT) to achieve negative feedback regulation.
[0037] Among them, according to the different phase relationships between the current sampling signal and the current setting signal, the way the error amplification circuit 131 calculates the signal error will also be correspondingly different. When the phases of the current sampling signal and the current setting signal are the same, the error amplification circuit 131 subtracts the two signals to calculate the signal error. When the phases of the current sampling signal and the current setting signal are opposite, the error amplification circuit 131 adds the two signals to calculate the signal error.
[0038] In one embodiment, the error amplification circuit 131 is an adder circuit. As Figure 3 shown, the adder circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, and an operational amplifier U1. The first end of the resistor R1 is connected to the current setting signal, the second end of the resistor R1 is connected to the first input terminal of the operational amplifier U1. The first end of the resistor R2 is connected to the current sampling unit 120, and the current sampling signal with a phase opposite to that of the current setting signal is connected. The second end of the resistor R2 is connected to the first end of the resistor R3. The second end of the resistor R3 is connected to the output terminal of the operational amplifier U1. The second input terminal of the operational amplifier U1 is grounded. The output terminal of the operational amplifier U1 is connected to the first end of the resistor R4. The second end of the resistor R4 is connected to the integration circuit 132. When the phases of the current sampling signal output by the current sampling unit 120 and the current setting signal are opposite, the two are summed and amplified through the adder circuit constructed by the operational amplifier, and then sent to the integration circuit 132 for integration operation.
[0039] Furthermore, the integration circuit 132 can also be constructed by using an operational amplifier. Continuing to refer to Figure 3, the integrating circuit 132 includes a resistor R5, a capacitor C1, and an operational amplifier U2. The first input terminal of the operational amplifier U2 is connected to the error amplification circuit 131 and the first terminal of the capacitor C1, specifically connected to the second terminal of the resistor R4 in the error amplification circuit 131. The second input terminal of the operational amplifier U2 is grounded. The second terminal of the capacitor C1 is connected to the output terminal of the operational amplifier U2. The output terminal of the operational amplifier U2 is connected to the first terminal of the resistor R5. The second terminal of the resistor R5 is connected to the first driving circuit 133. After the signal output by the error amplification circuit 131 is subjected to an integration operation by the integrating circuit 132 constructed by the operational amplifier, it is delivered to the third pole of the device under test DUT by the first driving circuit 133.
[0040] In one embodiment, the first driving circuit 133 includes a transistor Q1, a transistor Q2, and a resistor R6. The control terminals of the transistor Q1 and the transistor Q2 are both connected to the integrating circuit 132, specifically connected to the second terminal of the resistor R5 in the integrating circuit 132. The first terminal of the transistor Q1 is connected to the positive power supply terminal VCC. The second terminal of the transistor Q1 is connected to the first terminal of the transistor Q2 and the first terminal of the resistor R6. The second terminal of the transistor Q2 is connected to the negative power supply terminal VEE. The second terminal of the resistor R6 is connected to the third pole of the device under test DUT. Among them, the transistor Q1 and the transistor Q2 can be triodes, etc., for enhancing the driving ability.
[0041] Taking the device under test DUT as an enhancement-mode NMOS as an example, the greater the voltage difference between the third pole and the second pole, the greater the current between the first pole and the second pole. The current flowing through the sampling resistor Rs is a positive current, that is, the current sampling signal is positive, then the current setting signal is set to negative. The negative feedback formation method of the driving unit 130 is as follows: if the current sampling signal is greater than the current setting signal, that is, the actual current exceeds the set target value, then the integration input is positive, the integration output voltage drops, the voltage difference between the third pole and the second pole of the device under test DUT decreases, and the current between the first pole and the second pole decreases; conversely, if the actual current is less than the set target value, the voltage difference between the third pole and the second pole of the device under test DUT increases, and the current between the first pole and the second pole increases; when the summation result of the current sampling signal and the current setting signal is zero, that is, the actual current is equal to the set target value, then the integration circuit input is zero, the integration output is stable, the voltage difference between the third pole and the second pole of the device under test DUT is stable, and the current passing through the first pole and the second pole is stable.
[0042] It can be understood that in other embodiments, the structure of the driving unit 130 can also be constructed by processors such as FPGA (Field-Programmable Gate Array), embedded chips, etc.
[0043] Specifically, such as Figure 4As shown, the driving unit 130 may include an analog-to-digital converter U4, a processor U5, a digital-to-analog converter U6, and a second driving circuit 135. The analog-to-digital converter U4 is connected to the current sampling unit 120 and the processor U5. The processor U5 is connected to the digital-to-analog converter U6. The digital-to-analog converter U6 is connected to the second driving circuit 135. The second driving circuit 135 is connected to the third pole of the device under test DUT. Among them, the processor U5 may be a functional chip such as an FPGA, an MCU (Microcontroller Unit), or a CPU (Central Processing Unit). The analog-to-digital converter U4 performs analog-to-digital conversion on the current sampling signal output by the current sampling unit 120, obtains a digital signal and sends it to the processor U5. The processor U5 processes the digital signal and the current setting signal and then outputs them to the digital-to-analog converter U6. The digital-to-analog converter U6 performs digital-to-analog conversion on the received signal and outputs an analog signal to the second driving circuit 135. In addition, the driving unit 130 may further include a follower U3 and an amplifier circuit 134. The analog-to-digital converter U4 is connected to the current sampling unit 120 through the follower U3, and the digital-to-analog converter U6 is connected to the second driving circuit 135 through the amplifier circuit 134.
[0044] The current sampling signal output by the current sampling unit 120 enters the analog-to-digital converter U4 through the follower U3, is converted into a digital signal recognizable by the processor algorithm program, and then sent to the processor U5. In the processor U5, the digital signal and the current setting signal are subjected to error comparison, amplification, integration, and other processes. The processing result is output as a digital signal to the digital-to-analog converter U6. The analog signal output by the digital-to-analog converter U6 is amplified by the amplifier circuit 134 to the actual required voltage range and then output by the second driving circuit 135 to the third pole of the device under test DUT. Among them, the follower U3 may also use an operational amplifier. The first input terminal of the follower U3 is connected to the current sampling unit 120 to access the current sampling signal. The second input terminal of the follower U3 is connected to the output terminal of the follower U3, and the output terminal of the follower U3 is connected to the analog-to-digital converter U4.
[0045] In one embodiment, as Figure 4 shown, the amplifier circuit 134 includes a resistor R7, a resistor R8, a resistor R9, and an operational amplifier U7. The first end of the resistor R7 is connected to the digital-to-analog converter U6. The second end of the resistor R7 is connected to the first end of the resistor R8 and the first input terminal of the operational amplifier U7. The second input terminal of the operational amplifier U7 is grounded. The second end of the resistor R8 is connected to the output terminal of the operational amplifier U7. The output terminal of the operational amplifier U7 is connected to the first end of the resistor R9. The second end of the resistor R9 is connected to the second driving circuit 135.
[0046] Further, the second driving circuit 135 may include a transistor Q3, a transistor Q4, and a resistor R10. The control terminals of the transistor Q3 and the transistor Q4 are both connected to the amplifying circuit 134, specifically connected to the second terminal of the resistor R9 in the amplifying circuit 134. The first terminal of the transistor Q3 is connected to the positive power supply terminal VCC. The second terminal of the transistor Q3 is connected to the first terminal of the transistor Q4 and the first terminal of the resistor R10. The second terminal of the transistor Q4 is connected to the negative power supply terminal VEE. The second terminal of the resistor R10 is connected to the third pole of the device under test DUT. Wherein, the transistor Q3 and the transistor Q4 may be triodes, etc., for enhancing the driving ability.
[0047] Taking the NMOS as an example of the device under test, its transconductance measurement method is as follows:
[0048] In the first step, the voltage source 110 outputs a voltage V DS , and applies the voltage required to test the first pole and the second pole;
[0049] In the second step, a current setting I DS1 is set, and the driving unit 130 sets the first current value required to pass through the first pole and the second pole for the test;
[0050] In the third step, the voltage value V GS1 of the differential measurement unit 140 is obtained, and the voltage value between the third pole and the second pole of the device under test DUT under the conditions of the first step and the second step is obtained;
[0051] In the fourth step, a current setting I DS2 is set, and the driving unit 130 sets the second current value required to pass through the first pole and the second pole for the test;
[0052] In the fifth step, the voltage value V GS2 of the differential measurement unit 140 is obtained, and the voltage value between the third pole and the second pole of the device under test DUT under the conditions of the third step and the fourth step is obtained;
[0053] In the sixth step, the transconductance is calculated. Based on I DS1 , I DS2 , V GS1 , V GS2 the difference ΔI DS and the difference ΔV GS are calculated, and then the transconductance parameter of the device under test DUT is obtained: g fs =ΔI DS / ΔV GS .
[0054] In addition, the transconductance parameter test device may further include a controller. The controller is connected to the voltage source 110 and the driving unit 130. The controller is used to send a voltage setting signal to the voltage source 110 to adjust the output voltage of the voltage source 110, and send a current setting signal to the driving unit 130 for current setting.
[0055] The above transconductance parameter test device forms a feedback between the second and third poles of the device under test (DUT) through the current sampling unit 120 and the driving unit 130, samples the current at the second pole of the DUT as feedback to adjust the voltage at the third pole of the DUT, and avoids large current oscillations caused by excessive voltage difference between the second and third poles of the DUT.
[0056] This transconductance parameter test device only requires one VI source for transconductance testing, which simplifies the hardware structure. Compared with the scheme where the voltage at the third pole is obtained by integrating the voltage feedback from the second pole, it is not necessary for the voltage across the current source to be zero at steady state, so a four-quadrant VI source is not required. The VI source only needs to output voltage externally, so a single-quadrant VI source can meet the requirements, reducing the cost of the VI source. Especially in the design of a large-current VI source, the current capacity of N-channel power amplifier transistors is much higher than that of P-channel power amplifier transistors. The single-quadrant VI source can be constructed based on N-channel power amplifier transistors, which simplifies the design of the VI source. At the same time, the number of feedback loops of the entire device is also reduced (from three loops including the voltage loop of the voltage source, the current loop of the current source, and the integration loop of the third pole of the DUT to two loops). It can be understood that all loops work together to achieve overall constant voltage and constant current, and it is required that the parameters of the three loops match. Otherwise, it is very easy to cause oscillations, especially when the current is large. Affected by the parasitic parameters of the link, the system waveform is difficult to stabilize. The reduction of the loops can improve the stability of transconductance testing.
[0057] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered that the scope described in this specification is covered.
[0058] The above embodiments only represent several implementation manners of the present application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A transconductance parameter testing device, characterized in that: include: A voltage source, a first end of the voltage source is connected to a first electrode of the device under test, and a second end of the voltage source is grounded; A sampling resistor, wherein a first end of the sampling resistor is connected to a second electrode of the device under test, and a second end of the sampling resistor is grounded; A current sampling unit, connected to the first end and the second end of the sampling resistor; A driving unit connected to the third pole of the device under test and the current sampling unit; the current sampling unit and the driving unit constitute feedback between the second pole and the third pole of the device under test; Among them, the first and second poles of the device under test are the output poles of the device under test, the third pole of the device under test is the input pole of the device under test, and the voltage difference between the third pole and the second pole of the device under test determines the output characteristics between the first pole and the second pole of the device under test.
2. The transconductance parameter testing device according to claim 1, characterized in that: The voltage source is a DC VI source with inductive remote voltage compensation, the positive output electrode of the voltage source is connected to the first electrode of the device under test, the negative output electrode of the voltage source is grounded, and the two feedback ends of the voltage source are respectively connected to the first electrode and the second electrode of the device under test.
3. The transconductance parameter testing device according to claim 1, characterized in that: The driving unit comprises an error amplifying circuit, an integrating circuit and a first driving circuit, the error amplifying circuit is connected to the current sampling unit and the integrating circuit, the integrating circuit is connected to the first driving circuit, and the first driving circuit is connected to the third electrode of the device under test; The error amplifier circuit compares the current sampling signal output by the current sampling unit with the current setting signal, amplifies the obtained signal error and outputs it to the integration circuit, and the integration circuit processes the received signal and outputs it to the first drive circuit.
4. The transconductance parameter testing device according to claim 3, characterized in that: The error amplifier circuit is an adder circuit; the adder circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4 and an operational amplifier U1, the first end of the resistor R1 is connected to the current setting signal, the second end of the resistor R1 is connected to the first input end of the operational amplifier U1, the first end of the resistor R2 is connected to the current sampling unit, and is connected to the current sampling signal with a phase opposite to that of the current setting signal, the second end of the resistor R2 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the output end of the operational amplifier U1, the second input end of the operational amplifier U1 is grounded, the output end of the operational amplifier U1 is connected to the first end of the resistor R4, and the second end of the resistor R4 is connected to the integration circuit.
5. The transconductance parameter testing device according to claim 3, characterized in that: The integration circuit includes a resistor R5, a capacitor C1 and an operational amplifier U2, wherein a first input terminal of the operational amplifier U2 is connected to the error amplifier circuit and a first end of the capacitor C1, a second input terminal of the operational amplifier U2 is grounded, a second end of the capacitor C1 is connected to an output terminal of the operational amplifier U2, an output terminal of the operational amplifier U2 is connected to a first end of the resistor R5, and a second end of the resistor R5 is connected to the first drive circuit.
6. The transconductance parameter testing device according to claim 3, characterized in that: The first driving circuit includes a transistor Q1, a transistor Q2 and a resistor R6, the control end of the transistor Q1 and the control end of the transistor Q2 are both connected to the integration circuit, the first end of the transistor Q1 is connected to the positive power supply end, the second end of the transistor Q1 is connected to the first end of the transistor Q2 and the first end of the resistor R6, the second end of the transistor Q2 is connected to the negative power supply end, and the second end of the resistor R6 is connected to the third electrode of the device under test.
7. The transconductance parameter testing device according to claim 1, characterized in that: The driving unit comprises an analog-to-digital converter, a processor, a digital-to-analog converter and a second driving circuit, the analog-to-digital converter is connected to the current sampling unit and the processor, the processor is connected to the digital-to-analog converter, the digital-to-analog converter is connected to the second driving circuit, and the second driving circuit is connected to the third pole of the device under test; The analog-to-digital converter performs analog-to-digital conversion on the current sampling signal output by the current sampling unit, obtains a digital signal and sends it to the processor. The processor processes the digital signal and the current setting signal and outputs them to the digital-to-analog converter. The digital-to-analog converter performs digital-to-analog conversion on the received signal and outputs an analog signal to the second drive circuit.
8. The transconductance parameter testing device according to claim 7, characterized in that: The driving unit further includes a follower and an amplifier circuit, the analog-to-digital converter is connected to the current sampling unit via the follower, and the digital-to-analog converter is connected to the second driving circuit via the amplifier circuit.
9. The transconductance parameter testing device according to claim 8, characterized in that: The amplification circuit includes resistors R7, R8, R9 and an operational amplifier U7, wherein a first end of the resistor R7 is connected to the digital-to-analog converter, a second end of the resistor R7 is connected to a first end of the resistor R8 and a first input end of the operational amplifier U7, a second input end of the operational amplifier U7 is grounded, a second end of the resistor R8 is connected to an output end of the operational amplifier U7, an output end of the operational amplifier U7 is connected to a first end of the resistor R9, and a second end of the resistor R9 is connected to the second drive circuit.
10. The transconductance parameter testing device according to claim 8, characterized in that: The second driving circuit includes a transistor Q3, a transistor Q4 and a resistor R10, the control end of the transistor Q3 and the control end of the transistor Q4 are both connected to the amplifier circuit, the first end of the transistor Q3 is connected to the positive power supply end, the second end of the transistor Q3 is connected to the first end of the transistor Q4 and the first end of the resistor R10, the second end of the transistor Q4 is connected to the negative power supply end, and the second end of the resistor R10 is connected to the third electrode of the device under test.