Digital audio switcher with controllable output sampling rate

Abstract

The utility model discloses a digital audio switcher with a controllable output sampling rate, which comprises a digital audio receiving module, a digital audio sampling rate conversion module, a gating module, an external synchronous clock module, a clock switching module, a digital audio transmitting module and an MCU (Microprogrammed Control Unit) module, the digital audio sampling rate conversion module is connected with the gating module and the digital audio receiving module, the gating module is connected with the clock switching module through an internal clock signal, the external synchronous clock module is connected with the clock switching module through an external synchronous clock signal, and the clock switching module is connected with the digital audio sending module through a clock signal. The gating module is connected with the digital audio sending module through audio signals, and the MCU module is connected with the gating module and the clock switching module through control signals. According to the scheme, the sampling rate of the output signal can be adjusted as required, and subsequent equipment can be directly adapted.

Description

Technical Field

[0001] The utility model relates to the field of digital audio transmission, and in particular to a digital audio switch with a controllable output sampling rate. Background Art

[0002] An audio switch can transmit multiple audio input signals to an output port. In the case of multiple input signals, any one of the input signals can be switched to the output port. In the digital audio industry, the common practice is to directly perform SRC sampling rate conversion on the input digital audio at the input end, convert it to a unified sampling rate within the system, and then perform processing or re-output. However, for a switch with multiple audio sources input, the switched output digital audio may need to be adapted to different sampling rates due to the interface requirements of the subsequent device. Therefore, there is also a need to control the sampling rate of the digital audio switched by the switch. Summary of the Invention

[0003] The utility model mainly solves the technical problem existing in the prior art that only a single sampling rate can be output, and provides a digital audio switch with a controllable output sampling rate.

[0004] The utility model mainly solves the above technical problems through the following technical solutions: A digital audio switch with a controllable output sampling rate includes a digital audio receiving module, a digital audio sampling rate conversion module, a gating module, an external synchronous clock module, a clock switching module, a digital audio transmitting module, and an MCU module. There are several digital audio receiving modules and digital audio sampling rate conversion modules that correspond one by one. The digital audio receiving module is connected to the clock switching module through an audio clock signal, the digital audio receiving module is connected to the digital audio sampling rate conversion module through an I2S audio signal, the digital audio sampling rate conversion module is connected to the gating module through an I2S audio signal, the gating module is connected to the clock switching module through an internal clock signal, the external synchronous clock module is connected to the clock switching module through an external synchronous clock signal, the clock switching module is connected to the digital audio transmitting module through a clock signal, the gating module is connected to the digital audio transmitting module through an audio signal, and the MCU module is connected to the gating module and the clock switching module through a control signal.

[0005] Preferably, there are five digital audio receiving modules and five digital audio sampling rate conversion modules.

[0006] Preferably, each digital audio receiving module includes a digital audio receiver, which is a CS8416 chip. The 4th and 5th pins of the digital audio receiver are connected to the input AES audio signal. The 26th pin of the digital audio receiver outputs the I2S audio signal to the digital audio sampling rate conversion module. The 24th, 27th, and 28th pins of the digital audio receiver output the clock signal parsed from the AES audio signal to the clock switching module.

[0007] Each digital audio receiving module receives one digital audio sound source and sends the clock signal parsed from the sound source to the gating module. This solution can connect up to five AES input sound sources simultaneously. The digital audio receiving module also sends the received audio signal to the digital audio sampling rate conversion module.

[0008] Preferably, each digital audio sampling rate conversion module includes a digital audio sampling rate converter, which is a CS8421 chip. The 9th pin of the digital audio sampling rate converter is connected to the 26th pin of the digital audio receiver. The 12th pin of the digital audio sampling rate converter outputs the I2S audio signal with a sampling rate of 48KHz to the gating module.

[0009] The digital audio sampling rate conversion module converts the received audio signal to a sampling rate of 48KHz and then sends it to the gating module.

[0010] Preferably, the gating module includes a CPLD chip, which is an XC95144XL chip. The 69th, 70th, 71st, 74th, and 75th pins of the CPLD chip are each connected to the 12th pin of a digital audio sampling rate converter. The 85th, 86th, and 88th pins of the CPLD chip output the internal clock signal to the clock switching module. The 83rd pin of the CPLD chip outputs the audio signal to the digital audio sending module. The 44th, 45th, 46th, 48th, 49th, 50th, 51st, 52nd, and 53rd pins of the CPLD are connected to the MCU module. The 91st, 92nd, 140th, 142nd, and 143rd pins of the CPLD chip are also connected to the keys.

[0011] The gating module receives five audio signals and, under the control of the MCU and the keys, selects one audio signal to be sent from the 83rd pin to the digital audio sending module. At the same time, the CPLD also outputs a 48KHz clock signal to the clock switching module.

[0012] Preferably, the clock switching module includes three multiplexers, and the multiplexer is an HCF4051 chip. The 13th pins of the three multiplexers are connected to the clock signal output by the first digital audio receiving module, the 14th pins of the three multiplexers are connected to the clock signal output by the second digital audio receiving module, the 15th pins of the three multiplexers are connected to the clock signal output by the third digital audio receiving module, the 12th pins of the three multiplexers are connected to the clock signal output by the fourth digital audio module, the 1st pins of the three multiplexers are connected to the clock signal output by the fifth digital audio receiving module, the 5th pins of the three multiplexers are connected to the external synchronous clock signal output by the external synchronous clock module, and the 2nd pins of the three multiplexers are connected to the internal clock signal output by the gating module; the 9th, 10th, and 11th pins of the three multiplexers are connected to the MCU module, and the 3rd pins of the three multiplexers output the selected clock signal to the digital audio - transmitting module through a buffer.

[0013] The clock switching module receives a variety of different clock signals and outputs a selected clock signal to the digital audio transmitting module under the control of the MCU control signal.

[0014] Preferably, the external synchronous clock module includes a clock signal receiving chip, and the clock signal receiving chip is a CS8416 chip. The 4th and 5th pins of the clock signal receiving chip are connected to the external clock signal input terminal, and the 24th, 27th, and 28th pins of the clock signal receiving chip output the external synchronous clock signal to the clock switching module.

[0015] As needed, an external clock signal can be input separately in the AES / EBU mode, and the I2S clock signal is parsed by the external synchronous clock module and sent to the clock switching module for selection.

[0016] Preferably, the digital audio transmitting module includes a digital audio transmitter, and the digital audio transmitter is a CS8420 chip. The 16th, 17th, and 21st pins of the digital audio transmitter receive the clock signal from the clock switching module, the 14th pin of the digital audio transmitter receives the audio signal from the gating module, and the 25th and 26th pins of the digital audio transmitter output the audio signal converted to the selected clock frequency through an isolation transformer.

[0017] The CS8420 chip receives the clock signal from the clock switching module and outputs the audio signal after converting it to this sampling rate.

[0018] The beneficial effects brought by the present utility model are that the sampling rate of the output signal can be adjusted according to needs to directly adapt to the subsequent equipment. The sampling rate can be from the original sound source, external clock signal or internal clock signal, with a wide adjustable range and strong adaptability. Description of the Drawings

[0019] Figure 1 is a circuit block diagram of a digital audio switch of the present utility model;

[0020] Figure 2 is a circuit diagram of a first digital audio receiving module of the present utility model;

[0021] Figure 3 is a circuit diagram of a first digital audio sampling rate conversion module of the present utility model;

[0022] Figure 4 and Figure 5 is a circuit diagram of a gating module of the present utility model;

[0023] Figure 6 is a circuit diagram of a clock switching module of the present utility model;

[0024] Figure 7 is a circuit diagram of a digital audio transmitting module of the present utility model;

[0025] Figure 8 is a circuit diagram of an external synchronous clock module of the present utility model;

[0026] Figure 9 、 Figure 10 and Figure 11 is a circuit diagram of an MCU module of the present utility model;

[0027] In the figure: 1. Digital audio receiving module; 2. Digital audio sampling rate conversion module; 3. Gating module; 4. External synchronous clock module; 5. Clock switching module; 6. Digital audio transmitting module; 7. MCU module. Specific embodiments

[0028] The technical solution of the present utility model will be further specifically described below through embodiments in conjunction with the accompanying drawings.

[0029] Embodiment: A digital audio switch with a controllable output sampling rate in this embodiment, such as Figure 1As shown in the figure, it includes a digital audio receiving module 1, a digital audio sampling rate conversion module 2, a gating module 3, an external synchronous clock module 4, a clock switching module 5, a digital audio transmitting module 6, and an MCU module 7. There are 5 digital audio receiving modules and 5 digital audio sampling rate conversion modules, which are in one-to-one correspondence. The digital audio receiving module is connected to the clock switching module through an audio clock signal, the digital audio receiving module is connected to the digital audio sampling rate conversion module through an I2S audio signal, the digital audio sampling rate conversion module is connected to the gating module through an I2S audio signal, the gating module is connected to the clock switching module through an internal clock signal, the external synchronous clock module is connected to the clock switching module through an external synchronous clock signal, the clock switching module is connected to the digital audio transmitting module through a clock signal, the gating module is connected to the digital audio transmitting module through an audio signal, and the MCU module is connected to the gating module and the clock switching module through a control signal.

[0030] Each digital audio receiving module includes a digital audio receiver, and the digital audio receiver is a CS8416 chip. The 4th and 5th pins of the digital audio receiver are connected to the input AES audio signal, the 26th pin of the digital audio receiver outputs an I2S audio signal to the digital audio sampling rate conversion module, and the 24th, 27th, and 28th pins of the digital audio receiver output the clock signals (OMCLK1-5, OSCLK1-5, OLRCK1-5) parsed from the AES audio signal to the clock switching module. Figure 2 The circuit diagram of the first digital audio receiving module is shown. The circuits of the second to fifth digital audio receiving modules are the same as that of the first digital audio receiving module.

[0031] Each digital audio receiving module receives one digital audio sound source and sends the clock signal parsed from the sound source to the gating module. This solution can connect up to five AES input sound sources simultaneously. The digital audio receiving module also sends the received audio signal to the digital audio sampling rate conversion module.

[0032] Each digital audio sampling rate conversion module includes a digital audio sampling rate converter, and the digital audio sampling rate converter is a CS8421 chip. The 9th pin of the digital audio sampling rate converter is connected to the 26th pin of the digital audio receiver, and the 12th pin of the digital audio sampling rate converter outputs an I2S audio signal with a sampling rate of 48KHz to the gating module.

[0033] Figure 3 The circuit diagram of the first digital audio sampling rate conversion module is shown. The circuits of the second to fifth digital audio sampling rate conversion modules are the same as that of the first digital audio sampling rate conversion module. The digital audio sampling rate conversion module converts the received audio signal to a sampling rate of 48KHz and then sends it to the gating module.

[0034] AsFigure 4 and Figure 5 As shown in Figure 5 , the gating module includes a CPLD chip, which is an XC95144XL chip. Pin 69, Pin 70, Pin 71, Pin 74, and Pin 75 of the CPLD chip are each connected to Pin 12 of a digital audio sampling rate converter. Pin 85, Pin 86, and Pin 88 of the CPLD chip output internal clock signals (ADMCLK, ADSCLK, ADLRCK) to the clock switching module. Pin 83 of the CPLD chip outputs an audio signal to the digital audio transmission module. Pin 44, Pin 45, Pin 46, Pin 48, Pin 49, Pin 50, Pin 51, Pin 52, and Pin 53 of the CPLD are connected to the MCU module. Pin 91, Pin 92, Pin 140, Pin 142, and Pin 143 of the CPLD chip are also connected to keys.

[0035] The gating module receives five audio signals and, under the control of the MCU and keys, selects one audio signal to be sent from Pin 83 to the digital audio transmission module. At the same time, the CPLD also outputs a 48KHz clock signal to the clock switching module.

[0036] As Figure 6 shown in Figure 6 , the clock switching module includes three multiplexers, which are HCF4051 chips. Pin 13 of the three multiplexers is connected to the clock signal output by the first digital audio receiving module. Pin 14 of the three multiplexers is connected to the clock signal output by the second digital audio receiving module. Pin 15 of the three multiplexers is connected to the clock signal output by the third digital audio receiving module. Pin 12 of the three multiplexers is connected to the clock signal output by the fourth digital audio module. Pin 1 of the three multiplexers is connected to the clock signal output by the fifth digital audio receiving module. Pin 5 of the three multiplexers is connected to the external synchronous clock signal output by the external synchronous clock module. Pin 2 of the three multiplexers is connected to the internal clock signal output by the gating module. Pin 9, Pin 10, and Pin 11 of the three multiplexers are connected to the MCU module. Pin 3 of the three multiplexers outputs the selected clock signal to the digital audio - transmission module through a buffer.

[0037] The clock switching module receives multiple different clock signals and, under the control of the MCU control signal, outputs one selected clock signal to the digital audio transmission module.

[0038] As Figure 8 shown in Figure 8 , the external synchronous clock module includes a clock signal receiving chip, which is a CS8416 chip. Pin 4 and Pin 5 of the clock signal receiving chip are connected to the external clock signal input terminal. Pin 24, Pin 27, and Pin 28 of the clock signal receiving chip output external synchronous clock signals (SYNC_LACK, SYNC_SCLK, SYNC_MCLK) to the clock switching module.

[0039] As needed, an external clock signal can be input separately in the AES / EBU mode. The external synchronization clock module resolves the I2S clock signal and sends it to the clock switching module for selection.

[0040] As Figure 7 shown, the digital audio transmission module includes a digital audio transmitter, and the digital audio transmitter is a CS8420 chip. The 16th, 17th, and 21st pins of the digital audio transmitter receive the clock signal from the clock switching module. The 14th pin of the digital audio transmitter receives the audio signal from the gating module. The 25th and 26th pins of the digital audio transmitter output the audio signal converted to the selected clock frequency through an isolation transformer.

[0041] The CS8420 chip receives the clock signal from the clock switching module and outputs the audio signal after converting it to this sampling rate.

[0042] Figure 9 、 Figure 10 and Figure 11 are the circuit schematic diagrams of the MCU module. The MCU module includes an STM32F207 chip and realizes the control of other modules. The entire circuit is supplied with 3.3V and 5V voltages by an external power supply.

[0043] The specific embodiments described herein are merely illustrative of the spirit of the present invention. Those skilled in the art to which the present utility model pertains can make various modifications or supplements to the described specific embodiments or use similar methods for substitution, but will not deviate from the principle of the present utility model or exceed the scope defined by the appended claims.

[0044] Although terms such as clock signal, gating, and switching are used more frequently in this article, the possibility of using other terms is not excluded. These terms are used only to more conveniently describe and explain the essence of the present utility model; interpreting them as any additional limitation is contrary to the spirit of the present invention.

Claims

1. A digital audio switcher with controllable output sampling rate, characterized in that: It includes a digital audio receiving module, a digital audio sampling rate conversion module, a gating module, an external synchronous clock module, a clock switching module, a digital audio sending module and an MCU module. There are several digital audio receiving modules and digital audio sampling rate conversion modules and they correspond to each other. The digital audio receiving module is connected to the clock switching module through an audio clock signal, the digital audio receiving module is connected to the digital audio sampling rate conversion module through an I2S audio signal, the digital audio sampling rate conversion module is connected to the gating module through an I2S audio signal, the gating module is connected to the clock switching module through an internal clock signal, the external synchronous clock module is connected to the clock switching module through an external synchronous clock signal, the clock switching module is connected to the digital audio sending module through a clock signal, the gating module is connected to the digital audio sending module through an audio signal, and the MCU module is connected to the gating module and the clock switching module through a control signal.

2. The digital audio switcher with controllable output sampling rate according to claim 1, characterized in that: There are five digital audio receiving modules and five digital audio sampling rate conversion modules.

3. The digital audio switcher with controllable output sampling rate according to claim 1, characterized in that: Each digital audio receiving module includes a digital audio receiver, which is a CS8416 chip. Pins 4 and 5 of the digital audio receiver are connected to the input AES audio signal, and pin 26 of the digital audio receiver outputs the I2S audio signal to the digital audio sampling rate conversion module. Pins 24, 27 and 28 of the digital audio receiver output the clock signal parsed from the AES audio signal to the clock switching module.

4. The digital audio switcher with controllable output sampling rate according to claim 3, characterized in that: Each digital audio sampling rate conversion module includes a digital audio sampling rate converter, which is a CS8421 chip. Pin 9 of the digital audio sampling rate converter is connected to pin 26 of the digital audio receiver, and pin 12 of the digital audio sampling rate converter outputs an I2S audio signal with a sampling rate of 48KHz to the selection module.

5. The digital audio switcher with controllable output sampling rate according to claim 4, characterized in that: The gating module comprises a CPLD chip, which is an XC95144XL chip. Pins 69, 70, 71, 74 and 75 of the CPLD chip are respectively connected to pin 12 of a digital audio sampling rate converter, pins 85, 86 and 88 of the CPLD chip output an internal clock signal to a clock switching module, pin 83 of the CPLD chip outputs an audio signal to a digital audio sending module, pins 44, 45, 46, 48, 49, 50, 51, 52 and 53 of the CPLD are connected to an MCU module, and pins 91, 92, 140, 142 and 143 of the CPLD chip are also connected to a key.

6. The digital audio switcher with controllable output sampling rate according to claim 2, characterized in that: The clock switching module includes three multiplexers, the multiplexers are HCF4051 chips, the 13th pins of the three multiplexers are connected to the clock signal output by the first digital audio receiving module, the 14th pins of the three multiplexers are connected to the clock signal output by the second digital audio receiving module, the 15th pins of the three multiplexers are connected to the clock signal output by the third digital audio receiving module, the 12th pins of the three multiplexers are connected to the clock signal output by the fourth digital audio module, the 1st pins of the three multiplexers are connected to the clock signal output by the fifth digital audio receiving module, the 5th pins of the three multiplexers are connected to the external synchronous clock signal output by the external synchronous clock module, and the 2nd pins of the three multiplexers are connected to the internal clock signal output by the selection module; Pins 9, 10 and 11 of the three multiplexers are connected to the MCU module, and pins 3 of the three multiplexers output the selected clock signal through the buffer to the digital audio sending module.

7. The digital audio switcher with controllable output sampling rate according to claim 2 or 6, characterized in that: The external synchronous clock module includes a clock signal receiving chip, which is a CS8416 chip. Pins 4 and 5 of the clock signal receiving chip are connected to the external clock signal input terminal, and pins 24, 27 and 28 of the clock signal receiving chip output the external synchronous clock signal to the clock switching module.

8. The digital audio switcher with controllable output sampling rate according to claim 6, characterized in that: The digital audio sending module includes a digital audio transmitter, which is a CS8420 chip. Pins 16, 17 and 21 of the digital audio transmitter receive the clock signal of the clock switching module, pin 14 of the digital audio transmitter receives the audio signal of the selection module, and pins 25 and 26 of the digital audio transmitter convert the audio signal into the selected clock frequency and output it through an isolation transformer.

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