Synchronous rectification circuit with MOS tube driving and driving signal amplitude limiting

Abstract

The utility model discloses a synchronous rectification circuit with MOS (Metal Oxide Semiconductor) tube driving and driving signal amplitude limiting, which relates to the technical field of rectification and comprises a capacitor C1, a capacitor C2, a transformer T1, an MOS tube Q1, an MOS tube Q1, an MOS tube Q1, an MOS tube Q1, an MOS tube Q1, an MOS tube Q1 and an MOS tube Q1. The secondary end is respectively connected with the drain electrodes of the MOS tube Q2 and the MOS tube Q3 and the first end of the inductor L, the source electrode of the Q3 and the source electrode of the Q2 are connected with the negative output end of the power supply, the second end of the inductor L is connected with the positive output end of the power supply, the source electrode of the Q1 is connected with the negative input end of the power supply, the grid electrode of the Q1 and the grid electrode of the Q3 are respectively connected with a first control signal and a second control signal, and the grid electrode of the Q2 is connected with a rectification MOS tube driving circuit with a driving level amplitude limiting unit. Secondary synchronous rectification MOS tube driving based on forward topology is realized, the driving level amplitude is limited, and stable and reliable driving signals can be provided.

Description

Technical Field

[0001] The utility model relates to the technical field of rectification, and specifically, it is a synchronous rectification circuit with MOS tube drive and drive signal limiting. Background Art

[0002] Traditional rectification technology mainly relies on rectifier diodes. However, due to the relatively high forward voltage drop of rectifier diodes, especially under low-voltage and high-current operating conditions, the rectification loss becomes particularly significant. For example, the forward voltage drop of fast recovery diodes (FRD) or ultra-fast recovery diodes (SRD) can reach 1.0 - 1.2V. Even when using Schottky barrier diodes (SBD) with a low forward voltage drop, a voltage drop of approximately 0.6V will still be generated. These voltage drops not only increase the rectification loss but also reduce the overall efficiency of the power supply. To solve this problem, synchronous rectification technology emerged. This technology uses power MOSFETs with extremely low on-resistance to replace traditional rectifier diodes. The on-resistance of power MOSFETs is relatively small, usually only about 0.006V, which greatly reduces the rectification loss and improves the efficiency of the circuit. In addition, synchronous rectification technology also eliminates the dead zone voltage caused by the Schottky barrier voltage, further improving the power ratio. Whether the synchronous rectification drive circuit is reasonably designed also determines the stability of the rectification MOD tube, thus directly playing a crucial role in the reliability of the entire machine. With the introduction of synchronous rectification technology into the forward switching power supply, although the total power consumption of the circuit has decreased, the problems of synchronous rectification reliability and drive loss in the forward switching power supply have become increasingly prominent, especially for synchronous rectification circuits using traditional direct drive methods, such as Figure 1 As shown, since the drive signal of the synchronous rectification MOS tube is directly taken from the secondary winding of the transformer or through resistor-capacitor voltage reduction, as the output voltage increases or the output power increases, the drive amplitude of the synchronous rectification MOS will exceed the maximum drive voltage VGS of the MOS tube itself (the maximum allowable drive voltage of the MOS tube is generally within ±20V), which easily causes the VGS voltage of MOS tubes Q2 and Q3 to be too high and damage Q2 and Q3, resulting in a reduction in the overall reliability of the power supply. At the same time, the increase in drive loss leads to a reduction in the power supply efficiency. Summary of the Utility Model

[0003] To solve the above technical problems, the purpose of the utility model is to provide a synchronous rectification circuit with MOS tube drive and drive signal limiting to solve the problem of excessive drive amplitude of the synchronous rectification MOS tube.

[0004] The utility model solves the above problems through the following technical solutions:

[0005] A synchronous rectification circuit with MOS transistor drive and drive signal amplitude limiting, comprising a capacitor C1, a transformer T1, an inductor L, and a capacitor C2. The two ends of the capacitor C1 are respectively connected to the positive power input terminal and the negative power input terminal. The two ends of the capacitor C2 are respectively connected to the positive power output terminal and the negative power output terminal. The primary terminal of the transformer T1 is respectively connected to the positive power input terminal and the drain of the MOS transistor Q1. The secondary terminal of the transformer T1 is respectively connected to the drain of the MOS transistor Q2 and the first end of the inductor L. The first end of the inductor L is also connected to the drain of the MOS transistor Q3. The source of the MOS transistor Q3 is connected to the negative power output terminal. The source of the MOS transistor Q2 is connected to the negative power output terminal. The second end of the inductor L is connected to the positive power output terminal. The source of the MOS transistor Q1 is connected to the negative power input terminal. The gate of the MOS transistor Q1 is connected to a first control signal. The gate of the MOS transistor Q3 is connected to a second control signal. The gate of the MOS transistor Q2 is connected to a rectifier MOS transistor drive circuit, and the rectifier MOS transistor drive circuit is provided with a drive level limiting unit.

[0006] The MOS transistor Q2 is driven by the rectifier MOS transistor drive circuit, and at the same time, the voltage amplitude applied to the gate of the MOS transistor Q2 is limited by the drive level limiting unit, solving the problem of excessive drive amplitude of the synchronous rectification MOS transistor.

[0007] Further, the rectifier MOS transistor drive circuit includes a capacitor C3 and a diode D1. The first end of the capacitor C3 and the first end of the diode D1 are connected to the first end of the inductor L. The second end of the capacitor C3 is connected to the first end of a resistor R1. The second end of the resistor R1 is connected to the collector of a triode Q4. The emitter of the triode Q4 is connected to the gate of the MOS transistor Q2 and the first end of a resistor R4. The second end of the diode D1 is connected to the first end of a resistor R2. The second end of the resistor R2 is connected to the cathode of a zener diode Z1, the first end of a resistor R3, and the base of the MOS transistor Q4. The anode of the zener diode Z1, the second end of the resistor R3, and the second end of the resistor R4 are connected to the negative power output terminal. The diode D1, the resistor R2, and the zener diode Z1 constitute the drive level limiting unit.

[0008] Working principle:

[0009] When the MOS transistor Q1 (primary switching transistor) is turned on (controlled by the first control signal), the primary of the transformer T1 becomes positive at the top and negative at the bottom, that is, the first terminal VT1 of the primary is positive and the second terminal VT2 of the primary is negative. Since the first terminal VS1 of the secondary of the transformer T1 is in phase with the first terminal VT1 of the primary, and the second terminal VS2 of the secondary is in phase with the second terminal VT2 of the primary, at this time, the first terminal VS1 of the secondary is positive. The voltage signal is obtained from the capacitor C3 and the resistor R1 to get the signal DRVA and flows into the collector of the triode Q4. At the same time, the voltage signal passes through the diode D1 and the resistor R2 and enters the voltage regulator diode Z1 for amplitude limiting to obtain the signal VD1. At this time, according to the characteristics of the bipolar transistor, the signal SDRV output from the emitter of the triode Q4 = VD1 - 0.7V. Therefore, the selection of the voltage regulator diode Z1 can directly determine the amplitude of the drive signal SDRV of the MOS transistor Q2. After the MOS transistor Q2 obtains a stable signal SDRV, it is turned on, and the signal of the first terminal VS1 of the secondary supplies power to the output load terminal through the inductor L and the capacitor C2, completing the rectification cycle of the forward converter power supply.

[0010] When the MOS transistor Q1 is turned off, the primary of the transformer T1 becomes positive at the bottom and negative at the top, that is, the first terminal VT1 of the primary is the negative terminal relative to the second terminal VT2 of the primary. Since the first terminal VS1 of the secondary of the transformer T1 is in phase with the first terminal VT1 of the primary, and the second terminal VT2 of the primary is in phase with the second terminal VS2 of the secondary, at this time, the first terminal VS1 of the secondary is negative. At the same time, the freewheeling MOS transistor Q3 obtains the second control signal DRV and is turned on. The inductor L and the MOS transistor Q3 form an energy dissipation circuit to complete the freewheeling cycle.

[0011] The utility model realizes the design of a secondary synchronous rectification MOS transistor drive circuit based on the forward topology, especially for the function of limiting the amplitude of the gate drive level of the rectification MOS transistor, and can provide a stable and reliable drive signal for the synchronous rectification switching transistor; the drive level limiting unit can provide a stable drive level for the conduction of the rectification MOS transistor, and the capacitor C3 can isolate the DC component.

[0012] Furthermore, the gate of the MOS transistor Q2 is also connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the negative pole of the voltage output. The diode D2 can prevent the drive voltage of the rectification MOS transistor from generating a negative voltage and affecting the reliability of the MOS transistor, and further stabilize the drive voltage of the MOS transistor Q2.

[0013] Compared with the prior art, the utility model has the following advantages and beneficial effects:

[0014] (1) The utility model realizes the secondary synchronous rectification MOS transistor drive based on the forward topology, and has the function of limiting the amplitude of the gate drive level of the rectification MOS transistor, and can provide a stable and reliable drive signal for the synchronous rectification switching transistor. The utility model solves the problem of too high drive amplitude of the synchronous rectification MOS transistor.

[0015] (2) The diode D2 can prevent the driving voltage of the rectifying MOS transistor from generating negative voltage, which may affect the reliability of the MOS transistor, and the capacitor C3 can isolate the DC component.

[0016] (3) The utility model realizes precise control of the driving amplitude of the synchronous rectifying MOS transistor to provide protection for the gate of the synchronous rectifying MOS transistor.

[0017] (4) The utility model has low implementation cost, simple circuit and high reliability. At the same time, the driving level amplitude of the synchronous rectifying driving MOS transistor can be freely adjusted, which greatly improves the reliability of the forward converter power supply.

[0018] (5) The utility model has a fast driving response speed. The driving rise time and fall time are determined by the transformer signal, with no driving delay and fast response speed. It also improves the response speed of the limiting circuit and reduces the driving loss.

[0019] (6) In practical applications, the utility model can further reduce costs, improve the power conversion efficiency, and increase the stability and reliability of the whole machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is the schematic diagram of the synchronous rectification circuit of the traditional direct drive method in the prior art;

[0021] Figure 2 is the schematic diagram of the utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] The following further describes the utility model in detail with reference to the embodiments, but the implementation manners of the utility model are not limited thereto.

[0023] Embodiment:

[0024] Combined with the attached Figure 2As shown in the figure, a synchronous rectification circuit with MOS transistor drive and drive signal amplitude limiting includes a capacitor C1, a transformer T1, an inductor L, and a capacitor C2. The two ends of the capacitor C1 are respectively connected to the positive power input terminal and the negative power input terminal. The two ends of the capacitor C2 are respectively connected to the positive power output terminal and the negative power output terminal. The primary terminal of the transformer T1 is respectively connected to the positive power input terminal and the drain of the MOS transistor Q1. The secondary terminal of the transformer T1 is respectively connected to the drain of the MOS transistor Q2 and the first end of the inductor L. The first end of the inductor L is also connected to the drain of the MOS transistor Q3. The source of the MOS transistor Q3 is connected to the negative power output terminal. The source of the MOS transistor Q2 is connected to the negative power output terminal. The second end of the inductor L is connected to the positive power output terminal. The source of the MOS transistor Q1 is connected to the negative power input terminal. The gate of the MOS transistor Q1 is connected to a first control signal. The gate of the MOS transistor Q3 is connected to a second control signal. The gate of the MOS transistor Q2 is connected to a rectifier MOS transistor drive circuit, and the rectifier MOS transistor drive circuit is provided with a drive level limiting unit.

[0025] The MOS transistor Q2 is driven by the rectifier MOS transistor drive circuit, and at the same time, the voltage amplitude applied to the gate of the MOS transistor Q2 is limited by the drive level limiting unit, solving the problem of excessive drive amplitude of the synchronous rectification MOS transistor.

[0026] Further, the rectifier MOS transistor drive circuit includes a capacitor C3 and a diode D1. The first end of the capacitor C3 and the first end of the diode D1 are connected to the first end of the inductor L. The second end of the capacitor C3 is connected to the first end of a resistor R1. The second end of the resistor R1 is connected to the collector of a triode Q4. The emitter of the triode Q4 is connected to the gate of the MOS transistor Q2 and the first end of a resistor R4. The second end of the diode D1 is connected to the first end of a resistor R2. The second end of the resistor R2 is connected to the cathode of a zener diode Z1, the first end of a resistor R3, and the base of the MOS transistor Q4. The anode of the zener diode Z1, the second end of the resistor R3, and the second end of the resistor R4 are connected to the negative power output terminal. The diode D1, the resistor R2, and the zener diode Z1 form a drive level limiting unit.

[0027] The utility model consists of a rectifier MOS transistor drive circuit (including a zener diode Z1, a capacitor C3, resistors R1, R2, R3, R4, and a triode Q4), a synchronous rectification MOS transistor Q2, and a freewheeling MOS transistor Q3 to form a secondary synchronous rectification circuit with low loss and high reliability.

[0028] Synchronous rectification MOS transistor Q2: The PWM pulse taken from the secondary output of transformer T1 is synchronously rectified with switch transistor Q1 after passing through the drive level limiting unit composed of capacitor C3, resistor R1, and triode Q4, reducing the rectification loss, improving the rectification efficiency, and increasing the reliability.

[0029] Freewheeling MOS transistor Q3: It is switched by the drive circuit ((not involved in this example, so replaced by the second control signal DRV)).

[0030] Working principle:

[0031] When MOS transistor Q1 (primary switch transistor) conducts, the primary of transformer T1 becomes positive at the top and negative at the bottom, that is, the first primary terminal VT1 is positive and the second primary terminal VT2 is negative. Since the first secondary terminal VS1 of transformer T1 is in phase with the first primary terminal VT1 and the second secondary terminal VS2 is in phase with the second primary terminal VT2, at this time, the first secondary terminal VS1 is positive. The voltage signal obtains the signal DRVA from capacitor C3 and resistor R1 and flows into the collector of triode Q4. At the same time, the voltage signal passes through diode D1 and resistor R2 and enters zener diode Z1 for amplitude limiting to obtain the signal VD1. At this time, according to the characteristics of the bipolar transistor, the signal SDRV output from the emitter of triode Q4 = VD1 - 0.7V. Therefore, the selection of zener diode Z1 can directly determine the amplitude of the drive signal SDRV of MOS transistor Q2. After MOS transistor Q2 obtains the stable signal SDRV, it conducts, and the signal of the first secondary terminal VS1 supplies power to the output load terminal through inductor L and capacitor C2, completing the rectification cycle of the forward converter power supply.

[0032] When MOS transistor Q1 is cut off, the primary of transformer T1 becomes positive at the bottom and negative at the top, that is, the first primary terminal VT1 is the negative terminal relative to the second primary terminal VT2. Since the first secondary terminal VS1 of transformer T1 is in phase with the first primary terminal VT1 and the second secondary terminal VS2 is in phase with the second primary terminal VT2, at this time, the first secondary terminal VS1 is negative. At the same time, the freewheeling MOS transistor Q3 obtains the second control signal DRV and conducts. Inductor L and MOS transistor Q3 form an energy discharge circuit to complete the freewheeling cycle.

[0033] The present utility model realizes the design of the secondary synchronous rectification MOS transistor drive circuit based on the forward topology. Especially for the function of limiting the amplitude of the gate drive level of the rectification MOS transistor, it can provide a stable and reliable drive signal for the synchronous rectification switch transistor; the limiting circuit can provide a stable drive level for the conduction of the rectification MOS transistor, and capacitor C3 can isolate the DC component.

[0034] Further, the gate of the MOS transistor Q2 is also connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the negative voltage output terminal. The diode D2 can prevent the driving voltage of the rectifying MOS transistor from generating negative voltage, which may affect the reliability of the MOS transistor, and further stabilize the driving voltage of the MOS transistor Q2.

[0035] Although the present invention has been described herein with reference to illustrative embodiments of the present invention, the above embodiments are only preferred embodiments of the present invention, and the embodiments of the present invention are not limited by the above embodiments. It should be understood that those skilled in the art can design many other modifications and embodiments, which will fall within the scope of the principles and spirit disclosed in this application.

Claims

1. A synchronous rectification circuit with MOS tube drive and driving signal limiting, comprising a capacitor C1, a transformer T1, an inductor L and a capacitor C2, wherein two ends of the capacitor C1 are respectively connected to a positive end of a power input and a negative end of a power input, and two ends of the capacitor C2 are respectively connected to a positive end of a power output and a negative end of a power output, a primary end of the transformer T1 is respectively connected to a positive end of a power input and a drain of a MOS tube Q1, a secondary end of the transformer T1 is respectively connected to a drain of a MOS tube Q2 and a first end of the inductor L, and a first end of the inductor L is also connected to a drain of a MOS tube Q3, a source of the MOS tube Q3 is connected to a negative end of a power output, a source of the MOS tube Q2 is connected to the negative end of a power output, a second end of the inductor L is connected to the positive end of a power output, a source of the MOS tube Q1 is connected to the negative end of a power input, a gate of the MOS tube Q1 is connected to a first control signal, and a gate of the MOS tube Q3 is connected to a second control signal, wherein: The gate of the MOS tube Q2 is connected to a rectifier MOS tube driving circuit, and the rectifier MOS tube driving circuit is provided with a driving level limiting unit.

2. A synchronous rectification circuit with MOS tube driving and driving signal limiting according to claim 1, characterized in that: The rectifier MOS tube driving circuit includes a capacitor C3 and a diode D1. The first end of the capacitor C3 and the first end of the diode D1 are connected to the first end of the inductor L. The second end of the capacitor C3 is connected to the first end of the resistor R1. The second end of the resistor R1 is connected to the collector of the transistor Q4. The emitter of the transistor Q4 is connected to the gate of the MOS tube Q2 and the first end of the resistor R4. The second end of the diode D1 is connected to the first end of the resistor R2. The second end of the resistor R2 is connected to the cathode of the voltage-stabilizing diode Z1, the first end of the resistor R3 and the base of the MOS tube Q4. The anode of the voltage-stabilizing diode Z1, the second end of the resistor R3 and the second end of the resistor R4 are connected to the negative end of the power supply output. The diode D1, the resistor R2 and the voltage-stabilizing diode Z1 constitute a driving level limiting unit.

3. A synchronous rectification circuit with MOS tube driving and driving signal limiting according to claim 2, characterized in that: The gate of the MOS transistor Q2 is also connected to the cathode of the diode D2, and the anode of the diode D2 is connected to the negative output terminal of the power supply.

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