Multi-die stacked radio frequency device

Abstract

The utility model provides a multi-die stacked radio frequency device, which belongs to the field of piezoelectric composite materials and comprises a first bare chip and a plurality of filter bare chips, the filter bare chips are coupled with the front surface of the first bare chip, and a signal lead-out part is manufactured on the back surface of the first bare chip opposite to the coupling surface. The first bare chip comprises a multi-layer heterogeneous bonding substrate, functionalized metal holes, wafer-level packaging and at least one surface acoustic wave filter manufactured on the front and back surfaces of the first bare chip, and the functionalized metal holes comprise at least one of penetrating type via holes and / or dielectric barrier type radio frequency via holes; and the surface acoustic wave filter performs radio frequency signal communication through the functionalized metal hole. The functionalized metal holes can realize capacitance and inductance series-parallel matching and performance coupling improvement or isolation coexistence of a plurality of filter bare chips and a plurality of film type surface acoustic wave filters on two sides of the bare chips, and the filters are higher in integration level and lower in loss.

Description

Technical Field

[0001] The utility model belongs to the technical field of radio frequency devices, and particularly relates to a multi-chip stacked radio frequency device. Background Art

[0002] Spectrum resources are an indispensable foundation for modern communication and broadcasting technologies. Their effective management and rational utilization are crucial for ensuring the stability and quality of wireless communication services. Spectrum resources have extremely high economic value in modern society and are the foundation for supporting key infrastructures such as mobile communication, Internet access, broadcast media, and satellite communication.

[0003] With the upgrading of mobile terminals, the market demand requires more radio frequency filters to be integrated in a single terminal device. For example, the number of filters in a mobile phone has increased from a few in the past to 40 - 60 today, and future high-performance mobile phones will require the integration of hundreds of filters. This poses a severe challenge to the miniaturization and packaging of filters. The miniaturization of filters compresses the design space of devices, resulting in a certain sacrifice in the comprehensive performance of filters.

[0004] The development of three-dimensional stacking technology enables filters to reduce the occupied area of radio frequency modules, trading space height for area. However, it also brings problems such as high packaging process costs and poor packaging reliability. Summary of the Utility Model

[0005] To solve the above problems, the utility model provides a multi-chip stacked radio frequency device, which can integrate more filters in a unit space and can have comprehensive performances such as lower insertion loss and better isolation.

[0006] The utility model adopts the following technical solutions to solve the above problems:

[0007] A multi-chip stacked radio frequency device includes a first die and multiple filter dies. The filter dies are coupled to the front side of the first die, and signal leads are made on the back side of the first die opposite to the coupling surface. The first die includes a multi-layer heterogeneous bonding substrate, functionalized metal holes, wafer-level packaging, and at least one surface acoustic wave filter fabricated on both the front and back sides of the first die. The functionalized metal holes include at least one of through vias and / or dielectric-barrier radio frequency vias. The metalization pattern of the surface acoustic wave filter is connected for radio frequency signals through the functionalized metal holes.

[0008] Furthermore, interconnection patterns are fabricated on the upper and lower surfaces of the through vias to form a three-dimensional spiral inductor, and a dielectric layer is fabricated on the dielectric-barrier radio frequency vias to form a low-loss capacitor.

[0009] Further, the dielectric in the dielectric barrier type RF via can be any layer in the multi-layer heterogeneous bonded substrate, and the thickness of the dielectric in the dielectric barrier type RF via is not greater than the thickness of this dielectric layer.

[0010] Further, both the front and back sides of the first die include surface acoustic wave filters, coupling sites for multiple filter dies, metal interconnection lines, and organic polymers. The coupling sites and the surface acoustic wave filter on the first surface transfer signals to the metallized holes through the first interconnection metal lines.

[0011] Further, the organic polymer constructs cavities in the regions with surface acoustic wave resonators and seals the resonators. The wafer-level package includes the construction of cavities above the resonators by the organic polymer and the fabrication of UBMs at the wafer coupling sites. The UBM metal structures of the coupling sites include Ti-Cu-Ni, Ti-Cu-Ni-Sn, Ti-Cu-Ni-Pd-Au, Ti-Cu-Ni-Au, NiCr-Cu, NiCr-Cu-Sn, NiCr-Cu-Ni-Sn, NiCr-Cu-Ni-Au.

[0012] Further, the coupling sites of the multiple filter dies and the functionalized metal hole positions on the first die are in a coincident state and a state of being connected and conducted through metal interconnection lines when not coincident. The area of the die coupling sites is 1 - 3 times the area of the functionalized metal holes.

[0013] Further, the die coupling sites on the first surface and the surface acoustic wave filter on the first surface transfer signals to the metallized holes through the first interconnection metal lines. The first interconnection metal lines connect, couple, or isolate the surface acoustic wave filter on the first surface of the first die, the filters of the multiple filter dies, and the metal holes on the first surface according to design requirements.

[0014] Further, the metallized hole positions on the second surface and the surface acoustic wave filter on the second surface transfer signals to the signal extraction coupling sites through the second interconnection metal lines. The second interconnection metal lines connect, couple, or isolate the signals at the metallized hole positions on the second surface of the first die, the surface acoustic wave filter on the second surface, and the coupling connection sites for signal extraction on the second surface according to design requirements.

[0015] Further, the coupling methods between the filter dies and the first die include metal ball bumping and flipping, metal bump - metal bump bonding, electroplated metal pillar - pad flip-chip reflow.

[0016] Further, the filter die includes at least one packaged radio frequency filter die, specifically including one or more of surface acoustic wave filters (SAW), bulk acoustic wave filters (BAW), integrated passive filters (IPD), low temperature co-fired ceramic filters, and millimeter wave filters.

[0017] Further, the multi-layer heterogeneous bonding substrate includes a first thin film piezoelectric layer and a second thin film piezoelectric layer, a first isolation layer and a second isolation layer, a first absorption layer and a second absorption layer, and an intermediate substrate layer with independent material properties and material parameters.

[0018] Further, the materials of the first thin film piezoelectric layer and the second thin film piezoelectric layer include lithium niobate and lithium tantalate. The materials of the first isolation layer and the second isolation layer are low sound velocity materials, including silicon dioxide. The preparation processes of the materials of the first isolation layer and the second isolation layer are not necessarily the same. The preparation processes include magnetron sputtering, ion beam sputtering, chemical vapor deposition, thermal oxidation, and sol-gel method. The materials of the first absorption layer and the second absorption layer capture electrons to improve the quality factor Q of the device. The absorption layer materials include polysilicon. The substrate layer is a high sound velocity material, including high resistivity silicon, silicon carbide, diamond, sapphire, and quartz.

[0019] Further, the material properties include physical and chemical properties such as the lattice structure, crystal type, dielectric constant, magnetic permeability, density, and electro-optic effect of the crystal material; the material parameters include material thickness and material distribution area.

[0020] Through holes are made and metallized on the multi-layer heterogeneous bonding sheet. An insulating layer, an adhesion layer, and a metal layer are sputtered on the side walls of the through holes, and electroplated copper is used for metallization filling inside the through holes to connect the upper and lower surfaces of the multi-layer heterogeneous bonding sheet.

[0021] The beneficial effects of the present utility model are as follows:

[0022] 1. The multi-layer heterogeneous bonding technology, via etching technology, and die-to-die coupling technology using double-sided piezoelectric films are used, enabling more filters to be monolithically integrated on a single chip, with a larger filter design space, lower insertion loss, better isolation, higher reliability, and better comprehensive device performance.

[0023] 2. The layout of the metallized holes in the multi-layer heterogeneous bonding wafer structure is divided into multiple specifications. The size and arrangement position of the metallized holes are different under each specification. The size and arrangement of the metallized holes under a certain specification are fixed and become one of the rules for the pin definition and design of surface acoustic wave filters, facilitating batch production of composite wafers.

[0024] 3. The materials of the first absorption layer and the second absorption layer include polysilicon, silicon nitride, and metal, which can capture electrons and improve the quality factor Q of the device.

[0025] 4. The functionalized solid metal holes include at least one of the through vias penetrating the upper and lower surfaces of the holes and the RF vias with intermediate dielectric barriers. Interconnection patterns can be fabricated on the upper and lower surfaces of the through vias to form a three-dimensional spiral inductor. A dielectric layer can be formed on the solid holes with dielectric barriers to form a low-loss capacitor with a certain capacitance value. The inductors and capacitors fabricated based on the functionalized solid metal holes can be used by multi-die stacked RF devices for circuit matching or for optimizing the performance of a certain resonator through series and parallel connections. Description of the Drawings

[0026] To more clearly illustrate the specific embodiments of the present invention, the drawings required for use in the description of the specific embodiments will be briefly introduced below. The drawings in the following description are example diagrams of the novel RF front-end surface acoustic wave filter module described above. Obviously, the drawings described below are merely exemplary, and those of ordinary skill in the art can obtain other embodiment drawings based on the provided drawings without creative efforts.

[0027] Figure 1 Structural diagram of a multi-die stacked RF device that only includes through metal holes;

[0028] Figure 2 Schematic diagram of the distribution and connection method of surface filters, pads, and functionalized metal holes on the surface of a multi-layer heterogeneous bonded wafer;

[0029] Figure 3 Typical structural diagram of a multi-layer heterogeneous bonded wafer;

[0030] Figure 4 Schematic diagram of the structure of a multi-layer heterogeneous bonded wafer with openings;

[0031] Figure 5 Schematic diagram of the structure of a multi-layer heterogeneous bonded wafer with via metallization;

[0032] Figure 6 Schematic diagram of the structure of a multi-layer heterogeneous bonded wafer with double-sided grinding and polishing;

[0033] Figure 7 Schematic diagram of the structure of a multi-layer heterogeneous bonded wafer with surface acoustic wave filters fabricated on both sides and wafer-level packaging;

[0034] Figure 8 Schematic diagram of the structure of a die assembly component with ball implantation;

[0035] Figure 9 Structural diagram of a multi-die stacked RF device that includes through and dielectric capacitor isolated metal holes.

[0036] In the figure: 1 - interdigital transducer metal fingers; 2 - organic polymer cavity; 3 - organic polymer; 4 - die coupling site; 5 - metal interconnection line; 6 - functionalized metal hole; 7 - second piezoelectric thin film layer; 8 - second isolation layer; 9 - second absorption layer; 10 - substrate layer; 11 - first absorption layer; 12 - first isolation layer; 13 - first piezoelectric thin film layer; 14 - functionalized metal hole coupling panel; 15 - filter die; 16 - filter die and multi-layer heterogeneous bonding wafer coupling site; 17 - interconnection line between functionalized metal hole and coupling site; 18 - short-distance metal interconnection line; 19 - long-distance metal interconnection line; 20 - filter pad on the surface of multi-layer heterogeneous bonding wafer; 21 - filter on the surface of multi-layer heterogeneous bonding wafer; 22 - surface of multi-layer heterogeneous bonding wafer; 23 - metal pad on the surface of multi-layer heterogeneous bonding wafer; 25 - functionalized metal hole after electroplating filling; 26 - surface electroplated metal layer; 28 - functionalized metal hole after etching; 29 - through-hole via after grinding to remove surface metal layer; 30 - dielectric barrier RF via hole. Detailed implementation mode

[0037] The exemplary embodiments of this patent will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of this patent are shown in the drawings, it should be understood that this patent can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of this patent and to fully convey the scope of this patent to those skilled in the art. It should be noted that, without conflict, the embodiments in this patent and the features in the embodiments can be combined with each other. This patent will be described in detail below with reference to the drawings and in combination with the embodiments.

[0038] Embodiment 1

[0039] As Figure 1-2As shown in the figure, the present utility model provides a multi-die stacked radio frequency device, which includes a first die and multiple filter dies 15. The first die has a front side and a back side. The front side is the first surface, and the back side is the second surface. The filter dies 15 are coupled to the front side of the first die. The coupling methods between the filter dies 15 and the first die include flip-chip bonding with metal ball bumping, metal bump-metal bump bonding, and electroplated metal pillar-pad flip-chip reflow soldering. Signal leads are made on the back side of the first die opposite to the coupling surface. The first die includes a multi-layer heterogeneous bonding substrate, functionalized metal vias 6 penetrating the first die, wafer-level packaging, and at least one surface acoustic wave filter fabricated on both the front and back sides of the first die. Thin-film surface acoustic wave filter metallization patterns are respectively fabricated on the front and back sides of the first die, and the surface acoustic wave filter metallization patterns are connected by radio frequency signals through the functionalized metal vias 6. Both the front and back sides of the first die include surface acoustic wave filters, coupling sites for multiple filter dies, metal interconnection lines, and organic polymer. The coupling sites and the surface acoustic wave filters on the first surface transfer signals to the metallized holes through the first interconnection metal lines. The filter die includes at least one packaged radio frequency filter die, specifically including one or more of surface acoustic wave filters (SAW), bulk acoustic wave filters (BAW), integrated passive filters (IPD), low-temperature co-fired ceramic filters, and millimeter-wave filters.

[0040] In this embodiment, the functionalized metal vias 6 only include through vias. Interconnection patterns are fabricated on the upper and lower surfaces of the through vias to form a three-dimensional spiral inductor. The inductor fabricated based on the functionalized metal vias 6 can be used by the multi-die stacked radio frequency device for circuit matching or for series-parallel optimization of the performance of a certain resonator.

[0041] The organic polymer 3 constructs an organic polymer cavity 2 in the area where there is a surface acoustic wave resonator and seals the resonator. The wafer-level packaging includes the construction of an organic polymer cavity above the resonator and the fabrication of UBM at the wafer coupling sites. The UBM metal structure at the coupling sites includes Ti-Cu-Ni, Ti-Cu-Ni-Sn, Ti-Cu-Ni-Pd-Au, Ti-Cu-Ni-Au, NiCr-Cu, NiCr-Cu-Sn, NiCr-Cu-Ni-Sn, NiCr-Cu-Ni-Au.

[0042] The coupling sites of multiple filter dies 15 coincide with the positions of the functionalized metal holes on the first die and are connected and conducted through metal interconnections in the non - coincident state. The area of the die coupling sites is 1 - 3 times the area of the functionalized metal holes. The coupling sites on the first surface and the surface acoustic wave filter on the first surface transfer signals to the metallized holes through the first interconnection metal lines. The first interconnection metal lines connect and couple or isolate the surface acoustic wave filter on the first surface of the first die, the filters of multiple filter dies, and the metal holes on the first surface according to design requirements. The positions of the metallized holes on the second surface and the surface acoustic wave filter on the second surface transfer signals to the signal extraction coupling sites through the second interconnection metal lines. The second interconnection metal lines connect and couple or isolate the signals of the metallized hole positions on the second surface of the first die, the surface acoustic wave filter on the second surface, and the coupling connection sites for signal extraction on the second surface according to design requirements.

[0043] In this embodiment, the multi - die stacked radio frequency device structure includes: a first die and multiple filter dies 15. The first die includes a first piezoelectric thin film layer 13, a first isolation layer 12, a first absorption layer 11, a substrate layer 10, a second absorption layer 9, a second isolation layer 8, a second piezoelectric thin film layer 7, functionalized metal holes 6, a functionalized metal hole coupling panel 14, interdigital transducer metal fingers 1 on the first die, an organic polymer 3, an organic polymer cavity 2, metal interconnections 5, an interconnection line 17 between the functionalized metal holes and coupling sites on the first die, die coupling sites 4. The first piezoelectric thin film layer 13 and the second piezoelectric thin film layer 7 are lithium niobate thin films, and their crystal orientations and thicknesses are not necessarily the same. In this embodiment, according to the design requirements of the surface acoustic wave filters on the front and back sides, multi - module coupled acoustic - electric simulation is performed through professional software before preparation to determine the filter performance corresponding to the piezoelectric material in multiple crystal orientations, and different crystal material structures are arranged on the front and back sides. The crystal orientation of the piezoelectric thin film layer 13 on the first surface of the first die is designed to be 15°YX - lithium niobate, and the thickness is 500 nm. The crystal orientation of the piezoelectric thin film layer 7 on the second surface of the first die is designed to be 128°YX - lithium tantalate, and the thickness is 750 nm. The material parameters and preparation processes of the first isolation layer 12 and the second isolation layer 8 on the first die are not necessarily the same. In this embodiment, the first isolation layer 12 and the second isolation layer 8 are preferably made of silicon dioxide and are prepared by magnetron sputtering. The substrate temperature, sputtering atmosphere, and ionization intensity in magnetron sputtering are adjusted in this embodiment to change important material parameters such as the density and dielectric constant of silicon dioxide. The thicknesses of the first isolation layer 12 and the second isolation layer 8 are 500 nm. The first absorption layer 11 and the second absorption layer 9 are made of polysilicon material, and a polysilicon layer with a thickness of 1 um is fabricated on the single - crystal substrate layer by sputtering. The substrate layer 10 is a high - sound - velocity material. Considering the good high - sound - impedance characteristics of the silicon substrate and the current mature through - silicon via (TSV) process, a high - resistivity silicon substrate is selected in this embodiment, the silicon crystal orientation is (1, 1, 1), and the thickness of the substrate silicon is 500 um.

[0044] For the piezoelectric thin film layer, the currently common etching methods are Ar physical etching and wet etching. However, wet etching is greatly affected by the anisotropy of the piezoelectric crystal material, generally resulting in poor hole morphology. Ar physical bombardment etching is a common practice in the academic and industrial circles. By fabricating a mask on the surface of the piezoelectric thin film layer, Ar physical bombardment etching is used to penetrate the piezoelectric thin film layer and the silicon dioxide isolation layer, and CF4 and SF6 gases are used for cyclic etching on the silicon layer to remove the polysilicon absorption layer and the single crystal silicon substrate layer in the holes, obtaining through-holes with a diameter of 50 - 80 um. The through-holes penetrate the first die, and after metallization, the front and back signals are connected. In the embodiment, a 1-um-thick insulating layer of silicon dioxide is sputtered in the through-holes after fabrication, a 0.3-um-thick adhesion layer of Ti and a 3-um-thick electroplating seed layer are sputtered, electroplating is used to fill the holes and the surface metal copper is removed by CMP, and the surface is polished. At this time, a first die with no height difference and seamless connection between the metallized hole surface and the piezoelectric thin film is formed on the first and second surfaces. The quality of the metal filling in the through-holes can be detected by XRD.

[0045] A surface acoustic wave filter is fabricated on the surface of the first die. Through mature semiconductor processing techniques such as photoresist coating, lithography, development, evaporation coating, stripping, and bus bar thickening, a metal pattern on the first surface of the first die is fabricated, and necessary metal interconnection lines and metal pads are also fabricated therein according to the design.

[0046] As Figure 2 shown, in this embodiment, an incomplete surface acoustic wave filter 21, a multi-layer heterogeneous bonding wafer surface metal pad 23, and short-distance metal interconnection lines 18 are fabricated on the second surface of the first die. The multi-layer heterogeneous bonding wafer surface filter 21 on the multi-layer heterogeneous bonding wafer surface has a multi-layer heterogeneous bonding wafer surface filter pad 20 by itself, and does not completely rely on the multi-layer heterogeneous bonding wafer surface metal pad 23 on the second surface of the first die. The diameter of the through-holes 6, die coupling sites 4, and multi-layer heterogeneous bonding wafer surface metal pads 23 on the second surface is 120 um, which are used for coupling with an external radio frequency circuit. The short-distance metal interconnection lines 18, metal interconnection lines 5, and long-distance metal interconnection lines 19 provided on the second surface are used for coupling with the external radio frequency circuit. The bottom of the multi-layer heterogeneous bonding wafer surface metal pad 23 is a piezoelectric thin film layer without through-holes 6 or a piezoelectric thin film layer with through-holes 6. In this embodiment, a large-sized cell is provided on the second surface, which includes six multi-layer heterogeneous bonding wafer surfaces 22 with different sizes. Different multi-layer heterogeneous bonding wafer surface filters 21 are designed and fabricated in each multi-layer heterogeneous bonding wafer surface 22, and a plurality of through-holes 6 and a plurality of multi-layer heterogeneous bonding wafer surface metal pads 23 are distributed in the gaps between each multi-layer heterogeneous bonding wafer surface filter 21. The signals of the through-holes 6 are connected to the electrical signals on the first surface of the first die.

[0047] The through - via via - holes 6, the first piezoelectric thin - film layer 13, the metal interconnecting lines 5, the short - distance metal interconnecting lines 18, and the long - distance metal interconnecting lines 19 are provided. On the one hand, the through - via via - holes 6 transfer the electrical signals on the first surface to the metal pads 23 on the surface of the multi - layer heterogeneous - bonded wafer through the metal interconnecting lines 5, the short - distance metal interconnecting lines 18, or the long - distance metal interconnecting lines 19, and then access the radio - frequency circuit, playing the role of short - distance conduction and integration. On the other hand, it enables the performance coupling between multiple filters, increasing more design space. Filters are fabricated on both the front and back sides of the first die to improve the isolation of the device, or a three - dimensional spiral inductor is formed by interconnecting the upper and lower surfaces of the through - via via - holes 6 and incorporated into the filter to form a matching circuit to improve specific device metrics, or the common - ground terminals of multiple different filters are connected together to achieve out - of - band suppression in a specific frequency band, etc.

[0048] The first surface is directly coupled to the filter die 5. Therefore, the position specifications of the metal pads 23 on the surface of the multi - layer heterogeneous - bonded wafer and the size and layout of the filter die are closely related. After the filter dies on the first surface are stacked and coupled, they are connected to the die coupling sites 4 and the through - via via - holes 6 through the interconnecting lines 17 between the first - die functionalized metal holes and the coupling sites, or the bottom of the die coupling site 4 is in direct contact with the through - via via - hole 6 and then conducts to transmit the signal to the second surface. The multi - layer heterogeneous - bonded wafer surface filters 21 on the first surface conduct each signal terminal to the through - via via - hole 6 through the interconnecting lines 17 between the first - die functionalized metal holes and the coupling sites. The interconnecting lines 17 between the first - die functionalized metal holes and the coupling sites can conduct with each other. If the common - ground terminal is conducted through the interconnecting lines 17 between the first - die functionalized metal holes and the coupling sites on the first surface, it can couple the multi - layer heterogeneous - bonded wafer surface filters 21 on the first surface with the filter die, thereby increasing the combination of multiple filters and achieving the flexibility of performance coupling, and improving the integration of the device.

[0049] The manufacturing method of the above - mentioned multi - die stacked radio - frequency device, the intermediate state during its manufacturing is as Figures 3-7 shown, and the specific steps are as follows:

[0050] 1) Provide two pieces of double - side polished and flat piezoelectric single - crystal materials. The thickness of each piezoelectric single - crystal material is 250 um. After subsequent ion implantation and annealing and stripping, they become the second piezoelectric thin - film layer 7 and the first piezoelectric thin - film layer 13. The first piezoelectric crystal is 15°YX - lithium niobate, and the second piezoelectric crystal is 128°YX - lithium tantalate. Cutting the wafer downward can make the comprehensive performance of the surface acoustic wave filter better. The comprehensive performance of the filter includes pass - band insertion loss, bandwidth, and quality factor. The first piezoelectric crystal material includes the upper surface and the lower surface of the wafer. The upper surface of the wafer is the first surface, and the lower surface of the wafer is the second surface. The first surface is He +The implanted surface. The second piezoelectric crystal material includes the upper surface and the lower surface of the wafer. The upper surface of the wafer is the third surface, and the lower surface of the wafer is the fourth surface. The third surface is the He + implanted surface.

[0051] 2) Implant He into the lithium niobate wafer + , and the implanted ion energy is selected according to the required film thickness (i.e., the implantation depth). In this embodiment, the material of the first piezoelectric wafer is a lithium niobate thin film with a thickness of 500 nm, and the material of the second piezoelectric wafer is a thin film lithium tantalate with a thickness of 750 nm. Set the acceleration voltage and energy of the device to a certain range so that the He + ion implantation depth in 15°YX-lithium niobate reaches 500 nm, and the He+ ion implantation depth in 128°YX-lithium tantalate reaches 750 nm.

[0052] 3) Provide a high-resistance silicon substrate as the substrate layer 10 for multi-layer hetero-bonding. The thickness of the high-resistance silicon substrate is 500 um. The high-resistance silicon substrate is divided into the first surface and the second surface. Sputter the second absorption layer 9 and the first absorption layer 11 of polysilicon thin film on the first and second surfaces respectively. The second absorption layer 9 and the first absorption layer 11 serve as absorption layers, which can capture the leaked electrons in the wafer and improve the Q value of the device. The thickness of the polysilicon thin film is 1 um.

[0053] 4) Fabricate a silicon oxide thin film on the surface of the polysilicon absorption layer. The silicon oxide thin film constitutes the acoustic low-impedance layer, that is, the second isolation layer 8 and the first isolation layer 12. The silicon oxide thin film can be grown on the polysilicon surface by thermal oxidation. The required thickness of the polysilicon is approximately the sum of the thickness of the grown silicon oxide and the reserved absorption layer thickness. In this growth mode, the interface between the silicon oxide and the polysilicon is perfectly bonded. The silicon oxide thin film can also be prepared by sputtering. The purity and density of the generated silicon dioxide are adjusted by adjusting parameters such as the gas pressure of magnetron sputtering O2 and Ar and the electric field ionization intensity. Preferably, in this embodiment, dense silicon dioxide is generated on the wafer surface by the reaction of the silicon target with ionized O under the action of a bias voltage. Silicon oxide thin films with a thickness of 500 nm are provided on both the first surface and the second surface of the substrate layer 10.

[0054] 5) The first surface of the 15°YX-lithium niobate piezoelectric single crystal material and the first surface of the silicon oxide wafer exhibit better activation effects than Ar under O2 and N2 plasma activation, forming strong hydrophilicity, which is beneficial to hydrophilic bonding. The piezoelectric wafer and the silicon oxide wafer are placed under plasma activation in an O2 and N2 atmosphere, which has physical and chemical effects. It can remove impurities, break chemical bonds, and form hydroxyl groups and hydrogen bonds on the surface by reacting with water, enhancing hydrophilicity. In the bonding process, the surface roughness of the wafer affects the bonding effect. After plasma activation, megasonic cleaning is required. Megasonic cleaning technology uses high-frequency sound waves to efficiently clean fine particles in the solution through acoustic pressure and acoustic streaming effects to ensure no pollutant residues, providing a high-quality foundation for the bonding process. In this embodiment, megasonic cleaning is performed on the silicon substrate and the 15°YX-lithium niobate piezoelectric wafer to be bonded at a power of 300W for 120s.

[0055] 6) Align and contact the first surfaces of the 15°YX-lithium niobate piezoelectric single crystal material and the silicon oxide wafer that have been activated and cleaned. At this time, both the surfaces of lithium niobate and the silicon oxide wafer have appropriate hydroxyl densities. By applying pressure, the hydroxyl groups on the two wafer surfaces are close enough. At room temperature, a dehydration condensation reaction is spontaneously formed by fitting with the interfacial force to achieve atomic-level wafer bonding.

[0056] 7) Annealing and strengthening. The interfacial energy will increase after the pre-bonded wafers are stored at room temperature, mainly because H2O molecules gradually diffuse along the bonding interface into the air or the SiO2 layer. High-temperature annealing can accelerate this process to form a stable connection, enhance the bonding strength, and reduce bubbles. However, conventional annealing easily causes wafer fragmentation due to the large difference in the thermal expansion coefficients of lithium niobate crystals and silicon. The stepwise heating and cooling annealing process can slow down the stress. In this embodiment, stepwise annealing and strengthening are performed on the pre-bonded wafers, rising from room temperature to 90°C at a rate of 1°C / min, maintaining at this temperature for 5h, then continuing to rise to 150°C at a rate of 1°C / min and holding for 10h, and finally cooling to room temperature at a rate of 1°C / min.

[0057] 8) Performance characterization. Bonding strength is one of the most important measured characteristics in the bonding process. Low strength may lead to wafer cracking. In this embodiment, the double cantilever beam test method is used to evaluate the bonding strength by testing the crack length. The bonding strength tested in the embodiment reaches 1.94 J / cm 2 , which can withstand the mechanical, thermal, and water stress corrosion in subsequent processing, providing a solid foundation for wafer peeling and device preparation.

[0058] 9) The third surface of the 128°YX-lithium tantalate piezoelectric single crystal material and the second surface of the silicon oxide wafer are activated by O2 and N2 plasmas. After activation, megasonic cleaning is carried out. The megasonic cleaning technology uses high-frequency sound waves to efficiently clean fine particles in the solution through acoustic pressure and acoustic streaming effects, ensuring no pollutant residues and providing a high-quality basis for the bonding process. In this embodiment, megasonic cleaning is performed on the silicon substrate and the 128°YX-lithium tantalate piezoelectric wafer to be bonded at a power of 300 W for 120 s.

[0059] 10) Align and contact the activated surfaces of the third surface of the 128°YX-lithium tantalate piezoelectric single crystal material and the second surface of the silicon oxide wafer after activation and cleaning. At this time, both the surfaces of lithium niobate and the silicon oxide wafer have appropriate hydroxyl densities. By applying pressure, the hydroxyls on the two wafer surfaces are close enough, and a dehydration condensation reaction is spontaneously formed by interfacial force bonding at room temperature to achieve atomic-level wafer bonding.

[0060] 11) Annealing and strengthening. Stepwise annealing and strengthening are performed on the pre-bonded wafers, heating from room temperature to 90 °C at a rate of 1 °C / min, holding at this temperature for 5 h, then continuing to heat to 150 °C at a rate of 1 °C / min and maintaining for 10 h, and subsequently cooling to room temperature at a rate of 1 °C / min.

[0061] 12) Performance characterization. In this embodiment, the bonding strength is evaluated by measuring the crack length through the double cantilever beam test method. The measured bonding strength in the embodiment reaches 1.97 J / cm 2 , which can withstand mechanical, thermal, and hydrostatic stress corrosion during subsequent processing, providing a solid foundation for wafer peeling and device fabrication.

[0062] 13) Preparation of the piezoelectric thin film layer. First, hold at 165 °C for 16 h, then anneal at 190 °C for 6 h to further improve the bonding strength. Then raise the sample temperature to about 228 °C to separate the He + implantation layer from the lithium niobate donor material, thereby separating the piezoelectric wafers on both sides from the required depth.

[0063] 14) Double-sided grinding. Double-sided grinding is performed on the first bare die after bonding and peeling to make the rough piezoelectric thin film surface smooth after peeling.

[0064] After the preparation through the above steps, a Figure 3 multi-layer hetero-bonded wafer with double-sided piezoelectric thin films is obtained. Then through-silicon vias fabrication and through-silicon via metallization are carried out.

[0065] 15) A soft mask material is fabricated on the surfaces of the front and back piezoelectric thin film layers. In this embodiment, the photoresist HSQ is used, and holes to be etched are fabricated after photolithography and development.

[0066] 16) Etch the front and back thin film layers including the piezoelectric thin film layer and the isolation layer using an Ar ion etcher. Adjust the voltage of the Ar ions and the gas atmosphere, and control the sidewall angle of the hole etching to make the sidewall etching close to a vertical angle.

[0067] 17) Etch the polysilicon layer and the high-resistance silicon layer using a mature TSV process to obtain the etched functionalized metal holes 28, and ultrasonically clean to remove impurities in the holes to obtain Figure 4 the wafer structure.

[0068] 18) Sputter an insulating layer on the inner hole wall of the through hole. In this embodiment, the thickness of the sputtered silicon oxide layer is 300 nm, the thickness of the sputtered deposited metal Ti is 300 nm, and the thickness of the electroplating seed layer Cu is 3000 nm. In this embodiment, a sputtering machine tool with an aspect ratio coverage ability greater than 5:1 is selected to achieve uniform coverage of the hole wall insulating layer, the adhesion layer, and the electroplating seed layer.

[0069] 19) Electroplate the functionalized metal holes. In this embodiment, adjust the electroplating solution formula and the distribution of the electroplating potential to solidify and fill the metal copper in the through hole. For the filled structure diagram, refer to Figure 5 where a surface electroplated metal layer 26 is electroplated and attached to the wafer surface, and the electroplated metal is significantly recessed at the through hole position to form a through-type via 25 after electroplating filling.

[0070] 20) Double-sided grinding and polishing. Perform CMP grinding on the front and back sides of the prepared first die until the surface of the piezoelectric thin film layer is completely exposed, and then polish to obtain Figure 6 the structure where the through-type via 29 after removing the surface metal layer is flush with the wafer surface and there is no metal residue, and the flatness parameters such as the in-chip uniformity PTTV and TTV meet the wafer standard.

[0071] 21) Preparation and packaging of the surface acoustic wave filter on the first surface of the first die. Prepare the chip into a metal pattern including electroplated interconnections through photolithography and lift-off processes. Obtain a series of photoresist strip / photoresist seam photoresist patterns on the first surface of the first die by spin-coating photoresist, exposing with a photomask, and developing with TMAH. Evaporate 10 nm of metal Ti - 300 nm of Al, and use an NMP stripping solution to punch and strip to remove the metal photoresist strips, leaving the interdigital transducer metal fingers 1 and the metal interconnections 5 on the first die, and the interconnections 17 between the functionalized metal holes and the coupling sites on the first die. Vacuum stick a dry film of the organic polymer 3 on the first surface without bubbles, then bake, and then perform i-line exposure. After developing with a dry film special developer, the resonators and the coupling pads are exposed on the surface. Refer to Figure 7The organic polymer cavity 2, die coupling site 4, metal interconnect 5, and through-hole via 6 form a window for the resonator, coupling pad area without damage and pollution. After baking, the dry film in other areas fits tightly with the surface. Then, the first dry film is cured at 200 °C for 2 hours to allow the dry film to undergo sufficient chemical reactions.

[0072] 22) Prepare the second layer of negative dry film on the first surface of the first die. The second layer of dry film is laminated with the first die in a vacuum environment without gaps and bubbles, then baked, followed by i-line exposure. After developing with a dry film special developer, a window with exposed coupling sites and a surface without damage and pollution is obtained. Refer to Figure 7 the die coupling site 4 and through-hole via 6 of the die. After baking, the dry film in other areas fits tightly with the surface, thus constructing an organic polymer cavity 2 above the resonator. Then, the second layer of dry film is cured at 200 °C for 2 hours to allow the dry film to undergo sufficient chemical reactions.

[0073] 23) Prepare and package the surface acoustic wave filter on the second surface of the first die, similar to step 21.

[0074] 24) Prepare the second layer of negative dry film on the second surface of the first die, similar to step 22.

[0075] 25) Fabricate the die assembly component. Refer to Figure 1 、 Figure 2 、 Figure 8 The filter die 15 includes types such as surface acoustic wave filters (SAW), bulk acoustic wave filters (BAW), integrated passive filters (IPD), low-temperature co-fired ceramic filters, and millimeter-wave filters. In this embodiment, six different dies are fabricated and packaged. Then, on the surface coupling sites of the packaged filter die 15, multiple filter dies with a diameter of 100 um and a height of 50 um and multi-layer heterogeneous bonding wafer coupling sites 16 are fabricated by ultrasonic pressing and ball planting with gold wires. The wafer is then diced into small dielets, and the small dielets of multiple different types of wafers are sequentially inverted on the surface 22 of the multi-layer heterogeneous bonding wafer, realizing multi-die stacking ( Figure 1 ).

[0076] Example 2:

[0077] As Figure 9As shown, the functionalized metal hole 6 includes a through-hole via and a dielectric-barrier RF via 30. The dielectric in the dielectric-barrier RF via 30 can be any layer in the multi-layer heterogeneous bonding substrate, and the thickness of the dielectric in the dielectric-barrier RF via is not greater than the thickness of that dielectric layer. Interconnection patterns are fabricated on the upper and lower surfaces of the through-hole via to form a three-dimensional spiral inductor, and a dielectric layer is fabricated on the dielectric-barrier RF via 30 to form a low-loss capacitor. The inductor and capacitor fabricated based on the functionalized metal hole 6 can be used by a multi-die stacked RF device for circuit matching or for series / parallel connection to optimize the performance of a certain resonator. Other technical features are the same as those in Embodiment 1.

[0078] This embodiment provides a multi-die stacked RF device. The device structure includes: a first bare die and multiple filter bare dies. The first bare die includes a first piezoelectric thin film layer 13, a first isolation layer 12, a dielectric layer 30 extending from the first isolation layer, a first absorption layer 11, a substrate layer 10, a second absorption layer 9, a second isolation layer 8, a second piezoelectric thin film layer 7, a functionalized metal hole 6, a functionalized metal hole coupling panel 14, interdigital transducer metal fingers 1 on the first bare die, an organic polymer 3, an organic polymer cavity 2, a metal interconnection line 5, an interconnection line 17 between the functionalized metal hole of the first bare die and the coupling site, a die coupling site 4. The first piezoelectric thin film layer 13 and the second piezoelectric thin film layer 7 are lithium niobate thin films, and their crystal cuts and thicknesses are not necessarily the same.

[0079] This embodiment is similar to Embodiment 1 in terms of structure and process flow. The most important difference is that the functionalized metal hole 6 in this embodiment includes a through-metal hole and a dielectric-barrier RF via 30. The dielectric-barrier RF via 30 is etched-exempted from some material layers of the multi-layer heterogeneous bonding wafer. The manufacturing process is more complex than that of Embodiment 1 and involves double-sided alignment etching. By fabricating alignment marks on the front and back sides of the wafer, such as alignment vias, high-precision front-back alignment can be achieved. Thus, after etching away the surface piezoelectric thin film on the front side, multi-layer materials can be etched on the back side while controlling the etching recipe and time well.

[0080] Based on the process of Embodiment 1, steps 15 to 19 are modified. The process of the modified part in this embodiment is as follows:

[0081] 15) A soft mask material is fabricated on the surfaces of the front and back piezoelectric thin film layers. In this embodiment, the photoresist HSQ is used, and holes to be etched are fabricated after photolithography and development.

[0082] 16) Use an Ar ion etcher to etch the front and back thin film layers including the first and second piezoelectric thin film layers and the second isolation layer. Adjust the voltage and gas atmosphere of the Ar ions, control the etching depth of the Ar ions well, and stop etching when reaching the specified depth. Control the sidewall angle of the hole etching to make the sidewall etching close to a vertical angle.

[0083] 17) Etch the first absorption layer 11 of polysilicon material, the second absorption layer 9, and the intermediate substrate layer 10 of high-resistivity silicon material from the back using a mature TSV process, and ultrasonically clean to remove impurities in the holes;

[0084] 18) Sputter an insulating layer on the inner hole wall of the through hole. In this embodiment, a silicon oxide layer of 300 nm is sputtered, a metal Ti layer of 300 nm is sputtered and deposited, and an electroplating seed layer of Cu of 3000 nm is electroplated. In this embodiment, a sputtering machine tool with an aspect ratio coverage ability greater than 5:1 is selected to achieve uniform coverage of the hole wall insulating layer, adhesion layer, and electroplating seed layer;

[0085] 19) Electroplate functionalized metal holes. In this embodiment, the electroplating solution formulation and the distribution of the electroplating potential are adjusted to make the metal copper in the through holes and blind holes solidly filled.

[0086] It should be particularly noted that the content and exemplary embodiments herein are only used to illustrate the technical solutions of this patent, but the implementation manners of this patent are not limited by the above content. Any changes, modifications, substitutions, combinations, etc. made without departing from the innovative essence and principle of this patent are included in the protection scope of this patent. For those skilled in the art, the specific meanings of the above terms in the patent can be understood according to specific circumstances.

Claims

1. A multi-die stacked radio frequency device, characterized in that: It includes a first bare chip and multiple filter bare chips, the filter bare chip is coupled to the front side of the first bare chip, and a signal lead is made on the back side of the first bare chip opposite to the coupling surface. The first bare chip includes a multi-layer heterogeneous bonding substrate, a functionalized metal hole, a wafer-level package, and at least one surface acoustic wave filter made on the front and back sides of the first bare chip. The functionalized metal hole includes at least one of a through-type conductive hole and / or a dielectric barrier type RF conductive hole. The surface acoustic wave filter communicates RF signals through the functionalized metal hole.

2. A multi-die stacked radio frequency device according to claim 1, characterized in that: The upper and lower surfaces of the through-type via are made into interconnection patterns to form a three-dimensional spiral inductor, and the dielectric barrier type radio frequency via is made into a dielectric layer to form a low-loss capacitor.

3. The multi-die stacked radio frequency device according to claim 2, characterized in that: The medium in the dielectric-barrier RF via hole may be any layer in a multi-layer heterogeneous bonding substrate, and the thickness of the medium in the dielectric-barrier RF via hole is not greater than the thickness of the dielectric layer.

4. The multi-die stacked radio frequency device according to claim 1, characterized in that: The front and back sides of the first bare chip include surface acoustic wave filters, coupling sites of multiple filter bare chips, metal interconnection lines and organic high polymers. The coupling sites and the first surface acoustic wave filter transmit signals to the metallized holes through the first interconnection metal lines.

5. The multi-die stacked radio frequency device according to claim 4, characterized in that: The organic high polymer constructs a cavity in the area where the surface acoustic wave resonator is located and seals the resonator. The wafer-level packaging includes the construction of the cavity above the resonator by the organic high polymer and the UBM production of the wafer coupling site.

6. The multi-die stacked radio frequency device according to claim 4, characterized in that: The coupling sites of the multiple filter bare chips overlap with the functionalized metal holes on the first bare chip, and are connected and conducted through metal interconnects without overlapping. The area of ​​the bare chip coupling sites is 1-3 times the area of ​​the functionalized metal holes.

7. The multi-die stacked radio frequency device according to claim 1, characterized in that: The coupling method of the filter bare chip and the first bare chip includes metal ball implantation flip-up, metal bump-metal bump bonding, and electroplated metal column-pad flip-chip reflow.

8. A multi-die stacked radio frequency device according to any one of claims 1 to 7, characterized in that: The filter die includes one or more of a surface acoustic wave filter, a bulk acoustic wave filter, an integrated passive filter, a low temperature co-fired ceramic filter, and a millimeter wave filter.

9. A multi-die stacked radio frequency device according to any one of claims 1 to 7, characterized in that: The multilayer heterogeneous bonding substrate comprises a first thin film piezoelectric layer and a second thin film piezoelectric layer, a first isolation layer and a second isolation layer, a first absorption layer and a second absorption layer, and an intermediate substrate layer, the material properties and material parameters of which are independent of each other.

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