Digital-analog hybrid sip structure based on software radio architecture

Abstract

The utility model discloses a digital-analog hybrid sip structure based on a software radio architecture, which relates to the technical field of electronics, and comprises a tube shell adopting a ceramic substrate double-sided design; wherein an SPI Flash is arranged on the TOP surface through lead bonding, and a multifunctional radio frequency chip and a PSOC chip are arranged on the TOP surface in an inverted manner; a DRAM (Dynamic Random Access Memory) chip is arranged on the Bottom surface through lead bonding; the SPI Flash, the DRAM chip and the multifunctional radio frequency chip are all connected with the PSOC chip; in the digital-analog hybrid sip structure, a software radio processing architecture of a PSOC chip and a multifunctional radio frequency chip is adopted, and a two-transmitting and three-receiving channel is established; the digital-analog hybrid system solves the problems that a conventional digital-analog hybrid system is large in overall size, poor in flexibility, single in use environment and the like, and meets the requirements of light weight, miniaturization and high reliability.

Description

Technical Field

[0001] The utility model relates to the field of electronic technology, and particularly relates to a digital-analog hybrid SIP structure based on a software radio architecture. Background Art

[0002] The statements in this section only provide background information related to the present disclosure and may not constitute prior art.

[0003] With the rapid development of modern communication systems, traditional digital-analog hybrid processing systems use FR4 circuit boards as carriers, and integrate ADC, DAC, FLASH, FPGA, and other resistor-capacitor components on the FR4 circuit board by means of manual soldering or reflow soldering. Although this method is simple, the overall volume of the machine is large, the usage environment is single, and the integration degree is low, which does not meet the current requirements of light miniaturization and high reliability.

[0004] SIP technology can integrate active and passive circuits with different functions, different digital circuits, radio frequency circuits, etc. into a single structural housing, with many advantages such as short R & D cycle, flexible design, small size, high integration degree, etc. Secondly, compared with traditional instrument function systems, computer programming is more convenient to implement functions such as data analysis, processing, storage, and display, and the software design function modules have high stability, are not affected by the external environment, and have strong flexibility and reliability. Therefore, developing a digital-analog hybrid SIP based on a software radio architecture conforms to the trend of electronic development. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a digital-analog hybrid SIP structure based on a software radio architecture for the problems of the large overall size, poor flexibility, and single usage environment of the current digital-analog hybrid system. It uses a ceramic CCGA504 package, a double-sided double-chamber design, and integrates devices such as radio frequency transceiver chips, PSOC chips, and memories. It not only reduces the size of the overall package, reduces the packaging and heat dissipation risks, but also can realize multiple functions such as radio frequency transceiver wireless communication, Glink bus communication, 485 / 422 communication, Ethernet communication, general-purpose IO, and comprehensive processing, thus solving the above problems, meeting the requirements of light miniaturization and high reliability, and being convenient for wide use in engineering.

[0006] The technical solution of the utility model is as follows:

[0007] A digital-analog hybrid SIP structure based on a software-defined radio architecture, comprising: a package, the package adopting a double-sided design of a ceramic substrate; wherein, an SPI Flash is placed on the TOP surface through wire bonding, and a multi-functional radio frequency chip and a PSOC chip are placed through flip-chip; a DRAM chip is placed on the Bottom surface through wire bonding; the SPI Flash, the DRAM chip, and the multi-functional radio frequency chip are all connected to the PSOC chip; inside the digital-analog hybrid SIP structure, a software-defined radio processing architecture of a PSOC chip + a multi-functional radio frequency chip is adopted to establish a two-transmit and three-receive channel.

[0008] Further, two 16-bit DRAM chips are spliced into a 32-bit operating memory and mounted on the PS of the PSOC chip to form a memory with a data bit width of 32 bits; another two 16-bit DRAM chips are spliced into a 32-bit operating memory and mounted on the PL of the PSOC chip to form a memory with a data bit width of 32 bits; the SPI Flash serves as the program memory of the PSOC chip and is used to store the configuration program of the PSOC chip.

[0009] Further, inside the digital-analog hybrid SIP structure, it further comprises: a clock; the clock includes: two types of clocks, namely a PSOC clock and a radio frequency transceiver clock.

[0010] Further, the PSOC clock includes:

[0011] 1 PS input clock, 1 PL input clock, 1 PL DDR3 input clock, and 4 GTX input clocks. The 7 clocks of the PSOC chip are separately led out to the external pins of the SiP.

[0012] Further, the radio frequency transceiver clock includes:

[0013] 1 reference clock input, and this clock is led out to the external pins of the SiP.

[0014] Further, the external functional interfaces of the digital-analog hybrid SIP structure include:

[0015] 16 GTX high-speed interfaces, 1 Ethernet interface, 1 485 / 422 serial port, 60 GPIOs, 2 radio frequency transmissions, and 3 radio frequency receptions.

[0016] Further, the external debugging interfaces of the digital-analog hybrid SIP structure include:

[0017] The JTAG debugging interfaces of the PS and PL of the PSOC chip, the PSOC mode selection interface, the PSOC configuration interface, and the clock output interface of the multi-functional radio frequency chip.

[0018] Further, both the external functional interfaces and the external debugging interfaces are led out to the external pins of the package.

[0019] Further, the model number of the PSOC chip is: FMQL45T900; the model number of the multi-functional radio frequency chip is: CX9261S; the model number of the SPI Flash is: JFM25QL256; the model number of the DRAM chip is: SM41J128M16M.

[0020] Further, the package is drilled in any layer interconnection manner; the via pad is 75μm, the aperture is 50μm, the minimum line width and line spacing are 50μm / 50μm, and the gold wire diameter is 18μm or 25μm.

[0021] Compared with the existing technology, the beneficial effects of the present utility model are:

[0022] A digital-analog hybrid SIP structure based on a software radio architecture, using a ceramic CCGA504 package, with a double-sided double-chamber design, integrating devices such as radio frequency transceiver chips, PSOC, and memories. It not only reduces the size of the overall package, reduces the packaging and heat dissipation risks, but also can realize various functions such as radio frequency transceiver wireless communication, Glink bus communication, 485 / 422 communication, Ethernet communication, general-purpose IO, and comprehensive processing. It solves the problems of large size, poor flexibility, and single use environment of the current digital-analog hybrid system, and meets the requirements of light miniaturization and high reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the system composition inside the SIP;

[0024] Figure 2 It is a circuit block diagram of the memory inside the SIP;

[0025] Figure 3 It is a schematic side structure diagram of the partial sealing scheme of the double-sided pendulum;

[0026] Figure 4 It is a TOP layout diagram of the package design;

[0027] Figure 5 It is a BOTTOM layout of the package design;

[0028] Figure 6 It is a dimension diagram of the CCGA504 package. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0030] The features and performance of the present utility model will be further described in detail below in conjunction with the embodiments.

[0031] Embodiment 1

[0032] Please refer to Figure 1 and Figure 3 , a digital-analog hybrid SIP structure based on a software radio architecture, comprising: a package shell, the package shell adopting a double-sided design of a ceramic substrate; wherein, an SPI Flash is placed on the TOP surface by wire bonding, and a multi-functional radio frequency chip and a PSOC chip are placed by flip-chip; a DRAM chip is placed on the Bottom surface by wire bonding; the SPI Flash, the DRAM chip, and the multi-functional radio frequency chip are all connected to the PSOC chip; inside the digital-analog hybrid SIP structure, a software radio processing architecture of a PSOC chip + a multi-functional radio frequency chip is adopted to establish a two-transmit and three-receive channel;

[0033] It should be noted that the SIP package adopted in this embodiment is a high-temperature ceramic package, adopting a CCGA444 package form, with a pin pitch of 1.0 mm, double-sided component placement, and the final package size is 34 mm × 34 mm × 6.92 mm, as shown in Figure 6 ;

[0034] It should also be noted that, as shown in Figure 4 , the TOP surface also includes 127 ceramic resistors and capacitors in 0402 packages, and as shown in Figure 5 , the Bottom surface also includes 12 ceramic resistors and capacitors in 0402 packages

[0035] In this embodiment, specifically, as shown in Figure 2As shown in the figure, two 16-bit DRAM chips are spliced into a 32-bit running memory and mounted on the PS of the PSOC chip to form a memory with a data width of 32 bits; another two 16-bit DRAM chips are spliced into a 32-bit running memory and mounted on the PL of the PSOC chip to form a memory with a data width of 32 bits; the SPI Flash serves as the program memory of the PSOC chip and is used to store the configuration program of the PSOC chip.

[0036] In this embodiment, specifically, inside the digital-analog hybrid sip structure, there is also: a clock; the clock includes two types: the PSOC clock and the radio frequency transceiver clock.

[0037] Among them, the PSOC clock includes:

[0038] 1 PS input clock, 1 PL input clock, 1 PL DDR3 input clock, and 4 GTX input clocks. The 7 clocks of the PSOC chip are separately led out to the external pins of the SiP;

[0039] The radio frequency transceiver clock includes:

[0040] 1 reference clock input, and this clock is led out to the external pins of the SiP.

[0041] In this embodiment, specifically, the external functional interfaces of the digital-analog hybrid sip structure include:

[0042] 16 GTX high-speed interfaces, 1 Ethernet interface, 1 485 / 422 serial port, 60 GPIOs, 2 radio frequency transmissions, and 3 radio frequency receptions.

[0043] In this embodiment, specifically, the external debugging interfaces of the digital-analog hybrid sip structure include:

[0044] The JTAG debugging interfaces of the PS and PL of the PSOC chip, the PSOC mode selection interface, the PSOC configuration interface, the clock output interface of the multifunctional radio frequency chip, etc.

[0045] In this embodiment, specifically, when designing the above interfaces, they are all led out to the external pins of the package.

[0046] In this embodiment, specifically, the model of the PSOC chip is: FMQL45T900; the model of the multifunctional radio frequency chip is: CX9261S; the model of the SPI Flash is: JFM25QL256; the model of the DRAM chip is: SM41J128M16M.

[0047] In this embodiment, it should also be noted that the package is drilled in any layer interconnection manner; the upper surface is equipped with FLASH, PSOC, and CX9261S chips, and the lower surface of the ceramic package is a DRAM chip; the via pad is 75μm, the aperture is 50μm, the minimum line width and line pitch are 50μm / 50μm, and the gold wire diameter is 18μm or 25μm.

[0048] The above-described embodiments only represent the specific implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation of the protection scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the technical solution of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application.

[0049] This background art section is provided to generally present the context of the present utility model. The work of the currently named inventors, to the extent described in this background art section, and aspects of the work that do not constitute prior art at the time of filing this application are neither expressly nor impliedly admitted to be prior art of the present utility model.

Claims

1. A digital-analog hybrid SIP structure based on software radio architecture, characterized in that: include: The tube shell adopts a double-sided design of a ceramic substrate; wherein, the TOP surface is provided with an SPI Flash by wire bonding, and a multi-function RF chip and a PSOC chip are placed by flip-chip; the Bottom surface is provided with a DRAM chip by wire bonding; the SPI Flash, DRAM chip, and multi-function RF chip are all connected to the PSOC chip; within the digital-analog hybrid SIP structure, a software radio processing architecture of a PSOC chip + a multi-function RF chip is adopted to establish two-transmit and three-receive channels.

2. According to claim 1, a digital-analog hybrid SIP structure based on software radio architecture is characterized in that: Two 16-bit DRAM chips are spliced ​​into a 32-bit running memory and mounted on the PS of the PSOC chip, forming a memory with a data bit width of 32 bits; another two 16-bit DRAM chips are spliced ​​into a 32-bit running memory and mounted on the PL of the PSOC chip, forming a memory with a data bit width of 32 bits; SPIFlash is used as the program memory of the PSOC chip to store the configuration program of the PSOC chip.

3. According to claim 1, a digital-analog hybrid SIP structure based on software radio architecture is characterized in that: The digital-analog hybrid SIP structure also includes: a clock; the clock includes two types: a PSOC clock and a radio frequency transceiver clock.

4. The digital-analog hybrid SIP structure based on software radio architecture according to claim 3 is characterized in that: PSOC clock, including: 1 PS input clock, 1 PL input clock, 1 PL DDR3 input clock and 4 GTX input clocks. The 7 clocks of the PSOC chip are individually brought out to the SiP external pins.

5. The digital-analog hybrid SIP structure based on software radio architecture according to claim 3 is characterized in that: RF transceiver clocks, including: 1 reference clock input, which is led out to the SiP external pin.

6. A digital-analog hybrid SIP structure based on software radio architecture according to claim 5, characterized in that: The external functional interface of the digital-analog hybrid SIP structure includes: 16-channel GTX high-speed interface, 1-channel Ethernet interface, 1-channel 485 / 422 serial port, 60-channel GPIO, 2-channel RF transmission, and 3-channel RF reception.

7. The digital-analog hybrid SIP structure based on software radio architecture according to claim 6 is characterized in that: The external debugging interface of the digital-analog hybrid SIP structure includes: JTAG debugging interface of PS and PL of PSOC chip, PSOC mode selection interface, PSOC configuration interface, and clock output interface of multi-function RF chip.

8. The digital-analog hybrid SIP structure based on software radio architecture according to claim 7 is characterized in that: The external functional interface and the external debugging interface are both led out to the external pins of the tube shell.

9. The digital-analog hybrid SIP structure based on software radio architecture according to claim 1, characterized in that: The model of PSOC chip is: FMQL45T900; the model of multi-function RF chip is: CX9261S; the model of SPI Flash is: JFM25QL256; the model of DRAM chip is: SM41J128M16M.

10. The digital-analog hybrid SIP structure based on software radio architecture according to claim 1, characterized in that: The shell and tube are drilled in an arbitrary layer interconnection mode; the via pad is 75μm, the aperture is 50μm, the minimum line width and line spacing is 50μm / 50μm, and the gold wire diameter is 18μm or 25μm.

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