Lower computer testing tool

Abstract

The utility model discloses a lower computer testing tool which comprises an upper computer and a lower computer testing module, the upper computer is electrically connected with a central processing unit, the central processing unit is electrically connected with the lower computer, and corresponding detection points are reserved on the lower computer. Detection points of the lower computer are electrically connected with a corresponding analog signal detection unit, a square wave signal detection unit, a sine wave signal detection unit, a polymorphic signal detection unit, a delay signal detection unit and an IO detection unit. The signal output ends of the analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit, the polymorphic signal detection unit, the delay signal detection unit and the IO detection unit are electrically connected with the input end of the A / D conversion module, the output end of the A / D conversion module is electrically connected with the central processing unit, and the A / D conversion module converts analog signals into digital signals. The central processing unit processes the received signals and then feeds the signals back to the upper computer, and the upper computer displays the signals.

Description

Technical Field

[0001] The utility model belongs to the technical field of lower computer detection, and relates to a lower computer test tooling. Background Art

[0002] In the prior art, the lower computer is an important intelligent component along the coal mine underground monitoring system. The lower computer is used for signal input detection and output control. Therefore, the lower computer needs to be tested before use. The existing lower computer test technology is in a semi-automatic mode. The existing test instruments can only complete simple short-circuit and open-circuit tests in the lower computer circuit; the function and performance tests of the lower computer can only be completed manually. The deficiencies of this test method are long test time, artificial test errors, inability to record the intermediate test process, the test results are handwritten by the testers, etc., and the accuracy of the test results is not high. Summary of the Invention

[0003] In view of this, the purpose of the utility model is to provide a more convenient, intuitive and accurate lower computer test tooling.

[0004] To achieve the above purpose, the utility model provides the following technical solutions:

[0005] A lower computer test tooling includes an upper computer and a lower computer test module. The upper computer is electrically connected to a central processor, and the central processor is electrically connected to the lower computer. The lower computer has corresponding detection points. The detection points of the lower computer are respectively electrically connected to corresponding analog signal detection units, square wave signal detection units, sine wave signal detection units, multi-state signal detection units, delay signal detection units and IO detection units. The signal output ends of the analog signal detection units, square wave signal detection units, sine wave signal detection units, multi-state signal detection units, delay signal detection units and IO detection units are respectively electrically connected to the input end of an A / D conversion module. The output end of the A / D conversion module is electrically connected to the central processor. The A / D conversion module converts the analog signal into a digital signal and transmits it to the central processor. The central processor processes the received signal and then feeds it back to the upper computer for display.

[0006] Further, the analog signal detection unit includes a relay J1. Resistor R152 and resistor R267 are in parallel. The pin 4 of the relay J1 is connected to one end of the parallel connection of resistor R152 and resistor R267. Resistor R5 and resistor R268 are in parallel. The other end of the parallel connection of resistor R152 and resistor R267 is connected to one end of the parallel connection of resistor R5 and resistor R268. The other end of the parallel connection of resistor R5 and resistor R268 is connected to the pin 4 of the relay J2 and one end of resistor R32. The other end of resistor R32 is connected to the pin 5 of the relay J2 and then grounded to GND; the pin 3 of the relay J1 is connected to the power supply VDD, the pin 6 of the relay J1 is connected to the pin REF, and the pin 1 of the relay J1 is connected to the power supply; resistor R265 and resistor R151 are in parallel. The pin 5 of the relay J1 is connected to one end of the parallel connection of resistor R265 and resistor R151. Resistor R74 and resistor R266 are in parallel. The other end of the parallel connection of resistor R265 and resistor R151 is connected to one end of the parallel connection of resistor R74 and resistor R266. The other end of the parallel connection of resistor R74 and resistor R266 is connected to the pin 4 of the relay J3 and one end of resistor R33. The other end of resistor R33 is connected to the pin 5 of the relay J3; the pin 3 and pin 6 of the relay J3 are respectively connected to the pin 3 and pin 6 of the relay J2; the pin 8 of the relay J1 is connected to the positive electrode of the diode D1 and then connected to one end of the collector of the triode Q3. The emitter of the triode Q3 is grounded to GND. The base of the triode Q3 is connected to one end of resistor R20. The other end of resistor R20 is connected to the pin P-ON; the pin 8 of the relay J3 is connected to the positive electrode of the diode D6 and then connected to one end of the collector of the triode Q6. The emitter of the triode Q6 is grounded to GND. The base of the triode Q6 is connected to one end of resistor R47. The other end of resistor R47 is connected to the pin A2.

[0007] Further, the square wave signal detection unit includes a multiplex comparator U15 and a multiplex comparator U17. The pin 5 of the multiplex comparator U15 is connected to the pin 2 of the multiplex comparator U15, one end of the capacitor C66, and the pin 5 of U17. The pin 4 of U15 is connected to the other end of the capacitor C66 and the pin 3 of the multiplex comparator U17. The pin 2 of the multiplex comparator U15 is also connected to one end of the capacitor C67 and then grounded to GND. The other end of the capacitor C67 is connected to the pin 3 of the multiplex comparator U15 and then connected to the power supply. The pins 1 and 2 of the multiplex comparator U17 are connected and then connected to one end of the resistor R121. The other end of the resistor R121 is connected to the non-inverting input terminal of the operational amplifier U8.4. The pin 4 of the multiplex comparator U17 is connected to one end of the capacitor C70 and then connected to the power supply. The other end of the capacitor C70 is connected to one end of the resistor R118. The other end of the resistor R118 is connected to the inverting input terminal of the operational amplifier U8.4, the capacitor C75, and one end of the resistor R109. The other ends of the capacitor C75 and the resistor R109 are connected and then connected to the output terminal of the operational amplifier U8.4 and one end of the resistor R119. The other end of the resistor R119 is connected to the base of the triode Q20. The collector of the triode Q20 is connected to the output port out. The emitter of the triode Q20 is connected to one end of the resistor R123. The other end of the resistor R123 is connected to the positive electrode of the diode D53, one end of the resistor R143, and the output terminal of the operational amplifier U4.1. The negative electrode of the diode D53 and the other end of the resistor R143 are connected and then connected to the 3.3V power supply. The positive power supply terminal of the operational amplifier U4.1 is connected to one end of the resistor R140 and one end of the capacitor C10 and then connected to the 5V power supply. The other end of the capacitor C10 is grounded to GND. The other end of the resistor R140 is connected to the inverting input terminal of the operational amplifier U4.1 and one end of the resistor R142 and then grounded to GND. The other end of the resistor R142 is connected to the negative power supply terminal of the operational amplifier U4.1 and one end of the resistor R141 and then grounded to GND. The other end of the resistor R141 is connected to the non-inverting input terminal of the operational amplifier U4.1 and then connected to the pin A1. The output terminal of the operational amplifier U4.2 is connected to one end of the resistor R154 and the positive electrode of the diode D52 and then leads out the output terminal to output the square wave signal. The other end of the resistor R154 and the negative electrode of the diode D52 are connected and then connected to the 3.3V power supply. The non-inverting input terminal of the operational amplifier U4.2 is connected to one end of the resistor R153. The other end of the resistor R153 is connected to the inverting input terminal of the operational amplifier U4.1 and then grounded to GND.

[0008] Further, the sine wave signal detection unit includes a dual-channel operational amplifier U32. One end of a capacitor C96 is connected to pin 4 of the dual-channel operational amplifier U32, and the other end of the capacitor C96 is connected to pin 5 of the dual-channel operational amplifier U32, one end of a resistor R285. The other end of the resistor R285 is connected to one end of a capacitor C102, and the other end of the capacitor C102 is connected to one end of a resistor R286, pins 6 and 7 of the dual-channel operational amplifier U32, and one end of a capacitor C98. The other end of the resistor R286 is connected to the input terminal IN. The other end of the capacitor C98 is connected to one end of a resistor R289, the base of a triode Q53, and one end of a resistor R288. The other end of the resistor R289 is connected to the power supply DVCC. The other end of the resistor R288 is connected to one end of a resistor R287 and the emitter of a triode Q58 and then grounded to GND. The other end of the resistor R287 is connected to the emitter of the triode Q53. The collector of the triode Q53 is connected to one end of a resistor R296, and the other end of the resistor R296 is connected to the base of the triode Q58. The collector of the triode Q58 outputs a signal, and the collector of the triode Q58 is also connected to one end of a resistor R295, one end of a capacitor C99, and one end of a resistor R290. The other end of the resistor R290 is connected to one end of a capacitor C101, and the other end of the capacitor C101 is connected to the other end of the capacitor C99 and the other end of the resistor R295. One end of a capacitor C97 is connected to pin 8 of the dual-channel operational amplifier U32, and the other end of the capacitor C97 is grounded to GND.

[0009] Further, the polymorphic signal detection unit includes a comparator U12. One end of the pin 1 of the comparator U12 is connected to one end of a capacitor C57, the positive extreme of an electrolytic capacitor C64, the pin 1 of a relay J13, and the negative extreme of a diode D21. The other end of the capacitor C57 and the negative extreme of the electrolytic capacitor C64 are connected to the pin 2 of the comparator U12, one end of a capacitor C59, and one end of a resistor RG1 and then grounded to GND. The other end of the capacitor C59 is connected to the pin 3 of the comparator U12 and one end of a resistor R59. The other end of the resistor R59 is connected to the positive extreme of an electrolytic capacitor C65, one end of a capacitor C61, and the pins 1 and 3 of a comparator U13. The other end of the resistor RG1 is connected to the negative extreme of the electrolytic capacitor C65, the other end of the capacitor C61, the pins 2 and 4 of the comparator U13, and one end of a capacitor C60 and then grounded. The pin 5 of the comparator U13 is connected to the other end of the capacitor C60 and then outputs a signal to the A / D conversion module. The positive extreme of the diode D21 is connected to the pin 8 of the relay J13 and then connected to the collector terminal of a triode Q21. The emitter of the triode Q21 is grounded. The base of the triode Q21 is connected to one end of a resistor R117, and the other end of the resistor R117 is connected to a 10V power supply. The pin 6 of the relay J13 is connected to the positive extreme of a diode D25. The negative extreme of the diode D25 is connected to the negative extreme of a diode D26 and then connected to port C. The positive extreme of the diode D26 is connected to the pin 6 of a relay J5. The pin 1 of the relay J5 is connected to the negative extreme of a diode D16. The positive extreme of the diode D16 is connected to the pin 8 of the relay J5 and the collector of a triode Q28. The emitter of the triode Q28 is grounded. The base of the triode Q28 is connected to one end of a resistor R9, and the other end of the resistor R9 is connected to a 10V power supply.

[0010] Further, the delay signal detection unit includes an operational amplifier U26.1. The input signal terminal is connected to one end of a resistor R255 and the inverting input terminal of the operational amplifier U26.1. The non-inverting input terminal of the operational amplifier U26.1 is connected to one end of a resistor R252 and one end of a resistor R253. The other end of the resistor R252 is connected to a 3.3V power supply. The other end of the resistor R253 is connected to the other end of the resistor R255 and the negative power supply terminal of the operational amplifier U26.1 and then grounded. The positive power supply terminal of the operational amplifier U26.1 is connected to one end of a capacitor C92 and then connected to a 10V power supply. The other end of the capacitor C92 is grounded. The output terminal of the operational amplifier U26.1 is connected to one end of a resistor R254 and the positive extreme of a diode D54 and then outputs a signal to the A / D conversion module. The other end of the resistor R254 is connected to the negative extreme of the diode D54 and then connected to a 3.3V power supply.

[0011] Further, the IO detection unit includes an operational amplifier U2.2, whose input terminal IN is connected to one end of a resistor R43; the other end of the resistor R43 is connected to the non-inverting input terminal of the operational amplifier U2.2 and one end of a resistor R47; the other end of the resistor R47 is connected to one end of a resistor R20, one end of a resistor R30, and the emitter of a triode Q41, and then grounded to GND; the other end of the resistor R20 is connected to the inverting input terminal of the operational amplifier U2.2 and one end of a resistor R77; the other end of the resistor R77 is connected to a 10V power supply; the other end of the resistor R30 is connected to the output terminal of the operational amplifier U2.2, one end of a resistor R12, and one end of a resistor R124; the other end of the resistor R12 is connected to one end of a resistor R84 and then connected to a 3.3V power supply; the other end of the resistor R124 is connected to the base of the triode Q41; the collector of the triode Q41 is connected to the other end of the resistor R84 and then outputs a signal to the A / D conversion module.

[0012] The beneficial effects of the present utility model are as follows:

[0013] The present utility model can shorten the test time, improve the test efficiency; eliminate the human test error; completely record the intermediate test process; and automatically save the test results. Description of the Drawings

[0014] The drawings constituting a part of the present utility model are used to provide a further understanding of the present utility model. The schematic embodiments and descriptions thereof of the present utility model are used to explain the present utility model and do not constitute an improper limitation to the present utility model. In the drawings:

[0015] Figure 1 is the working principle diagram of the embodiment of the present utility model;

[0016] Figure 2 is the circuit diagram of the analog signal detection unit described in the embodiment of the present utility model;

[0017] Figure 3 is the circuit diagram of the square wave signal detection unit described in the embodiment of the present utility model;

[0018] Figure 4 is the circuit diagram of the sine wave signal detection unit described in the embodiment of the present utility model;

[0019] Figure 5 is the circuit diagram of the polymorphic signal detection unit described in the embodiment of the present utility model;

[0020] Figure 6 is the circuit diagram of the delay signal detection unit described in the embodiment of the present utility model;

[0021] Figure 7 is the circuit diagram of the IO detection unit described in the embodiment of the present utility model. Detailed Implementation Modes

[0022] It should be noted that, without conflict, the embodiments in the present utility model and the features in the embodiments can be combined with each other.

[0023] In the description of the present utility model, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present utility model. In addition, the terms "first", "second", etc. are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "a plurality" is two or more.

[0024] In the description of the present utility model, it should be noted that, unless otherwise clearly specified and limited, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood through specific circumstances.

[0025] The present utility model will be described in detail below with reference to the drawings and in combination with the embodiments.

[0026] Such as Figure 1As shown in the figure, a lower computer test tooling includes an upper computer and a lower computer test module. The upper computer is electrically connected to a central processing unit, and the central processing unit is electrically connected to the lower computer. The lower computer has corresponding detection points, and the detection points of the lower computer are respectively electrically connected to a corresponding analog signal detection unit, a square wave signal detection unit, a sine wave signal detection unit, a polymorphic signal detection unit, a delay signal detection unit, and an IO detection unit through metal probes. The signal output ends of the analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit, the polymorphic signal detection unit, the delay signal detection unit, and the IO detection unit are respectively electrically connected to the input end of an A / D conversion module. The output end of the A / D conversion module is electrically connected to the central processing unit. The analog signal detection unit, the square wave signal detection unit, the sine wave signal detection unit, the polymorphic signal detection unit, the delay signal detection unit, and the IO detection unit respectively convert analog signals into digital signals through the A / D conversion module and transmit them to the central processing unit. The central processing unit processes the received signals and then feeds them back to the upper computer for display.

[0027] As Figure 2 shown, the analog signal detection unit includes a relay J1, resistors R152 and R267 are in parallel. The pin 4 of the relay J1 is connected to one end of the parallel connection of the resistors R152 and R267. Resistors R5 and R268 are in parallel. The other end of the parallel connection of the resistors R152 and R267 is connected to one end of the parallel connection of the resistors R5 and R268. The other end of the parallel connection of the resistors R5 and R268 is connected to the pin 4 of the relay J2 and one end of the resistor R32. The other end of the resistor R32 is connected to the pin 5 of the relay J2 and then grounded to GND.

[0028] The pin 3 of the relay J1 is connected to the power supply VDD, the pin 6 of the relay J1 is connected to the pin REF, and the pin 1 of the relay J1 is connected to a 5V power supply. Resistors R265 and R151 are in parallel. The pin 5 of the relay J1 is connected to one end of the parallel connection of the resistors R265 and R151. Resistors R74 and R266 are in parallel. The other end of the parallel connection of the resistors R265 and R151 is connected to one end of the parallel connection of the resistors R74 and R266. The other end of the parallel connection of the resistors R74 and R266 is connected to the pin 4 of the relay J3 and one end of the resistor R33. The other end of the resistor R33 is connected to the pin 5 of the relay J3. The pins 3 and 6 of the relay J3 are respectively connected to the pins 3 and 6 of the relay J2.

[0029] The pin 8 of the relay J1 is connected to the positive pole of the diode D1 and then connected to one end of the collector of the triode Q3. The emitter of the triode Q3 is grounded to GND. The base of the triode Q3 is connected to one end of the resistor R20, and the other end of the resistor R20 is connected to the pin P-ON.

[0030] Pin 8 of relay J3 is connected to the positive electrode of diode D6 and then connected to one end of the collector of triode Q6. The emitter of triode Q6 is grounded to GND. The base of triode Q6 is connected to one end of resistor R47, and the other end of resistor R47 is connected to pin A2. Pin A2 is the input port of the analog signal detection unit. The measured analog signal of the lower computer is output and input to the analog signal detection unit from pin A2. The negative electrode of diode D6 is connected to pin 1 of relay J3 and then outputs the analog signal to the A / D conversion module.

[0031] As Figure 3 shown, the square wave signal detection unit includes multi-channel comparator U15 and multi-channel comparator U17. Pin 5 of multi-channel comparator U15 is connected to pin 2 of multi-channel comparator U15, one end of capacitor C66, and pin 5 of multi-channel comparator U17. Pin 4 of multi-channel comparator U15 is connected to the other end of capacitor C66 and pin 3 of multi-channel comparator U17. Pin 2 of multi-channel comparator U15 is also connected to one end of capacitor C67 and then grounded to GND. The other end of capacitor C67 is connected to pin 3 of multi-channel comparator U15 and then connected to the power supply of 3.3V voltage.

[0032] Pins 1 and 2 of multi-channel comparator U17 are connected and then connected to one end of resistor R121. The other end of resistor R121 is connected to the non-inverting input terminal of operational amplifier U8.4. Pin 4 of multi-channel comparator U17 is connected to one end of capacitor C70 and then connected to the voltage of the 3.3V power supply. The other end of capacitor C70 is connected to one end of resistor R118. The other end of resistor R118 is connected to the inverting input terminal of operational amplifier U8.4, capacitor C75, and one end of resistor R109. The other ends of capacitor C75 and resistor R109 are connected and then connected to the output terminal of operational amplifier U8.4 and one end of resistor R119. The other end of resistor R119 is connected to the base of triode Q20. The collector of triode Q20 is connected to the output port out. The emitter of triode Q20 is connected to one end of resistor R123. The other end of resistor R123 is connected to the positive electrode of diode D53, one end of resistor R143, and the output terminal of operational amplifier U4.1. The negative electrode of diode D53 and the other end of resistor R143 are connected and then connected to the 3.3V power supply.

[0033] The positive power supply terminal of operational amplifier U4.1 is connected to one end of resistor R140 and one end of capacitor C10, and then connected to the 5V power supply; the other end of capacitor C10 is grounded to GND; the other end of resistor R140 is connected to the inverting input terminal of operational amplifier U4.1 and one end of resistor R142, and then grounded to GND; the other end of resistor R142 is connected to the negative power supply terminal of operational amplifier U4.1 and one end of resistor R141, and then grounded to GND; the other end of resistor R141 is connected to the non-inverting input terminal of operational amplifier U4.1 and then connected to pin A1. Pin A1 is the input of the square wave signal detection unit, and the output signal pin of the lower computer is connected to pin A1.

[0034] The output terminal of operational amplifier U4.2 is connected to one end of resistor R154 and the positive electrode of diode D52, and then the output terminal is led out to output a square wave signal; the other end of resistor R154 and the negative electrode of diode D52 are connected and then connected to the 3.3V power supply. The non-inverting input terminal of operational amplifier U4.2 is connected to one end of resistor R153, and the other end of resistor R153 is connected to the inverting input terminal of operational amplifier U4.1 and then grounded to GND.

[0035] As Figure 4 As shown, the sine wave signal detection unit includes a dual-channel operational amplifier U32. Pin 4 of the dual-channel operational amplifier U32 is connected to one end of capacitor C96. The other end of capacitor C96 is connected to pin 5 of the dual-channel operational amplifier U32, one end of resistor R285. The other end of resistor R285 is connected to one end of capacitor C102. The other end of capacitor C102 is connected to one end of resistor R286, pins 6 and 7 of the dual-channel operational amplifier U32, and one end of capacitor C98; the other end of resistor R286 is connected to the input terminal IN, and the sine wave output pin of the lower computer is connected to the input terminal IN; the other end of capacitor C98 is connected to one end of resistor R289, the base of transistor Q53, and one end of resistor R288; the other end of resistor R289 is connected to the power supply DVCC; the other end of resistor R288 is connected to one end of resistor R287 and the emitter of transistor Q58 and then grounded to GND; the other end of resistor R287 is connected to the emitter of transistor Q53; the collector of transistor Q53 is connected to one end of resistor R296, the other end of resistor R296 is connected to the base of transistor Q58, and the collector of transistor Q58 outputs a signal. The collector of transistor Q58 is also connected to one end of resistor R295, one end of capacitor C99, and one end of resistor R290; the other end of resistor R290 is connected to one end of capacitor C101, the other end of capacitor C101 is connected to the other end of capacitor C99 and the other end of resistor R295; pin 8 of the dual-channel operational amplifier U32 is connected to one end of capacitor C97, and the other end of capacitor C97 is grounded to GND.

[0036] AsFigure 5 As shown, the polymorphic signal detection unit includes a comparator U12. Pin 1 of the comparator U12 is connected to one end of a capacitor C57, the positive terminal of an electrolytic capacitor C64, pin 1 of a switch J13, and the negative terminal of a diode D21. The other end of the capacitor C57 and the negative terminal of the electrolytic capacitor C64 are connected to pin 2 of the comparator U12, one end of a capacitor C59, and one end of a resistor RG1, and then grounded to GND. The other end of the capacitor C59 is connected to pin 3 of the chip U12 and one end of a resistor R59. The other end of the resistor R59 is connected to the positive terminal of an electrolytic capacitor C65, one end of a capacitor C61, and pins 1 and 3 of a comparator U13. The other end of the resistor RG1 is connected to the negative terminal of the electrolytic capacitor C65, the other end of the capacitor C61, pins 2 and 4 of the comparator U13, and one end of a capacitor C60, and then grounded. Pin 5 of the comparator U13 is connected to the other end of the capacitor C60 and then outputs a signal to the A / D conversion module.

[0037] The positive terminal of the diode D21 is connected to pin 8 of the relay J13 and then to the collector terminal of a triode Q21. The emitter of the triode Q21 is grounded. The base of the triode Q21 is connected to one end of a resistor R117, and the other end of the resistor R117 is connected to a 10V power supply. Pin 6 of the relay J13 is connected to the positive terminal of a diode D25. The negative terminal of the diode D25 is connected to the negative terminal of a diode D26 and then connected to port C. Port C is the input port of the polymorphic signal of the lower computer, and port C is the closed signal in the polymorphic signal. Pin 5 of the relay J13 is the signal input terminal, and pin 5 of the relay J13 is the input port of the open signal in the polymorphic signal. The positive terminal of the diode D26 is connected to pin 6 of the relay J5. Pin 1 of the relay J5 is connected to the negative terminal of a diode D16. The positive terminal of the diode D16 is connected to pin 8 of the relay J5 and the collector of a triode Q28. The emitter of the triode Q28 is grounded. The base of the triode Q28 is connected to one end of a resistor R9, and the other end of the resistor R9 is connected to a 10V power supply. Pin 5 of the relay J5 is connected to port N, and port N is the input terminal of the high impedance state signal in the polymorphic signal.

[0038] As Figure 6As shown in the figure, the delay signal detection unit includes an operational amplifier U26.1. The input signal terminal is connected to one end of a resistor R255 and the inverting input terminal of the operational amplifier U26.1. The non-inverting input terminal of the operational amplifier U26.1 is connected to one end of a resistor R252 and one end of a resistor R253. The other end of the resistor R252 is connected to a 3.3V power supply. The other end of the resistor R253 is connected to the other end of the resistor R255 and the negative power supply terminal of the operational amplifier U26.1 and then grounded. The positive power supply terminal of the operational amplifier U26.1 is connected to one end of a capacitor C92 and then connected to a 10V power supply. The other end of the capacitor C92 is grounded. The output terminal of the operational amplifier U26.1 is connected to one end of a resistor R254 and the positive terminal of a diode D54 and then outputs a signal to the A / D conversion module. The other end of the resistor R254 is connected to the negative terminal of the diode D54 and then connected to a 3.3V power supply.

[0039] As Figure 7 shown in the figure, the IO detection unit includes an operational amplifier U2.2. The input terminal IN is connected to one end of a resistor R43. The other end of the resistor R43 is connected to the non-inverting input terminal of the operational amplifier U2.2 and one end of a resistor R47. The other end of the resistor R47 is connected to one end of a resistor R20, one end of a resistor R30, and the emitter of a triode Q41 and then grounded to GND. The other end of the resistor R20 is connected to the inverting input terminal of the operational amplifier U2.2 and one end of a resistor R77. The other end of the resistor R77 is connected to a 10V power supply. The other end of the resistor R30 is connected to the output terminal of the operational amplifier U2.2, one end of a resistor R12, and one end of a resistor R124. The other end of the resistor R12 is connected to one end of a resistor R84 and then connected to a 3.3V power supply. The other end of the resistor R124 is connected to the base of the triode Q41. The collector of the triode Q41 is connected to the other end of the resistor R84 and then outputs a signal to the A / D conversion module.

[0040] The working principle of the present utility model;

[0041] The lower computer test tooling mainly completes the test of the overall functions of the lower computer. Each function module of the lower computer has corresponding test points, and these test points are connected to the corresponding signal detection units of the lower computer test module through metal probes. The tester operates the upper computer and sends an instruction of "start testing" to the lower computer test module. After receiving the instruction, the lower computer test module starts the test. The whole test process is mainly controlled by the central processor. The central processor sets the detection timing and starts each signal detection unit step by step. After being started, the signal detection unit starts to detect the output signals of the corresponding function modules in the lower computer. After the detection is completed, the signals are converted into digital quantities through the A / D conversion module and transmitted to the central processor. After all the function detections are completed, the central processor sends the detection results to the upper computer. The upper computer displays and saves the test results.

[0042] The test results are provided below.

[0043] The test results of the analog signal are shown in Table 1

[0044] Table 1

[0045]

[0046]

[0047] The test results of the square wave signal are shown in Table 2

[0048] Table 2

[0049]

[0050] The test results of the sine wave signal are shown in Table 3

[0051]

[0052]

[0053] The above are only the preferred embodiments of the present utility model and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. A lower computer test tooling, comprising an upper computer and a lower computer test module, the upper computer is electrically connected to a central processing unit, and the central processing unit is electrically connected to the lower computer, characterized in that: The lower computer has corresponding detection points. The detection points of the lower computer are electrically connected to the corresponding analog signal detection unit, square wave signal detection unit, sine wave signal detection unit, polymorphic signal detection unit, delay signal detection unit, and IO detection unit respectively. The signal output ends of the analog signal detection unit, square wave signal detection unit, sine wave signal detection unit, polymorphic signal detection unit, delay signal detection unit, and IO detection unit are electrically connected to the input end of the A / D conversion module respectively. The output end of the A / D conversion module is electrically connected to the central processor. The A / D conversion module converts the analog signal into a digital signal and transmits it to the central processor. The central processor processes the received signal and then feeds it back to the upper computer for display.

2. The lower computer test tooling according to claim 1, characterized in that: The analog signal detection unit includes relay J1. Resistor R152 and resistor R267 are in parallel. One end of the parallel connection of relay J1's pin 4 with resistor R152 and resistor R267 is connected to one end of the parallel connection of resistor R5 and resistor R268. Resistor R5 and resistor R268 are in parallel. The other end of the parallel connection of resistor R152 and resistor R267 is connected to one end of the parallel connection of resistor R5 and resistor R268. The other end of the parallel connection of resistor R5 and resistor R268 is connected to pin 4 of relay J2 and one end of resistor R32. The other end of resistor R32 is connected to pin 5 of relay J2 and then grounded to GND. Pin 3 of relay J1 is connected to power supply VDD, pin 6 of relay J1 is connected to pin REF, and pin 1 of relay J1 is connected to the power supply. Resistor R265 and resistor R151 are in parallel. One end of the parallel connection of relay J1's pin 5 with resistor R265 and resistor R151 is connected to one end of the parallel connection of resistor R74 and resistor R266. Resistor R74 and resistor R266 are in parallel. The other end of the parallel connection of resistor R265 and resistor R151 is connected to one end of the parallel connection of resistor R74 and resistor R266. The other end of the parallel connection of resistor R74 and resistor R266 is connected to pin 4 of relay J3 and one end of resistor R33. The other end of resistor R33 is connected to pin 5 of relay J3. Pin 3 and pin 6 of relay J3 are respectively connected to pin 3 and pin 6 of relay J2. Pin 8 of relay J1 is connected to the positive pole of diode D1 and then connected to one end of the collector of triode Q3. The emitter of triode Q3 is grounded to GND. The base of triode Q3 is connected to one end of resistor R20. The other end of resistor R20 is connected to pin P-ON. Pin 8 of relay J3 is connected to the positive pole of diode D6 and then connected to one end of the collector of triode Q6. The emitter of triode Q6 is grounded to GND. The base of triode Q6 is connected to one end of resistor R47. The other end of resistor R47 is connected to pin A2.

3. The lower computer test tooling according to claim 1, characterized in that: The square wave signal detection unit includes a multiplex comparator U15 and a multiplex comparator U17. Pin 5 of the multiplex comparator U15 is connected to pin 2 of the multiplex comparator U15, one end of a capacitor C66, and pin 5 of U17. Pin 4 of U15 is connected to the other end of the capacitor C66 and pin 3 of the multiplex comparator U17; Pin 2 of the multiplex comparator U15 is also connected to one end of a capacitor C67 and then grounded to GND; The other end of the capacitor C67 is connected to pin 3 of the multiplex comparator U15 and then connected to the power supply; Pins 1 and 2 of the multiplex comparator U17 are connected and then connected to one end of a resistor R121. The other end of the resistor R121 is connected to the non-inverting input terminal of the operational amplifier U8.4; Pin 4 of the multiplex comparator U17 is connected to one end of a capacitor C70 and then connected to the power supply. The other end of the capacitor C70 is connected to one end of a resistor R118. The other end of the resistor R118 is connected to the inverting input terminal of the operational amplifier U8.4, a capacitor C75, and one end of a resistor R109. The other ends of the capacitor C75 and the resistor R109 are connected and then connected to the output terminal of the operational amplifier U8.4 and one end of a resistor R119. The other end of the resistor R119 is connected to the base of the triode Q20. The collector of the triode Q20 is connected to the output port out. The emitter of the triode Q20 is connected to one end of a resistor R123. The other end of the resistor R123 is connected to the positive electrode of a diode D53, one end of a resistor R143, and the output terminal of the operational amplifier U4.

1. The negative electrode of the diode D53 and the other end of the resistor R143 are connected and then connected to a 3.3V power supply; The positive power supply terminal of the operational amplifier U4.1 is connected to one end of a resistor R140 and one end of a capacitor C10 and then connected to a 5V power supply; The other end of the capacitor C10 is grounded to GND; The other end of the resistor R140 is connected to the inverting input terminal of the operational amplifier U4.1 and one end of a resistor R142 and then grounded to GND; The other end of the resistor R142 is connected to the negative power supply terminal of the operational amplifier U4.1 and one end of a resistor R141 and then grounded to GND; The other end of the resistor R141 is connected to the non-inverting input terminal of the operational amplifier U4.1 and then connected to pin A1; The output terminal of the operational amplifier U4.2 is connected to one end of a resistor R154 and the positive electrode of a diode D52 and then leads out an output terminal to output a square wave signal; The other end of the resistor R154 and the negative electrode of the diode D52 are connected and then connected to a 3.3V power supply; The non-inverting input terminal of the operational amplifier U4.2 is connected to one end of a resistor R153. The other end of the resistor R153 is connected to the inverting input terminal of the operational amplifier U4.1 and then grounded to GND.

4. The lower computer test tooling according to claim 1, wherein: The sine wave signal detection unit includes a dual-channel operational amplifier U32. One end of the pin 4 of the dual-channel operational amplifier U32 is connected to one end of the capacitor C96. The other end of the capacitor C96 is connected to the pin 5 of the dual-channel operational amplifier U32, one end of the resistor R285. The other end of the resistor R285 is connected to one end of the capacitor C102. The other end of the capacitor C102 is connected to one end of the resistor R286, the pin 6 and pin 7 of the dual-channel operational amplifier U32, one end of the capacitor C98. The other end of the resistor R286 is connected to the input terminal IN. The other end of the capacitor C98 is connected to one end of the resistor R289, the base of the triode Q53, one end of the resistor R288. The other end of the resistor R289 is connected to the power supply DVCC. The other end of the resistor R288 is connected to one end of the resistor R287, the emitter of the triode Q58 and then grounded to GND. The other end of the resistor R287 is connected to the emitter of the triode Q53. The collector of the triode Q53 is connected to one end of the resistor R296. The other end of the resistor R296 is connected to the base of the triode Q58. The collector of the triode Q58 outputs a signal. The collector of the triode Q58 is also connected to one end of the resistor R295, one end of the capacitor C99, one end of the resistor R290. The other end of the resistor R290 is connected to one end of the capacitor C101. The other end of the capacitor C101 is connected to the other end of the capacitor C99, the other end of the resistor R295. One end of the pin 8 of the dual-channel operational amplifier U32 is connected to one end of the capacitor C97. The other end of the capacitor C97 is grounded to GND.

5. The lower computer test tooling according to claim 1, characterized in that: The polymorphic signal detection unit includes a comparator U12. One end of the pin 1 of the comparator U12 is connected to one end of the capacitor C57, the positive terminal of the electrolytic capacitor C64, the pin 1 of the relay J13, and the negative terminal of the diode D21. The other end of the capacitor C57 and the negative terminal of the electrolytic capacitor C64 are connected to the pin 2 of the comparator U12, one end of the capacitor C59, and one end of the resistor RG1 and then grounded to GND. The other end of the capacitor C59 is connected to the pin 3 of the comparator U12 and one end of the resistor R59. The other end of the resistor R59 is connected to the positive terminal of the electrolytic capacitor C65, one end of the capacitor C61, and the pins 1 and 3 of the comparator U13. The other end of the resistor RG1 is connected to the negative terminal of the electrolytic capacitor C65, the other end of the capacitor C61, the pins 2 and 4 of the comparator U13, and one end of the capacitor C60 and then grounded. The pin 5 of the comparator U13 is connected to the other end of the capacitor C60 and then outputs a signal to the A / D conversion module. The positive terminal of the diode D21 is connected to the pin 8 of the relay J13 and then connected to the collector terminal of the triode Q21. The emitter of the triode Q21 is grounded. The base of the triode Q21 is connected to one end of the resistor R117, and the other end of the resistor R117 is connected to a 10V power supply. The pin 6 of the relay J13 is connected to the positive terminal of the diode D25. The negative terminal of the diode D25 is connected to the negative terminal of the diode D26 and then connected to the port C. The positive terminal of the diode D26 is connected to the pin 6 of the relay J5. The pin 1 of the relay J5 is connected to the negative terminal of the diode D16. The positive terminal of the diode D16 is connected to the pin 8 of the relay J5 and the collector of the triode Q28. The emitter of the triode Q28 is grounded. The base of the triode Q28 is connected to one end of the resistor R9, and the other end of the resistor R9 is connected to a 10V power supply.

6. The lower computer test tooling according to claim 1, characterized in that: The delay signal detection unit includes an operational amplifier U26.

1. The input signal terminal is connected to one end of the resistor R255 and the inverting input terminal of the operational amplifier U26.

1. The non-inverting input terminal of the operational amplifier U26.1 is connected to one end of the resistor R252 and one end of the resistor R253. The other end of the resistor R252 is connected to a 3.3V power supply. The other end of the resistor R253 is connected to the other end of the resistor R255 and the negative power supply terminal of the operational amplifier U26.1 and then grounded. The positive power supply terminal of the operational amplifier U26.1 is connected to one end of the capacitor C92 and then connected to a 10V power supply. The other end of the capacitor C92 is grounded. The output terminal of the operational amplifier U26.1 is connected to one end of the resistor R254 and the positive terminal of the diode D54 and then outputs a signal to the A / D conversion module. The other end of the resistor R254 is connected to the negative terminal of the diode D54 and then connected to a 3.3V power supply.

7. The lower computer test tooling according to claim 1, wherein: The IO detection unit includes an operational amplifier U2.2, with its input terminal IN connected to one end of a resistor R43; the other end of the resistor R43 is connected to the non-inverting input terminal of the operational amplifier U2.2 and one end of a resistor R47; the other end of the resistor R47 is connected to one end of a resistor R20, one end of a resistor R30, and the emitter of a triode Q41 and then grounded to GND; the other end of the resistor R20 is connected to the inverting input terminal of the operational amplifier U2.2 and one end of a resistor R77; the other end of the resistor R77 is connected to a 10V power supply; the other end of the resistor R30 is connected to the output terminal of the operational amplifier U2.2, one end of a resistor R12, and one end of a resistor R124; the other end of the resistor R12 is connected to one end of a resistor R84 and then connected to a 3.3V power supply; the other end of the resistor R124 is connected to the base of the triode Q41; the collector of the triode Q41 is connected to the other end of the resistor R84 and then outputs a signal to the A / D conversion module.

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