Upgrading control circuit, upgrading circuit and electronic equipment

Abstract

The utility model discloses an upgrade control circuit, upgrade circuit and electronic equipment, relates to electronic product technical field, wherein the upgrade control circuit is applied to the electronic equipment, the electronic equipment is provided with a button and a processor, the upgrade control circuit comprises a trigger control circuit, the detection end of the trigger control circuit is electrically connected with the button, and the detection end of the trigger control circuit is electrically connected with the processor. The trigger signal output end of the trigger control circuit is electrically connected with the processor, and the trigger control circuit outputs a corresponding trigger signal to the processor when detecting an upgrade control signal generated when the key is triggered by a user, so that the processor enters a downloading mode in response to the trigger signal. The utility model aims to enter an emergency downloading mode under the condition that a machine is not disassembled, complete software upgrading and problem positioning, and improve user experience.

Description

Technical Field

[0001] This application relates to the technical field of electronic devices, and particularly to an upgrade control circuit, an upgrade circuit, and an electronic device. Background Art

[0002] When upgrading software in an emergency download mode for a processor such as a CPU or other electronic products, the common practice is to trigger the processor or device to enter the emergency download mode by physically contacting specific pins (such as BOOT pins). The current implementation solutions mainly reserve some test points or jumpers on the printed circuit board (PCB). When it is necessary to force the device to boot into the download mode, technicians will use tweezers, jigs, or other tools to short-circuit these test points. Although this method is very useful for product debugging in the R & D stage and quality control on the production line, it has certain limitations. Once the device is encapsulated and assembled into the final product, users may not be able to easily access the test points on the PCB. For example, it is inconvenient or impossible to disassemble the machine to analyze problems and upgrade versions during the whole machine test and market repair stages. Summary of the Utility Model

[0003] The main purpose of the present utility model is to provide an upgrade control circuit, an upgrade circuit, and an electronic device, aiming to enter the emergency download mode without disassembling the machine, complete software upgrade and problem location, and improve the user experience.

[0004] To achieve the above object, the present utility model provides an upgrade control circuit applied to an electronic device. The electronic device is provided with a key and a processor. The upgrade control circuit includes:

[0005] A trigger control circuit, the detection end of the trigger control circuit is electrically connected to the key, the trigger signal output end of the trigger control circuit is electrically connected to the processor. When the trigger control circuit detects an upgrade control signal generated by the user triggering the key, it outputs a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters the download mode.

[0006] In an embodiment, the electronic device is provided with two keys, namely a first key and a second key; the trigger control circuit includes two trigger branches, namely a first trigger branch and a second trigger branch;

[0007] The detection end of the first trigger branch is electrically connected to the first key, the trigger signal output end of the first trigger branch is electrically connected to the processor, the detection end of the second trigger branch is electrically connected to the second key, and the trigger signal output end of the second trigger branch is electrically connected to the processor;

[0008] When the first trigger branch detects the first upgrade control signal generated by the user triggering the first button, it outputs the corresponding first trigger signal to the processor; when the second trigger branch detects the second upgrade control signal generated by the user triggering the second button, it outputs the corresponding second trigger signal to the processor, so that the processor responds to the first trigger signal and the second trigger signal and enters the download mode.

[0009] In an embodiment, the trigger control circuit further includes a logic control circuit. The first input end of the logic control circuit is electrically connected to the first trigger branch, and the second input end of the logic control circuit is electrically connected to the second trigger branch. The logic control circuit is configured to output a control signal to the processor when receiving the first trigger signal and the second trigger signal, so that the processor responds to the trigger signal and enters the download mode.

[0010] In an embodiment, the logic control circuit includes:

[0011] An AND gate circuit, the AND gate circuit includes at least two input ends, which are respectively electrically connected to the first trigger branch and the second trigger branch;

[0012] A switch circuit, the switch circuit is electrically connected to the output end of the AND gate circuit;

[0013] The AND gate circuit is configured to output a conduction signal to the switch circuit when receiving the first trigger signal and the second trigger signal, so as to output a control signal to the processor through the switch circuit.

[0014] In an embodiment, the trigger control circuit includes:

[0015] A trigger, the input end of the trigger is electrically connected to the button, and the output end of the trigger is electrically connected to the processor;

[0016] The trigger is configured to count once every time an upgrade control signal generated by the user triggering the button is received at the input end, so as to output a corresponding trigger signal to the processor when the set counting times is reached, so that the processor responds to the trigger signal and enters the download mode.

[0017] Alternatively, a timer, the input end of the timer is electrically connected to the button, and the output end of the timer is electrically connected to the processor;

[0018] The timer is configured to start timing when receiving an upgrade control signal generated by the user triggering the button, so as to output a corresponding trigger signal to the processor when the set timing duration is reached, so that the processor responds to the trigger signal and enters the download mode.

[0019] In one embodiment, the upgrade control circuit includes a power supply terminal for accessing a power supply voltage, and the first trigger branch includes:

[0020] A first switch module, a first end of the first switch module is electrically connected to the power supply terminal, a second end of the first switch module is electrically connected to a first key, and a third end of the first switch module is electrically connected to the processor;

[0021] The first switch module is configured to conduct a path between the power supply terminal and the processor when receiving a first upgrade control signal generated by the user triggering the first key, so as to output a first trigger signal to the processor;

[0022] The second trigger branch includes:

[0023] A second switch module, a first end of the second switch module is electrically connected to the power supply terminal, a second end of the second switch module is electrically connected to a second key, and a third end of the second switch module is electrically connected to the processor;

[0024] The second switch module is configured to conduct a path between the power supply terminal and the processor when receiving a second upgrade control signal generated by the user triggering the second key, so as to output a second trigger signal to the processor.

[0025] In one embodiment, the first switch module includes:

[0026] A first switch tube;

[0027] A first pull-up resistor, a first end of the first pull-up resistor is electrically connected to the power supply terminal, and a second end of the first pull-up resistor is electrically connected to a first end of the first switch tube;

[0028] A first voltage-dividing resistor, a first end of the first voltage-dividing resistor is the second end of the first switch module, and a second end of the first voltage-dividing resistor is electrically connected to a second end of the first pull-up resistor; and is configured to form a voltage-dividing circuit with the first pull-up resistor;

[0029] A first resistor, a first end of the first resistor is electrically connected to the power supply terminal, a second end of the first resistor is electrically connected to a second end of the first switch tube, and a third end of the first switch tube is grounded.

[0030] The second switch module includes:

[0031] A second switch tube;

[0032] A second pull-up resistor, a first end of the second pull-up resistor is electrically connected to the power supply terminal, and a second end of the second pull-up resistor is electrically connected to a first end of the second switch tube;

[0033] A second voltage-dividing resistor, a first end of the second voltage-dividing resistor being a second end of the second switching module, and a second end of the second voltage-dividing resistor being electrically connected to a second end of the second pull-up resistor; and being configured to form a voltage-dividing circuit with the second pull-up resistor.

[0034] A second resistor, a first end of the second resistor being electrically connected to the power supply terminal, a second end of the second resistor being electrically connected to a second end of the second switching transistor, and a third end of the second switching transistor being grounded.

[0035] In one embodiment, the upgrade control circuit further includes:

[0036] A power-on / off circuit, the power-on / off circuit being electrically connected to the trigger control circuit;

[0037] The power-on / off circuit is configured to detect a power-on / off state of the electronic device and output a state detection signal to the trigger control circuit;

[0038] The trigger control circuit is configured to, when determining that the electronic device is in a shutdown state according to the state detection signal and detecting an upgrade control signal generated by the user triggering the key, output a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters the download mode.

[0039] The present utility model provides an upgrade circuit, including a processor, a key, and the upgrade control circuit according to any one of the above.

[0040] The present utility model further provides an electronic device, including the upgrade circuit described above.

[0041] The present utility model provides an upgrade control circuit, which is applied to an electronic device. The electronic device is provided with a key and a processor. The upgrade control circuit includes a trigger control circuit. A detection end of the trigger control circuit is electrically connected to the key, and a trigger signal output end of the trigger control circuit is electrically connected to the processor. When the trigger control circuit detects an upgrade control signal generated by the user triggering the key, it outputs a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters the download mode.

[0042] In practical applications, when it is necessary to force the device to boot into the download mode, the user only needs to press a button. When the trigger circuit receives the upgrade control signal generated by the user's trigger, it will output the corresponding trigger signal to the processor. For example, the dedicated pin BOOT on the processor that indicates entering the emergency download mode will enter the emergency download mode. In this way, without disassembling the device to short-circuit the test points, the maintenance and upgrade of the device can be carried out. The user only needs to press a button to boot the device into the download mode, without the need for additional tools or professional technicians, which reduces the difficulty of entering the download mode, improves the user experience, and enhances the efficiency and convenience of device maintenance and upgrade. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on the structures shown in these drawings.

[0044] Figure 1 Schematic diagram of the circuit module of an embodiment of the upgrade control circuit of the present invention;

[0045] Figure 2 Schematic diagram of the circuit module of another embodiment of the upgrade control circuit of the present invention;

[0046] Figure 3 Schematic diagram of the circuit module of yet another embodiment of the upgrade control circuit of the present invention;

[0047] Figure 4 Schematic diagram of the circuit module of still another embodiment of the upgrade control circuit of the present invention;

[0048] Figure 5 Schematic diagram of the circuit module of another embodiment of the upgrade control circuit of the present invention;

[0049] Figure 6 Schematic diagram of the circuit module of yet another embodiment of the upgrade control circuit of the present invention;

[0050] Figure 7 Schematic diagram of the circuit module of still another embodiment of the upgrade control circuit of the present invention;

[0051] Figure 8 Schematic diagram of the circuit module of another embodiment of the upgrade control circuit of the present invention;

[0052] Figure 9 Specific circuit diagram of an embodiment of the upgrade control circuit of the present invention.

[0053] Description of the attached reference numerals:

[0054] 10. Trigger control circuit; 20. Logic control circuit; 11. First trigger branch; 12. Second trigger branch; 13. Trigger; 14. Timer; 21. AND gate circuit; 22. Switch circuit.

[0055] The realization, functional features and advantages of the present utility model will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0056] The technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0057] In addition, in the present utility model, descriptions such as "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions appears to be contradictory or unable to be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present utility model.

[0058] When upgrading software in the emergency download mode for a processor such as a CPU or other electronic products, the common practice is to trigger the processor or device to enter the emergency download mode by physically contacting specific pins (such as the BOOT pin). The current implementation solutions mainly reserve some test points or jumpers on the printed circuit board (PCB). When it is necessary to force the device to boot into the download mode, technicians will use tweezers, clamps or other tools to short-circuit these test points. Although this method is very useful for product debugging in the R & D stage and quality control on the production line, it has certain limitations. Once the device is encapsulated and assembled into the final product, users may not be able to easily access the test points on the PCB. For example, it is inconvenient or impossible to disassemble the machine to analyze problems and upgrade the version during the whole machine test and market repair stages.

[0059] It should be noted that the BOOT pin of a processor (such as a CPU) is used to control the startup behavior of the processor itself. When the processor is powered on or reset, the state of the BOOT pin determines the startup mode. Different processors have different ways of setting the startup mode, but the common ones are two states: high level (Vcc) and low level (GND). By setting the BOOT pin to a specific state (such as low level), the processor can be placed in the download mode (also known as the Bootloader mode). In the download mode, the processor will run a pre-embedded Bootloader program, which can receive new firmware and write it into the processor's flash memory through a serial interface (such as UART) or other communication methods. When the BOOT pin is set to another state (such as high level), the processor will enter the normal startup mode. In the normal startup mode, the processor will start executing the program from its internal flash memory or other preset startup locations. The BOOT pin allows users to switch and select between different startup modes, which is very important for device maintenance, upgrade, and production testing.

[0060] For this reason, referring to Figure 1 , the present utility model proposes an upgrade control circuit, which is applied to an electronic device. The electronic device is provided with a key and a processor. The upgrade control circuit includes:

[0061] A trigger control circuit 10, the detection end of the trigger control circuit 10 is electrically connected to the key, the trigger signal output end of the trigger control circuit 10 is electrically connected to the processor. When the trigger control circuit 10 detects an upgrade control signal generated by the user triggering the key, it outputs a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters the download mode.

[0062] In this embodiment, the trigger control circuit 10 can be implemented by a main controller, such as an MCU, a DSP (Digital Signal Process, digital signal processing chip), an FPGA (Field Programmable Gate Array, programmable logic gate array chip), a PLC, an SOC (System On Chip, system-level chip), etc. The electronic device includes a mobile phone, a tablet, a computer, headphones, a smart TV, a smart watch, etc.

[0063] Specifically, the trigger control circuit 10 is responsible for detecting the state change of the button. When the user presses the button, the trigger control circuit 10 will detect that the button is triggered. That is, the trigger control circuit 10 outputs a corresponding trigger signal to the processor according to the upgrade control signal generated when the button is triggered by the user, so that after receiving the trigger signal, the processor will respond to this trigger signal, and then the processor will be guided into the download mode. For example, a physical button for triggering the download mode is provided on the electronic device. The processor is a main controller with built-in flash memory and is used to execute the main functions of the device. When the trigger control circuit 10 sends a trigger signal to the BOOT pin of the processor, the processor will enter the download mode. When the button is not triggered, the detection terminal of the TC receives a high-level signal, and the processor is in the normal working mode and executes routine tasks. Among them, the processor can be implemented by using the above-mentioned main controller.

[0064] In this embodiment, the existing defined function button can be used to implement the BOOT control. For example, refer to Figure 8 The upgrade control circuit further includes: a power-on / off circuit, and the power-on / off circuit is electrically connected to the trigger control circuit 10;

[0065] The power-on / off circuit is used to detect the power-on / off state of the electronic device and output a state detection signal to the trigger control circuit 10;

[0066] The trigger control circuit 10 is configured to output a corresponding trigger signal to the processor when it is determined according to the state detection signal that the electronic device is in the shutdown state and detects the upgrade control signal generated by the button being triggered by the user, so that the processor responds to the trigger signal and enters the download mode.

[0067] In this embodiment, the power-on / off circuit can be implemented by using the above-mentioned main controller or physical / virtual buttons. When the device needs to enter the download mode, the user needs to first turn off the device by triggering a button, such as triggering the power-on / off button or the power-off button to make the device enter the power-off state. At this time, the user then triggers the physical button corresponding to the device to enter the download mode. For example, when applied to a mobile phone, this button can be the volume adjustment button (volume + or volume -), and when applied to an earphone, this button can be the play / pause button. When the user presses the power-on / off button or the power-off button, the trigger control circuit 10 determines that the electronic device is in the power-off state according to the status detection signal. At this time, when the user presses the physical button to enter the download mode, the trigger control circuit 10 will detect the upgrade control signal generated by the button being triggered by the user and output the corresponding trigger signal to the processor to make the processor enter the download mode. Only when the electronic device is in the power-off state does this button have the function of starting the processor to enter the download mode. When the electronic device is in the power-on state, this button has its original defined functions, such as volume adjustment function, play or pause function, etc. In this way, there is no need to additionally add a dedicated button for the device to enter the download mode, which does not affect the appearance of the electronic device and reduces the design cost and design difficulty.

[0068] In practical applications, maintenance personnel can easily perform software upgrades on the device on-site without the need for complex tools or professional knowledge. On the production line, testers can test the firmware update process of the device through simple button operations. Users can also update the firmware of the device themselves to obtain the latest functions or fix known problems. In this way, there is no need to short-circuit the test points by disassembling the machine. The user only needs to press a button to guide the device into the download mode without additional tools or professional technicians, reducing the difficulty of entering the download mode, improving the user experience, and the efficiency and convenience of device maintenance and upgrade.

[0069] It can be understood that when designing a dedicated button for triggering the electronic device to enter the download mode, there will be a problem of accidental triggering. Due to the inadvertent operation of the user, the button may be accidentally touched, thereby wrongly starting the upgrade process, which may cause data loss or the electronic device to be in an unstable state.

[0070] In one embodiment, referring to Figures 2 to 3 , the electronic device is provided with two buttons, namely a first button and a second button; the trigger control circuit 10 includes two trigger branches, namely a first trigger branch 11 and a second trigger branch 12;

[0071] The detection end of the first trigger branch 11 is electrically connected to the first button, the trigger signal output end of the first trigger branch 11 is electrically connected to the processor, the detection end of the second trigger branch 12 is electrically connected to the second button, and the trigger signal output end of the second trigger branch 12 is electrically connected to the processor;

[0072] When the first trigger branch 11 detects the first upgrade control signal generated by the user triggering the first button, it outputs a corresponding first trigger signal to the processor; when the second trigger branch 12 detects the second upgrade control signal generated by the user triggering the second button, it outputs a corresponding second trigger signal to the processor, so that the processor responds to the first trigger signal and the second trigger signal and enters the download mode.

[0073] A logic control circuit 20, the first input end of the logic control circuit 20 is electrically connected to the first trigger branch 11, the second input end of the logic control circuit 20 is electrically connected to the second trigger branch 12, and the logic control circuit 20 is configured to output a control signal to the processor when receiving the first trigger signal and the second trigger signal, so that the processor responds to the trigger signal and enters the download mode.

[0074] In this embodiment, both the first trigger branch 11 and the second trigger branch 12 can be implemented by a main controller. Refer to Figure 4 , the logic control circuit 20 can be implemented by a control circuit composed of an AND gate circuit and a switch circuit 22. Among them, the switch circuit 22 can be implemented by switch devices such as relays, contactors, and circuit breakers, or can be implemented by switching transistors such as triodes, MOS transistors, and IGBT transistors; the AND gate circuit includes at least two input ends, which are respectively electrically connected to the first trigger branch 11 and the second trigger branch 12; the switch circuit 22 is electrically connected to the output end of the AND gate circuit, and the AND gate circuit is configured to output a conduction signal to the switch circuit 22 when receiving the first trigger signal and the second trigger signal, so as to output a control signal to the processor through the switch circuit 22.

[0075] Combining the content of the above embodiments, the first button and the second button can be physical buttons specifically set for triggering the download mode, or the function buttons already defined in the electronic device can be used. Taking the first button and the second button as the function buttons already defined as an example for illustration, for example, the first button is the volume up (+) button, which is used to generate a first upgrade control signal. The second button is the volume down (-) button, which is used to generate a second upgrade control signal. The first trigger branch 11 is responsible for detecting the state of the first button, and when detecting the first upgrade control signal generated by the user triggering the first button, it outputs a corresponding first trigger signal to the input terminal of the AND gate circuit of the logic control circuit 20. The second trigger branch 12 is responsible for detecting the state of the second button, and when detecting the second upgrade control signal generated by the user triggering the second button, it outputs a corresponding second trigger signal to the other input terminal of the AND gate circuit. When the AND gate circuit receives the first trigger signal and the second trigger signal simultaneously, it outputs a conduction signal to the switch circuit 22, so as to output the control signal output by the AND gate circuit to the processor through the switch circuit 22 and enter the download mode.

[0076] Specifically, since the function buttons already defined in the electronic device are reused as the physical buttons for entering the download mode, it is necessary to first turn off the electronic device, so that the power on / off circuit detects the power on / off state of the electronic device and outputs a corresponding state detection signal to the trigger control circuit 10. When the trigger control circuit 10 determines that the electronic device is in the off state according to the state detection signal, if the user presses the first button volume up (+) button and the second button volume down (-) button, when both the first trigger signal and the second trigger signal are high-level signals, the AND gate circuit will output a high-level signal to the BOOT pin of the processor through the switch circuit 22 to start the processor to enter the download mode for operations such as repairing and upgrading the electronic device. It can be understood that when the user does not turn off the electronic device in advance, if the user presses the first button and / or the second button, at this time, the trigger control circuit 10 will not output a trigger signal to the processor, and the processor cannot enter the download mode, so as to ensure that when the device is in the on state, the first button and the second button are the function buttons originally defined in the electronic device to perform corresponding function operations. In addition, the setting of the AND gate circuit can ensure that when only one button is triggered, for example, when the user only presses the first button or the second button, the AND gate circuit will output a cut-off signal to the switch circuit 22 when receiving the first trigger signal or the second trigger signal, so that the processor cannot enter the download mode. That is, only when both the first trigger signal and the second trigger signal are high-level, the AND gate circuit will control the switch circuit 22 to be in the conduction state. In this way, the combination of the first button and the second button can enter the download mode before power on, and after power on, the combination of the first button and the second button can also be set to achieve other functions, such as entering the factory test mode, etc.;

[0077] With the above settings, since two buttons need to be pressed simultaneously to trigger the download mode, the risk of accidental operation caused by accidental touch of a single button is reduced. At the same time, by using the existing function buttons, no additional hardware modification is required, saving the design cost. In addition, the download mode can only be entered when the device is in the shutdown state, reducing the risk of accidentally entering the download mode during normal operation.

[0078] In one embodiment, referring to Figure 5 , the trigger control circuit 10 includes:

[0079] A trigger 13, the input end of the trigger 13 is electrically connected to the button, and the output end of the trigger 13 is electrically connected to the processor;

[0080] The trigger 13 is configured to count once each time an upgrade control signal generated by the button being triggered by the user is received at the input end, so as to output a corresponding trigger signal to the processor when the set count number is reached, so that the processor responds to the trigger signal and enters the download mode.

[0081] In this embodiment, the trigger 13 can be implemented by a D trigger 13, an SR trigger 13, a JK trigger 13, etc. The trigger 13 can be internally provided with a counter for recording the number of times the button is triggered, and when the set count number is reached, a corresponding trigger signal is output to the processor, so that the processor responds to the trigger signal and enters the download mode. It can be understood that a comparator can also be integrated in the trigger 13. Among them, the input end of the comparator is electrically connected to the output end of the counter, the reference end of the comparator is used to access the set count number signal, the comparator is used to compare the count value of the counter with the set count number, and when the count value of the counter reaches the set count number, a trigger signal is output to the processor. The set count number is set in advance by the R & D personnel.

[0082] Specifically, taking the set counting times as three times as an example, in the normal working mode, the physical button used to trigger the processor in the electronic device to enter the download mode is not triggered by the user. At this time, the count value of the counter is zero, and the processor is in the normal working mode. When the electronic device needs to be in the download mode for maintenance or upgrade processing, the user needs to continuously press the physical button used to trigger the processor in the electronic device to enter the download mode. The counter can detect the number of rising edges or falling edges of the upgrade control signal. Each time it is detected, the count increases by one unit. When the count value of the counter reaches three times, the output terminal of the comparator will output a trigger signal to the processor to make it enter the download mode. For example, when the count value is less than three times, the comparator outputs a low-level signal. When the count value is greater than or equal to three times, the comparator outputs a high-level signal. When the BOOT pin of the processor receives the high-level signal, the download mode is started. After completing the download or upgrade operation, the download mode can be exited according to specific steps. Usually, exiting the download mode requires pressing a specific combination of buttons again or through a software command. It can be understood that after completing one start and end process of the download mode, the count value of the counter will be reset to zero for the next counting operation.

[0083] It should be noted that, in order to improve the accuracy of starting the download mode, optionally, the trigger control circuit 10 may further include a timer 14, which is electrically connected to the trigger 13. When the user presses the button, the timer 14 starts timing, and at the same time the counter starts counting. If within the preset time period, the count value of the counter reaches the set counting times, the comparator outputs a high-level signal. When the BOOT pin of the processor receives the high-level signal, the download mode is started. If within the preset time period, the count value of the counter does not reach the set counting times, the comparator outputs a low-level signal and the download mode is not started. In this embodiment, the timer 14 and the trigger 13 can be integrated in the same integrated chip to reduce the wiring area. In this way, by presetting a preset time period, it can be limited that the user must complete the continuous triggering of the button within a specific time period, thereby reducing the risk of accidental triggering caused by long-term incorrect operations. Even if the user accidentally triggers the button, as long as the sufficient triggering times are not reached within the preset time period, the device will not enter the download mode, increasing the security.

[0084] By setting the trigger 13, it is ensured that when the user continuously triggers the button within the specified preset time period to reach a certain number of times (the set counting times), the processor will respond to the trigger signal and enter the download mode, thus significantly reducing the risk of entering the download mode due to accidental triggering. Starting the download mode in a simple and intuitive way (i.e., continuously pressing a single button) enables the user to understand and operate more easily. At the same time, the requirement for buttons is reduced. In addition, the trigger control circuit 10 uses common components, and the circuit design is simple and easy to implement.

[0085] In one embodiment, referring to Figure 6 , the trigger control circuit 10 includes:

[0086] A timer 14, an input end of the timer is electrically connected to a key, and an output end of the timer 14 is electrically connected to a processor;

[0087] The timer 14 is configured to start timing when receiving an upgrade control signal generated by the user triggering the key, and output a corresponding trigger signal to the processor when reaching a set timing duration, so that the processor responds to the trigger signal and enters the download mode.

[0088] In this embodiment, the timer 14 can be implemented by using an RTC (Real-Time Clock), a timer, etc. The timer 14 is configured to start timing when the key is pressed and end timing when the key is released. If the timing duration of the timer 14 reaches the set timing duration, a trigger signal is output to the processor to make it enter the download mode for software upgrade or problem location detection. A comparator can also be set in the timer 14 to compare the current timing duration of the timer 14 with the set timing duration. When the timing duration is equal to the set timing duration, the comparator can trigger an interruption or an event. That is, an input end of the comparator is electrically connected to the timer 14, and an output end of the comparator is electrically connected to the processor, so as to output a corresponding trigger signal to the processor when the timing duration reaches the set timing duration, and make the processor respond to the trigger signal and enter the download mode.

[0089] Specifically, taking the set timing duration of three seconds as an example, in the normal working mode, the physical button used to trigger the processor in the electronic device to enter the download mode is not triggered by the user. At this time, the initial value of the timer 14 is zero, and the processor is in the normal working mode; when it is necessary for the electronic device to be in the download mode for maintenance or upgrade processing, the timer 14 can be responsible for detecting the state change of the button and determining whether to output a trigger signal according to the time when the button is pressed. That is, the timer 14 is used to measure the time when the button is long-pressed. When the button is pressed, the timer 14 starts timing. When the button is released, the timing stops, and when the timing duration corresponding to the time when the button is pressed reaches the set timing duration, a trigger signal is output to the processor to make it enter the download mode. Optionally, a comparator can also be set in the timer 14. The comparator compares the timing duration and the set timing duration according to the timing signal output by the timer 14. When the timing duration reaches three seconds, the comparator outputs a trigger signal (such as a high-level signal) to the processor to make the processor enter the download mode. When the timing duration from the button being pressed to being released is less than three seconds, the processor remains in the normal working mode. That is, if the button is pressed by the user but the duration is less than three seconds, the processor cannot be triggered to enter the download mode. Among them, the set timing duration is set in advance by the R & D personnel. It can be understood that after completing one start and end process of the download mode, the value of the timer 14 will be reset to zero for the next timing work.

[0090] Combined with the content of the above embodiments, the button used to start the processor to enter the download mode can be an additional button or a button that has been defined, such as the power button of the electronic device. When the power button is short-pressed (the duration when the button is pressed is less than the set timing duration), its original function is triggered. When the power button is long-pressed and the timing duration from the button being pressed to being released reaches the set timing duration, the power button is used as the button to start the download mode. That is, when the power button is pressed, the timer 14 starts. When the power button is released, the timing stops. If the timing duration is less than the set timing duration, the default function of the power button (such as turning on or off) is executed. If the timing duration is greater than or equal to the set timing duration, the download mode is entered.

[0091] Through the above settings, the BOOT control is realized by using the function buttons with existing definitions without adding additional dedicated buttons for control, thus eliminating the need to increase additional hardware costs. Users can enter the download mode through simple operations (such as long-pressing the power button) without having to look for additional buttons or complex menus. At the same time, since it is necessary to long-press the button to enter the download mode, the risk of accidental triggering is reduced.

[0092] In another embodiment, referring to Figure 7 , the upgrade control circuit includes a power supply terminal for accessing the power supply voltage, and the first trigger branch 11 includes:

[0093] A first switch module, a first end of the first switch module is electrically connected to the power supply end, a second end of the first switch module is electrically connected to a first key, and a third end of the first switch module is electrically connected to the processor;

[0094] The first switch module is configured to conduct a path between the power supply end and the processor when receiving a first upgrade control signal generated by the user triggering the first key, so as to output a first trigger signal to the processor;

[0095] The second trigger branch 12 includes:

[0096] A second switch module, a first end of the second switch module is electrically connected to the power supply end, a second end of the second switch module is electrically connected to a second key, and a third end of the second switch module is electrically connected to the processor;

[0097] The second switch module is configured to conduct a path between the power supply end and the processor when receiving a second upgrade control signal generated by the user triggering the second key, so as to output a second trigger signal to the processor.

[0098] In this embodiment, both the first switch module and the second switch module can be implemented by switching tubes such as triodes, MOS tubes, and IGBT tubes and peripheral circuits, or by switching devices such as relays and contactors and peripheral circuits.

[0099] Optionally, the first switch module includes:

[0100] A first switching tube;

[0101] A first pull-up resistor, a first end of the first pull-up resistor is electrically connected to the power supply end, and a second end of the first pull-up resistor is electrically connected to a first end of the first switching tube;

[0102] A first voltage-dividing resistor, a first end of the first voltage-dividing resistor is the second end of the first switch module, and a second end of the first voltage-dividing resistor is electrically connected to the second end of the first pull-up resistor; and is used to form a voltage-dividing circuit with the first pull-up resistor;

[0103] A first resistor, a first end of the first resistor is electrically connected to the power supply end, a second end of the first resistor is electrically connected to a second end of the first switching tube, and a third end of the first switching tube is grounded.

[0104] The second switch module includes:

[0105] A second switching tube;

[0106] A second pull-up resistor, with the first end of the second pull-up resistor electrically connected to the power supply terminal and the second end of the second pull-up resistor electrically connected to the first end of the second switching transistor;

[0107] A second voltage-dividing resistor, with the first end of the second voltage-dividing resistor being the second end of the second switching module, and the second end of the second voltage-dividing resistor electrically connected to the second end of the second pull-up resistor; and it is used to form a voltage-dividing circuit with the second pull-up resistor;

[0108] A second resistor, with the first end of the second resistor electrically connected to the power supply terminal, the second end of the second resistor electrically connected to the second end of the second switching transistor, and the third end of the second switching transistor grounded.

[0109] In this embodiment, the first switching transistor and the second switching transistor can be implemented by switching transistors such as triodes, MOS transistors, and IGBT transistors, or by switching devices such as relays and contactors.

[0110] Taking the case where the first switching transistor, the second switching transistor, and the switching circuit 22 all adopt N-type MOS transistors and the AND gate circuit adopts an AND gate chip as an example for specific illustration. The first end of the first pull-up resistor R2 is electrically connected to the power supply terminal VDD, and the second end of the first pull-up resistor R2 is electrically connected to the gate of the first switching transistor Q1; the first end of the first voltage-dividing resistor R3 is the second end of the first switching module, and the second end of the first voltage-dividing resistor R3 is electrically connected to the second end of the first pull-up resistor R2; R3 and R2 form a first voltage-dividing circuit; the first end of the first resistor R1 is electrically connected to the power supply terminal VDD, the second end of the first resistor R1 is electrically connected to the drain of the first switching transistor Q1, and the source of the first switching transistor is grounded. The first end of the second pull-up resistor R5 is electrically connected to the power supply terminal VDD, and the second end of the second pull-up resistor R5 is electrically connected to the gate of the second switching transistor Q2; the first end of the second voltage-dividing resistor R6 is the second end of the second switching module, and the second end of the second voltage-dividing resistor R6 is electrically connected to the second end of the second pull-up resistor R5; R5 and R6 form a second voltage-dividing circuit; the first end of the second resistor R4 is electrically connected to the power supply terminal VDD, the second end of the second resistor R4 is electrically connected to the drain of the second switching transistor Q2, and the source of the second switching transistor is grounded. K is an AND gate chip, its first input terminal A is connected to the drain of the first switching transistor Q1, the second input terminal B is electrically connected to the drain of the second switching transistor Q2, the output terminal Y is electrically connected to the gate of the third switching transistor Q3, the drain of the third switching transistor Q3 is electrically connected to the BOOT pin, and the source of Q3 is grounded.

[0111] Combined with the content of the above embodiments, when the user presses the power on / off button or the power off button, the control circuit 10 is triggered to determine that the electronic device is in the power off state according to the status detection signal. At this time, when the user presses the volume up (KEY+) and volume down (KEY-) buttons simultaneously, the processor (or the electronic device) powers on and boots. Before the button (KEY+) is pressed, the first pull-up resistor R2 will pull up the gate voltage of Q1, and Q1 is in the conducting state, outputting a low-level signal to the AND gate chip K. Similarly, before the button (KEY-) is pressed, the second pull-up resistor R5 will pull up the gate voltage of Q2, and Q2 is in the conducting state, outputting a low-level signal to the AND gate chip K. Since both input terminals of the AND gate chip K are connected to low-level signals, the output terminal Y outputs a low-level signal at this time, and the voltage between the gate and source of Q3 is less than 0. Therefore, Q3 is cut off. When the button (KEY+) is pressed by the user, the first end of the first voltage-dividing resistor R3 is grounded, and R3 divides the voltage, pulling down the gate voltage of Q1, and Q1 is cut off. At this time, the voltage at the second end of the first resistor R1 is VDD, that is, a high level is output to the first input terminal A of the AND gate chip. When the button (KEY-) is pressed by the user, the first end of the second voltage-dividing resistor R6 is grounded, and R6 divides the voltage, pulling down the gate voltage of Q2, and Q2 is cut off. At this time, the voltage at the second end of the second resistor R4 is VDD, that is, a high level is output to the second input terminal B of the AND gate chip. Since both input terminals of the AND gate circuit K are connected to high-level signals, the output terminal Y outputs a high-level signal to the gate of the third switching transistor Q3, and Q3 conducts to the ground, pulling down the level signal of the BOOT pin, that is, the BOOT pin is connected to a low-level signal, and the processor enters the download mode.

[0112] Through the above settings, the problem that the whole machine cannot enter the download mode and software upgrade and problem location can only be carried out by disassembling the machine is improved. There is no need to set an additional button, which is realized by a pure hardware circuit, saving the circuit design cost and not affecting the appearance of the product. Since the combination buttons of the volume up button and the volume down button are pressed before the module is powered on, it does not affect the functions defined by the product. Compared with the situation where the download mode cannot be entered when a single button is damaged, the possibility of both buttons being damaged or abnormal at the same time is lower. The combination button form is adopted, reducing the risk of mis-triggering, and thus improving the reliability of the work.

[0113] The present invention proposes an upgrade circuit, and the upgrade circuit includes a processor, a button, and the upgrade control circuit as described in any one of the above.

[0114] Combined with the content of the above embodiments, the number of buttons can be one or more. The buttons can be function buttons that reuse the defined functions or buttons specially added for entering the download mode. When the number of buttons is multiple, a combination button form can be adopted, that is, when multiple buttons are pressed simultaneously, the processor will respond to trigger the trigger signal output by the control circuit 10 and enter the download mode. In this way, the risk of mis-triggering is reduced, and the working reliability is improved accordingly.

[0115] It should be noted that since the upgrade circuit of the present application includes the above-mentioned upgrade control circuit, the embodiments of the upgrade circuit of the present application include all the technical solutions of all the embodiments of the above-mentioned upgrade control circuit, and the achieved technical effects are also exactly the same, so they will not be elaborated here.

[0116] The present utility model also proposes an electronic device, including the upgrade circuit as described above.

[0117] It should be noted that since the electronic device of the present application includes the above-mentioned upgrade circuit, the embodiments of the electronic device of the present application include all the technical solutions of all the embodiments of the above-mentioned upgrade circuit, and the achieved technical effects are also exactly the same, so they will not be elaborated here.

[0118] The above are only the optional embodiments of the present utility model, and do not limit the patent scope of the present utility model accordingly. Any equivalent structural transformation made by using the specification and drawings of the present utility model under the inventive concept of the present utility model, or any direct / indirect application in other related technical fields is included in the scope of the present utility model.

Claims

1. An upgrade control circuit is applied to an electronic device. The electronic device is provided with a key and a processor, and is characterized in that The upgrade control circuit includes: A trigger control circuit, wherein a detection end of the trigger control circuit is electrically connected to a key, a trigger signal output end of the trigger control circuit is electrically connected to a processor, and when the trigger control circuit detects an upgrade control signal generated by the key being triggered by a user, the trigger control circuit outputs a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters a download mode.

2. The upgrade control circuit according to claim 1, wherein The electronic device is provided with two keys, namely a first key and a second key; the trigger control circuit includes two trigger branches, namely a first trigger branch and a second trigger branch; A detection end of the first trigger branch is electrically connected to the first key, a trigger signal output end of the first trigger branch is electrically connected to the processor, a detection end of the second trigger branch is electrically connected to the second key, and a trigger signal output end of the second trigger branch is electrically connected to the processor; When the first trigger branch detects a first upgrade control signal generated by the first key being triggered by a user, the first trigger branch outputs a corresponding first trigger signal to the processor; When the second trigger branch detects a second upgrade control signal generated by the second key being triggered by a user, the second trigger branch outputs a corresponding second trigger signal to the processor, so that the processor responds to the first trigger signal and the second trigger signal and enters a download mode.

3. The upgrade control circuit according to claim 2, wherein The trigger control circuit further includes a logic control circuit, a first input end of the logic control circuit is electrically connected to the first trigger branch, a second input end of the logic control circuit is electrically connected to the second trigger branch, and the logic control circuit is configured to output a control signal to the processor when receiving the first trigger signal and the second trigger signal, so that the processor responds to the trigger signal and enters a download mode.

4. The upgrade control circuit according to claim 3, characterized in that The logic control circuit includes: An AND gate circuit, the AND gate circuit includes at least two input ends, which are respectively electrically connected to the first trigger branch and the second trigger branch; A switch circuit, the switch circuit is electrically connected to an output end of the AND gate circuit; The AND gate circuit is configured to output a conduction signal to the switch circuit when receiving the first trigger signal and the second trigger signal, so as to output a control signal to the processor through the switch circuit.

5. The upgrade control circuit according to claim 1, wherein The trigger control circuit includes: A trigger, an input end of the trigger is electrically connected to a key, and an output end of the trigger is electrically connected to a processor; The trigger is configured to count once every time an upgrade control signal generated by the key being triggered by a user is received at the input end, and when a set counting number is reached, the trigger outputs a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters a download mode; Alternatively, a timer, an input end of the timer is electrically connected to a key, and an output end of the timer is electrically connected to a processor; The timer is configured to start timing when receiving an upgrade control signal generated by the key being triggered by a user, and when a set timing duration is reached, the timer outputs a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters a download mode.

6. The upgrade control circuit according to claim 2, characterized in that The upgrade control circuit includes a power supply end for accessing a power supply voltage, and the first trigger branch includes: A first switch module, a first end of the first switch module is electrically connected to the power supply terminal, a second end of the first switch module is electrically connected to a first key, and a third end of the first switch module is electrically connected to the processor; The first switch module is configured to, when receiving a first upgrade control signal generated by the user triggering the first key, conduct a path between the power supply terminal and the processor, so as to output a first trigger signal to the processor; The second trigger branch includes: A second switch module, a first end of the second switch module is electrically connected to the power supply terminal, a second end of the second switch module is electrically connected to a second key, and a third end of the second switch module is electrically connected to the processor; The second switch module is configured to, when receiving a second upgrade control signal generated by the user triggering the second key, conduct a path between the power supply terminal and the processor, so as to output a second trigger signal to the processor.

7. The upgrade control circuit according to claim 6, characterized in that The first switch module includes: A first switch tube; A first pull-up resistor, a first end of the first pull-up resistor is electrically connected to the power supply terminal, and a second end of the first pull-up resistor is electrically connected to a first end of the first switch tube; A first voltage-dividing resistor, a first end of the first voltage-dividing resistor is the second end of the first switch module, and a second end of the first voltage-dividing resistor is electrically connected to the second end of the first pull-up resistor; and is configured to form a voltage-dividing circuit with the first pull-up resistor; A first resistor, a first end of the first resistor is electrically connected to the power supply terminal, a second end of the first resistor is electrically connected to a second end of the first switch tube, and a third end of the first switch tube is grounded; The second switch module includes: A second switch tube; A second pull-up resistor, a first end of the second pull-up resistor is electrically connected to the power supply terminal, and a second end of the second pull-up resistor is electrically connected to a first end of the second switch tube; A second voltage-dividing resistor, a first end of the second voltage-dividing resistor is the second end of the second switch module, and a second end of the second voltage-dividing resistor is electrically connected to the second end of the second pull-up resistor; and is configured to form a voltage-dividing circuit with the second pull-up resistor; A second resistor, a first end of the second resistor is electrically connected to the power supply terminal, a second end of the second resistor is electrically connected to a second end of the second switch tube, and a third end of the second switch tube is grounded.

8. The upgrade control circuit according to claim 1, characterized in that The upgrade control circuit further includes: A power-on / off circuit, the power-on / off circuit is electrically connected to the trigger control circuit; The power-on / off circuit is configured to detect the power-on / off state of the electronic device, and output a state detection signal to the trigger control circuit; The trigger control circuit is configured to, when determining according to the state detection signal that the electronic device is in the power-off state and detecting an upgrade control signal generated by the user triggering a key, output a corresponding trigger signal to the processor, so that the processor responds to the trigger signal and enters the download mode.

9. An upgrade circuit, characterized in that, The upgrade circuit includes a processor, a key, and the upgrade control circuit according to any one of claims 1 to 8.

10. An electronic device, characterized in that, The electronic device includes the upgrade circuit according to claim 9.

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