CAN interface circuit and bus device

Abstract

The utility model belongs to the bus communication technology, and specifically relates to a CAN interface circuit and a bus device, the CAN interface circuit comprises a bus transmit-receive module, a bus control module and a logic processing module; wherein the bus control module is suitable for receiving a feedback signal output by the bus transceiving module so as to output an ACK (Acknowledgement Character) signal; the logic processing module is electrically connected with the bus control module and a processor module of the bus equipment so as to receive, logically and process the first bus message signal and the ACK signal from the processor module; the bus transceiving module is electrically connected with the logic processing module so as to receive a second bus message signal which is output after logic and processing of the logic processing module, so that a third bus message signal is output to external equipment; the CAN interface circuit provided by the utility model has a spontaneous ACK (Acknowledgement Character) capability, can realize active ACK response of a bus interface, and ensures that a bus transceiving module correctly sends a bus message, thereby ensuring that the CAN bus message is continuously sent.

Description

Technical Field

[0001] The utility model belongs to the field of bus communication technology, and particularly relates to a CAN interface circuit and a bus device. Background Art

[0002] In CAN bus communication, the ACK bit (acknowledgment bit) is an important signal used to indicate whether a node has successfully received a valid frame. Therefore, in a traditional CAN bus, it is necessary to ensure that there are at least two nodes in the network, one for sending messages and one for sending ACK signals. However, in certain specific scenarios, the user's CAN node cannot send an ACK (Acknowledge character) signal. At this time, due to the lack of an ACK node, the CAN tool cannot correctly send messages.

[0003] In the related art, an FPGA is used to implement active ACK message processing, but this method involves complex software design and extremely costly hardware design.

[0004] Therefore, without relying on an FPGA module, solving how to maintain CAN bus communication in the absence of an ACK node is a technical problem that urgently needs to be solved in this field. Summary of the Utility Model

[0005] In order to solve the technical problems mentioned in the background art, the utility model provides a CAN interface circuit and a bus device.

[0006] The utility model provides a CAN interface circuit, including:

[0007] A bus transceiver module, a bus control module, and a logic processing module; wherein

[0008] The bus control module is adapted to receive a feedback signal output by the bus transceiver module to output an ACK signal;

[0009] The logic processing module is electrically connected to the bus control module and the processor module of the bus device to receive and perform logical AND processing on the first bus message signal from the processor module and the ACK signal; and

[0010] The bus transceiver module is electrically connected to the logic processing module to receive the second bus message signal output after the logical AND processing by the logic processing module, so as to output a third bus message signal to an external device.

[0011] Further, the bus transceiver module is further adapted to send the feedback signal to the processor module while outputting the third bus message signal to the external device, so as to trigger the processor module to continuously output the first bus message signal.

[0012] Further, the bus control module is electrically connected to the processor module through an SPI interface.

[0013] Further, the logic processing module includes: an AND gate module; wherein

[0014] Two input ends of the AND gate module are respectively and electrically connected to a first bus message signal output pin of the processor module and an ACK signal output pin of the bus control module; and

[0015] An output end of the AND gate module is electrically connected to a data receiving pin of the bus transceiver module.

[0016] Further, the bus transceiver module includes: a bus transceiver; wherein

[0017] A feedback signal output pin of the bus transceiver is respectively and electrically connected to a feedback signal receiving pin of the processor module and a feedback signal receiving pin of the bus control module; and

[0018] The bus transceiver outputs a third bus message signal to an external device through a bus high-level pin and a bus low-level pin.

[0019] Further, the bus control module includes: a bus controller; wherein

[0020] A feedback signal receiving pin of the bus controller is electrically connected to a feedback signal output pin of the bus transceiver; and

[0021] An ACK signal output pin of the bus controller is electrically connected to an input end of the AND gate module.

[0022] In another aspect, the present utility model further provides a bus device, including: a processor module; and at least one CAN interface circuit as described above.

[0023] Further, the model of the processor module is a TC397XP-256F300S controller.

[0024] The beneficial effect of the present utility model is that the CAN interface circuit of the present utility model has the ability to spontaneously generate ACK. Specifically, through the cooperation of the logic processing module and the bus transceiver module, the bus control module is triggered to output an ACK signal, realizing an active ACK response of the bus interface, and through the cooperation of the processor module, the bus control module, the bus transceiver module and the logic processing module, it is ensured that the bus transceiver module correctly sends out bus messages, thereby ensuring the continuous sending of CAN bus messages, and the CAN interface circuit has a simple structure and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present utility model will be further described below in conjunction with the drawings and embodiments.

[0026] Figure 1 is the design block diagram of the CAN interface circuit provided by some embodiments;

[0027] Figure 2 is a partial circuit diagram of the logic processing module provided by some embodiments;

[0028] Figure 3 is a partial circuit diagram of the bus transceiver module provided by some embodiments;

[0029] Figure 4 is a partial circuit diagram of the bus control module provided by some embodiments;

[0030] Figure 5 is the principle block diagram of the bus device provided by some embodiments;

[0031] Figure 6 is a partial circuit diagram of the processor module provided by some embodiments. Detailed implementation manners

[0032] Now, the present utility model will be further described in detail with reference to the accompanying drawings. These drawings are all simplified schematic diagrams, only illustrating the basic structure of the present utility model in a schematic manner, so they only show the components related to the present utility model.

[0033] As Figure 1 shown, at least one embodiment provides a CAN interface circuit, including: a bus transceiver module, a bus control module, and a logic processing module; wherein the bus control module is adapted to receive the feedback signal CAN0_NODE0_RXD output by the bus transceiver module to output an ACK signal MCP1_CAN_TXD; the logic processing module is electrically connected to the bus control module and the processor module of the bus device to receive and logically process the first bus message signal CAN0_NODE0_TXD from the processor module and the ACK signal MCP1_CAN_TXD; and the bus transceiver module is electrically connected to the logic processing module to receive the second bus message signal CAN0_TXD_NODE0 output after the logical processing of the logic processing module, so as to output a third bus message signal to an external device.

[0034] In some embodiments, the bus transceiver module is further adapted to send the feedback signal CAN0_NODE0_RXD to the processor module while outputting the third bus message signal to the external device, so as to trigger the processor module to continuously output the first bus message signal

[0035] CAN0_NODE0_TXD.

[0036] The working principle of this CAN interface circuit is as follows: The first bus message signal CAN0_NODE0_TXD output by the processor module (the ACK bit of the first bus message signal CAN0_NODE0_TXD is recessive) and the ACK signal MCP1_CAN_TXD output by the bus control module are jointly used as the input signals of the logic processing module. At this time, after receiving the second bus message signal CAN0_TXD_NODE0 obtained by the logical AND processing of the logic processing module (the ACK bit of the second bus message signal CAN0_TXD_NODE0 is dominant at this time), the bus transceiver module outputs a complete third bus message signal to the external device (the ACK bit of the third bus message signal sent to the external device is also dominant). At the same time, the bus transceiver module also outputs a feedback signal CAN0_NODE0_RXD to the processor module and the bus control module, so that the processor module and the bus control module know that the bus transceiver module has sent a complete bus message signal, so that the processor module continuously outputs the first bus message signal

[0037] CAN0_NODE0_TXD and enables the bus control module to continuously output the ACK signal.

[0038] Specifically, the bus control module is also connected to the processor module through an SPI (Serial Peripheral Interface) interface to achieve synchronous communication; the external device is, for example but not limited to, an automotive ECU.

[0039] Specifically, the CAN interface circuit with the ability to spontaneously generate ACK in this embodiment triggers the bus control module to output the ACK signal through the cooperation of the logic processing module and the bus transceiver module, realizes the active ACK response of the bus interface, and ensures that the bus transceiver module correctly sends the bus message through the cooperation of the processor module, the bus control module, the bus transceiver module and the logic processing module, so as to ensure the continuous sending of the CAN bus message, and the CAN interface circuit has a simple structure and low cost.

[0040] In some embodiments, such as Figure 2As shown, the model of the logic processing module U9 can be, but is not limited to, a logic AND gate module, such as the SN74 series. In this embodiment, the SN74AHC1G08DBVR AND gate module is taken as an example. The 1st input pin of the SN74AHC1G08DBVR AND gate module is electrically connected to the output pin of the first bus message signal CAN0_NODE0_TXD of the processor module. The 2nd input pin of the SN74AHC1G08DBVR AND gate module is electrically connected to the output pin of the ACK signal MCP1_CAN_TXD of the bus control module. And the output pin of the second bus message signal CAN0_TXD_NODE0 of the SN74AHC1G08DBVR AND gate module is electrically connected to the data receiving pin of the bus transceiver module.

[0041] In some embodiments, such as Figure 3 As shown, the model of the bus transceiver module U5 is, for example but not limited to, the MCP2558FD transceiver. The 1st pin of the MCP2558FD transceiver serves as the data receiving pin. The 4th pin of the MCP2558FD transceiver serves as the output pin of the feedback signal CAN0_NODE0_RXD, which is electrically connected to the Y13 pin of the processor module and the 2nd pin of the bus control module respectively. And the MCP2558FD transceiver sends the third bus message signal to external devices through the CANH pin and the CANL pin.

[0042] In some embodiments, such as Figure 4 As shown, the model of the bus control module U6 is, for example but not limited to, the MCP2518FD controller. The 2nd pin of the MCP2518FD controller serves as the feedback signal receiving pin, which is electrically connected to the output pin of the feedback signal CAN0_NODE0_RXD of the MCP2558FD transceiver. And the 1st pin of the MCP2518FD controller serves as the output pin of the ACK signal MCP1_CAN_TXD, which is electrically connected to the 2nd input pin of the SN74AHC1G08DBVR AND gate module.

[0043] Such as Figure 5 As shown, some embodiments also provide a bus device, including: a processor module; and at least one CAN interface circuit as described above.

[0044] In some embodiments, such as Figure 6 As shown, the model of the processor module U138M is, for example but not limited to, the TC397XP-256F300S controller. Its corresponding CAN0_NODE0_TXD, CAN2_NODE1_TXD, CAN2_NODE2_TXD can respectively correspond to three CAN interface circuits to complete the output of the corresponding bus message signals.

[0045] This embodiment relates to the improvement of the circuit structure. Specifically, the ACK signal MCP1_CAN_TXD output by the bus control module and the first bus message signal CAN0_NODE0_TXD output by the processor module are processed through a logical AND gate by means of an AND gate module, so as to trigger the bus transceiver module to output a complete third bus message signal to the external device. This process does not involve the improvement of the CAN communication protocol and software methods. Those skilled in the art can implement the circuit design of this embodiment through the written description of the above implementation part.

[0046] Inspired by the above ideal embodiment according to the present invention, through the above description, relevant staff can make various changes and modifications completely within the scope without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A CAN interface circuit, characterized in that, Comprising: A bus transceiver module, a bus control module, and a logic processing module; Wherein The bus control module is adapted to receive a feedback signal output by the bus transceiver module to output an ACK signal; The logic processing module is electrically connected to the bus control module and the processor module of the bus device to receive and perform a logical AND operation on a first bus message signal and the ACK signal from the processor module; And The bus transceiver module is electrically connected to the logic processing module to receive a second bus message signal output after the logical AND operation by the logic processing module, so as to output a third bus message signal to an external device; The logic processing module uses an SN74AHC1G08DBVR AND gate chip, its pin 1 is electrically connected to the output pin of the first bus message signal CAN0_NODE0_TXD of the processor module, and its pin 2 is electrically connected to the output pin of the ACK signal MCP1_CAN_TXD of the bus control module; and the output pin of the second bus message signal CAN0_TXD_NODE0 of the SN74AHC1G08DBVR AND gate module is electrically connected to the data receiving pin of the bus transceiver module; The bus transceiver module uses an MCP2558FD transceiver; its pin 1 is used as the data receiving pin; its pin 4 is used as the output pin of the feedback signal CAN0_NODE0_RXD; and the MCP2558FD transceiver sends a third bus message signal to an external device through the CANH pin and the CANL pin; The bus control module uses an MCP2518FD controller, its pin 2 is used as the feedback signal receiving pin, and it is electrically connected to the output pin of the feedback signal CAN0_NODE0_RXD of the MCP2558FD transceiver; and the pin 1 of the MCP2518FD controller is used as the output pin of the ACK signal MCP1_CAN_TXD, and it is electrically connected to the pin 2 of the input of the SN74AHC1G08DBVR AND gate module.

2. The CAN interface circuit according to claim 1, characterized in that The bus transceiver module is further adapted to send the feedback signal to the processor module while outputting the third bus message signal to an external device to trigger the processor module to continuously output the first bus message signal.

3. The CAN interface circuit according to claim 1, characterized in that The bus control module is electrically connected to the processor module through an SPI interface.

4. The CAN interface circuit according to claim 1, characterized in that The logic processing module includes: an AND gate module; wherein Two input ends of the AND gate module are respectively electrically connected to the output pin of the first bus message signal of the processor module and the output pin of the ACK signal of the bus control module; and The output end of the AND gate module is electrically connected to the data receiving pin of the bus transceiver module.

5. The CAN interface circuit according to claim 3, characterized in that The bus transceiver module includes: a bus transceiver; wherein The feedback signal output pins of the bus transceiver are electrically connected to the feedback signal receiving pins of the processor module and the feedback signal receiving pins of the bus control module respectively; and The bus transceiver outputs a third bus message signal to an external device through a bus high-level pin and a bus low-level pin.

6. The CAN interface circuit according to claim 5, wherein The bus control module includes: a bus controller; wherein The feedback signal receiving pin of the bus controller is electrically connected to the feedback signal output pin of the bus transceiver.

7. A bus device, characterized in that, Comprising: A processor module; And At least one CAN interface circuit according to any one of claims 1-6; The model of the processor module is a TC397XP-256F300S controller.

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