M-Bus bus host circuit

Abstract

The utility model discloses an M-Bus bus host circuit, which relates to the field of information transmission and comprises a boosting module, a bus receiving and transmitting module, a bus receiving and transmitting module, a bus receiving and transmitting module, a bus receiving and transmitting module, a bus receiving and transmitting module, a bus receiving and transmitting module and a bus transmitting and receiving module, wherein the boosting module is used for boosting 3-15V direct current to 34V direct current; the mbus transceiving module is used for realizing signal transceiving of the host MCU through nine chip resistors and three triodes; the boost module is connected with the mbus transceiver module. Compared with the prior art, the utility model has the beneficial effects that the mbus transceiver module is composed of the chip resistors and the triodes which are low in cost, the required specification of the DCDC boost chip of the boost module is loose, the total material cost is not more than 2.5 yuan, and the mbus transceiver module has some defects of limited volume, limited cost and low cost. A new circuit design thought is provided for embedded applications with no high requirements for loading capacity, and the circuit is particularly suitable for design application of mbus one-to-one meter reading products.

Description

Technical Field

[0001] The utility model relates to the field of information transmission, and specifically to an M-Bus bus host circuit. Background Technique

[0002] M-Bus, short for Meter-Bus, is a bus topology structure specially designed for meters for remote meter reading and data transmission. It is widely used in the remote meter reading of water meters, heat meters, gas meters, and electricity meters, as well as the monitoring and management of various sensors and measuring devices in system integrations such as fire protection and building automation.

[0003] The M-Bus bus adopts a master-slave structure two-wire half-duplex communication mode, which can be one master-one slave or one master-multiple slaves. In addition to the communication function, the M-Bus host has the function of powering the slave.

[0004] The M-Bus bus defines logic "1" as MARK and logic "0" as SPACE.

[0005] M-Bus host sending principle: The host uses voltage modulation to send. In the steady state, the voltage Vmark corresponding to logic "1" and the voltage Vspace corresponding to logic "0". When 22V ≤ Vmark ≤ 42V, it represents that the transmitted is logic "1"; when 12V ≤ Vspace ≤ Vmark - 10V, it represents that the transmitted is logic "0".

[0006] M-Bus host receiving principle: The communication from the slave to the host uses current modulation. In the steady state, 0mA < Imark ≤ 1.5mA represents that the transmitted is logic "1"; when Imark + 11mA ≤ Ispace ≤ Imark + 20mA, it represents that the transmitted is logic "0".

[0007] In order to have a relatively large load driving capacity in the common mbus host circuit design, the host transmitting part uses a high-power MOS circuit to generate voltage switching through high-speed on-off, and then realizes the sending voltage modulation. The receiving circuit often uses a resistor below 10Ω for current sampling, and then realizes current recognition through an amplifier comparator. Multiple levels are required in this circuit, such as Vmark and Vspace corresponding to logic "1" and logic "0" signals respectively, and the 5v voltage required for the operation of the receiving amplifier comparator. The overall circuit design is large and complex. In some small loads, such as one-to-one communication, this circuit design has a relatively high cost, wastes equipment resources, and needs to be improved. Content of the Utility Model

[0008] The purpose of the utility model is to provide an M-Bus bus host circuit to solve the problems raised in the above background technique.

[0009] To achieve the above object, the present utility model provides the following technical solutions:

[0010] An M-Bus bus host circuit, comprising:

[0011] A boost module for boosting a direct current voltage of 3 - 15V to 34V direct current voltage for supplying to the mbus transceiver module;

[0012] An mbus transceiver module for realizing signal transceiver of the host MCU through nine chip resistors and three triodes;

[0013] The boost module is connected to the mbus transceiver module.

[0014] As a further scheme of the present utility model: The boost module includes a voltage regulator U1, the model of the voltage regulator U1 is AP3015. The fifth terminal of the voltage regulator U1 is connected to the fourth terminal of the voltage regulator U1, one end of an inductor L1, one end of a capacitor C1, and one end of a fuse F1. The other end of the capacitor C1 is grounded. The other end of the fuse F1 is connected to a voltage VIN (3 - 15V voltage). The other end of the inductor L1 is connected to the first terminal of the voltage regulator U1 and the positive electrode of a diode D1. The negative electrode of the diode D1 is connected to one end of a resistor R1, one end of a capacitor C4, and the mbus transceiver module. The other end of the capacitor C4 is grounded. The other end of the resistor R1 is connected to one end of a resistor R2 and the third terminal of the voltage regulator U1. The other end of the resistor R2 is grounded.

[0015] As a further scheme of the present utility model: The mbus transceiver module includes resistors R3, R4, R5, R6, R7, R8, R9, R12, R13, triodes Q1, Q2, Q3. The base of the triode Q1 is connected to the third terminal of the interface MASTER1 through the resistor R3. The emitter of the triode Q1 is grounded. The collector of the triode Q1 is connected to one end of the resistor R5, one end of the resistor R6, and one end of the resistor R13. The other end of the resistor R5 is grounded. The other end of the resistor R6 is connected to a 34V voltage, one end of the resistor R8, one end of the resistor R12, and the first terminal of the interface M-PORT1. The second terminal of the interface M-PORT1 is connected to the other end of the resistor R12 and the emitter of the triode Q2. The base of the triode Q2 is connected to the other end of the resistor R13. The collector of the triode Q2 is connected to one end of the resistor R7 and the base of the triode Q3. The other end of the resistor R7 is grounded. The emitter of the triode Q3 is grounded. The collector of the triode Q3 is connected to the other end of the resistor R8, one end of the resistor R9, and one end of the resistor R4. The other end of the resistor R9 is grounded. The other end of the resistor R4 is connected to the fourth terminal of the interface MASTER1.

[0016] As a further scheme of the present utility model: The triodes Q1 and Q3 are NPN triodes.

[0017] As a further solution of the present utility model: The triode Q2 is a PNP triode.

[0018] Compared with the prior art, the beneficial effects of the present utility model are as follows: The mbus transceiver module of the present utility model is composed of low-cost chip resistors and triodes, and has loose requirements for the specifications of the DCDC boost chip of the boost module. The total material cost does not exceed 2.5 yuan, providing a new circuit design idea for some embedded applications with limited volume, cost, and not too high requirements for load-carrying capacity, and is particularly suitable for the design and application of mbus one-to-one meter reading products. Description of the Drawings

[0019] Figure 1 It is the circuit diagram of the boost module.

[0020] Figure 2 It is the circuit diagram of the mbus transceiver module. Specific Embodiments

[0021] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0022] Please refer to Figure 1 , an M-Bus bus host circuit, including:

[0023] A boost module, used to boost the direct current of 3 - 15V to 34V direct current and supply it to the mbus transceiver module;

[0024] An mbus transceiver module, used to realize the signal transceiver of the host MCU through nine chip resistors and three triodes;

[0025] The boost module is connected to the mbus transceiver module.

[0026] In this embodiment: Please refer to Figure 1, the boost module includes a voltage regulator U1, the model of the voltage regulator U1 is AP3015. The fifth terminal of the voltage regulator U1 is connected to the fourth terminal of the voltage regulator U1, one end of the inductor L1, one end of the capacitor C1, and one end of the fuse F1. The other end of the capacitor C1 is grounded. The other end of the fuse F1 is connected to the voltage VIN (3 - 15V voltage). The other end of the inductor L1 is connected to the first terminal of the voltage regulator U1 and the positive electrode of the diode D1. The negative electrode of the diode D1 is connected to one end of the resistor R1, one end of the capacitor C4, and the mbus transceiver module. The other end of the capacitor C4 is grounded. The other end of the resistor R1 is connected to one end of the resistor R2 and the third terminal of the voltage regulator U1. The other end of the resistor R2 is grounded.

[0027] The voltage VIN is a 3 - 15V DC voltage in the embedded circuit. The fuse F1 (self - resetting fuse) has a holding current specification of 500mA and is used to disconnect the protection of this module and the main circuit power supply when the mbus transceiver module fails or has a short - circuit over - current. The output voltage generates a feedback voltage through the resistors R1 and R2 for the DCDC chip U1 (AP3015) to adjust the output level to 34V. The capacitors C1 and C4 are for filtering.

[0028] In this embodiment: Please refer to Figure 2 , the mbus transceiver module includes resistors R3, R4, R5, R6, R7, R8, R9, R12, R13, transistors Q1, Q2, Q3. The base of the transistor Q1 is connected to the third terminal of the interface MASTER1 through the resistor R3. The emitter of the transistor Q1 is grounded. The collector of the transistor Q1 is connected to one end of the resistor R5, one end of the resistor R6, and one end of the resistor R13. The other end of the resistor R5 is grounded. The other end of the resistor R6 is connected to the 34V voltage, one end of the resistor R8, one end of the resistor R12, and the first terminal of the interface M - PORT1. The second terminal of the interface M - PORT1 is connected to the other end of the resistor R12 and the emitter of the transistor Q2. The base of the transistor Q2 is connected to the other end of the resistor R13. The collector of the transistor Q2 is connected to one end of the resistor R7 and the base of the transistor Q3. The other end of the resistor R7 is grounded. The emitter of the transistor Q3 is grounded. The collector of the transistor Q3 is connected to the other end of the resistor R8, one end of the resistor R9, and one end of the resistor R4. The other end of the resistor R9 is grounded. The other end of the resistor R4 is connected to the fourth terminal of the interface MASTER1.

[0029] In this embodiment: Please refer to Figure 2 , the transistors Q1 and Q3 are NPN transistors.

[0030] In this embodiment: Please refer to Figure 2 , the transistor Q2 is a PNP transistor.

[0031] When the host MCU sends a logic signal, when sending a logic "1", the triode Q1 conducts, the base voltage of the triode Q2 is at a low level, the triode Q2 conducts, and since the resistance value of the resistor R12 is much larger than that of the resistor R7, the voltage across the resistor R12 is at a high level; when sending a logic "0", the triode Q1 is cut off, and the voltage dividing network composed of the resistors R5 and R6 clamps the base voltage of Q2 to the low level corresponding to the logic "0", so that the voltage across R12 is clamped to the low level corresponding to the logic "0".

[0032] When the host MCU receives a logic signal, during reception, the sending end level remains at the logic "1" high level. At this time, both the triodes Q1 and Q2 are in the conducting state, and at this time the resistor R7 serves as a sampling resistor. When receiving a signal with logic "1", the triode Q3 is cut off, and the resistors R8 and R9 divide the voltage, so that the voltage across the resistor R4 is at a high level; when receiving a signal with logic "0", the triode Q3 conducts, the resistor R9 is short-circuited, and this point is the ground point, so that the voltage output to the interface MASTER1 through the resistor R4 is at a low level.

[0033] The working principle of the present utility model is as follows: The boost module is used to boost the direct current of 3 - 15V to 34V direct current for supplying the mbus transceiver module; the mbus transceiver module is used to realize the signal transceiver of the host MCU through nine chip resistors and three triodes.

[0034] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-mentioned exemplary embodiments, and without departing from the spirit or basic characteristics of the present utility model, the present utility model can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting.

[0035] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An M-Bus bus host circuit, characterized in that, The M-Bus bus host circuit includes: A boost module, which is used to boost the direct current of 3 - 15V to 34V direct current for supplying the mbus transceiver module; An mbus transceiver module, which is used to realize the signal transceiver of the host MCU through nine patch resistors and three triodes; The boost module is connected to the mbus transceiver module.

2. The M-Bus bus host circuit according to claim 1, wherein The boost module includes a voltage regulator U1, the model of the voltage regulator U1 is AP3015. The fifth terminal of the voltage regulator U1 is connected to the fourth terminal of the voltage regulator U1, one end of the inductor L1, one end of the capacitor C1, and one end of the fuse F1. The other end of the capacitor C1 is grounded. The other end of the fuse F1 is connected to the voltage VIN. The other end of the inductor L1 is connected to the first terminal of the voltage regulator U1 and the positive electrode of the diode D1. The negative electrode of the diode D1 is connected to one end of the resistor R1, one end of the capacitor C4, and the mbus transceiver module. The other end of the capacitor C4 is grounded. The other end of the resistor R1 is connected to one end of the resistor R2 and the third terminal of the voltage regulator U1. The other end of the resistor R2 is grounded.

3. The M-Bus bus master circuit according to claim 1, characterized in that, The mbus transceiver module includes resistors R3, R4, R5, R6, R7, R8, R9, R12, R13, triodes Q1, Q2, Q3. The base of the triode Q1 is connected to the third terminal of the interface MASTER1 through the resistor R3. The emitter of the triode Q1 is grounded. The collector of the triode Q1 is connected to one end of the resistor R5, one end of the resistor R6, and one end of the resistor R13. The other end of the resistor R5 is grounded. The other end of the resistor R6 is connected to the 34V voltage, one end of the resistor R8, one end of the resistor R12, and the first terminal of the interface M-PORT1. The second terminal of the interface M-PORT1 is connected to the other end of the resistor R12 and the emitter of the triode Q2. The base of the triode Q2 is connected to the other end of the resistor R13. The collector of the triode Q2 is connected to one end of the resistor R7 and the base of the triode Q3. The other end of the resistor R7 is grounded. The emitter of the triode Q3 is grounded. The collector of the triode Q3 is connected to the other end of the resistor R8, one end of the resistor R9, and one end of the resistor R4. The other end of the resistor R9 is grounded. The other end of the resistor R4 is connected to the fourth terminal of the interface MASTER1.

4. The M-Bus bus host circuit according to claim 3, characterized in that, The triodes Q1 and Q3 are NPN triodes.

5. The M-Bus bus master circuit according to claim 3, characterized in that The triode Q2 is a PNP triode.

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