Planar gate metal oxide semiconductor field effect transistor (MOSFET)
The N+ region thickness is precisely controlled in the planar gate MOSFET through the etching process and the backfill process to form an additional conductive channel, solving the problem of difficulty in reducing the on-resistance and achieving lower on-resistance and higher yields.
Patent Information
- Application Number
- CN202421668489.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-15
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-07-15
AI Technical Summary
The on-resistance of the existing planar gate MOSFETs is difficult to further reduce. Traditional processes have problems of process complexity and low yield when controlling the thickness of the N+ region clamped by the P+ channel region and the P body region.
The etching process and backfill process are used instead of the diffusion process or ion implantation process, and the N+ region thickness of the P+ channel region and the P body region is accurately controlled to be 3-5 nm to form an additional gate-controlled conductive channel.
It achieves the reduction of on-resistance, expands the design range of N+ zone thickness, adapts to different application scenarios, and improves the yield of the device.
Smart Images
Figure CN223067435U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a planar gate MOSFET. Background Art
[0002] In the field of power electronic device technology, as a commonly used power semiconductor, MOSFET has replaced triodes and become one of the most commonly used switching devices in the power semiconductor field.
[0003] In the decades of iteration of MOSFET, improving power density has always been one of the main development directions. Reducing the on-resistance value per unit area is the most effective method to improve the device power density and also one of the main R & D directions of MOSFET.
[0004] The main measures in the industry to reduce its on-resistance are to reduce the cell pitch and adopt the superjunction structure. With the improvement of process precision, the cell pitch of the planar gate MOSFET has been reduced to the theoretical limit in recent years. After 20 years of development, the superjunction structure has also reached the theoretical limit. Therefore, for reducing the on-resistance of the planar gate MOSFET, new technologies and new structures must be adopted to achieve the purpose of further reducing its on-resistance.
[0005] Integrating an additional gate-controlled conductive channel in the MOSFET through structural design is a novel method. The inventor of the present utility model applied for a planar gate MOSFET for reducing on-resistance and its manufacturing method on the same day. The utility model provides a structure and manufacturing method for integrating an additional gate-controlled conductive channel in the MOSFET. The P+ channel region is prepared by using a diffusion process or an ion implantation process. When the thickness of the N+ region clamped by the P+ channel region and the P body region is relatively large (greater than 100 nm), this method has the advantages of simple process and low cost. When the thickness of the N+ region clamped by the P+ channel region and the P body region is less than 100 nm, precise control of the thickness of the P+ channel region is required to ensure that the P+ channel region and the P body region are not connected, and there will be a problem of low yield in actual operation. Summary of the Utility Model
[0006] To solve the above problems, the present utility model uses an etching process + backfilling process to replace the diffusion process (ion implantation process). By controlling the etching rate, the thickness of the N+ region clamped by the P+ channel region and the P body region is precisely controlled within 3 - 5 nm, expanding the design range of the N+ region thickness of this structure, and realizing a planar gate MOSFET for different application scenarios.
[0007] The technical solution of the present utility model is as follows:
[0008] A planar-gate MOSFET includes a D-pole electrode, an epitaxial wafer, polysilicon, and an isolation layer arranged successively from bottom to top;
[0009] On the top of the epitaxial wafer are provided:
[0010] A P-body region, having several and spaced from each other, respectively extending downward from the top surface of the epitaxial wafer, and having a spacing from the bottom surface of the N-voltage withstand layer of the epitaxial wafer;
[0011] Several N+ regions, arranged at intervals in the P-body region, and extending downward from the top surface of the epitaxial wafer;
[0012] Several P+ channel regions, respectively extending downward along one side from the top surface of the N+ region;
[0013] A gate dielectric, located on the top surface of the epitaxial wafer;
[0014] Several polysilicons are provided and spaced from each other, respectively located on the top surface of the gate dielectric above the P+ channel region;
[0015] The isolation layer is respectively arranged on the top surface of the gate dielectric and the top surface of the polysilicon; the isolation layer on the top surface of the gate dielectric is located between adjacent polysilicons;
[0016] Inside the isolation layer are provided:
[0017] An S-pole electrode, extending downward from the top surface of the isolation layer into the P-body region, and connecting with the N+ region and the P-body region to form an ohmic contact;
[0018] A G-pole electrode, extending downward from the top surface of the isolation layer into the polysilicon, and forming an ohmic contact with the polysilicon.
[0019] Specifically, the epitaxial wafer includes an N+ substrate layer and an N-voltage withstand layer connected from bottom to top.
[0020] Specifically, the bottom of the substrate layer is provided with a D-pole electrode, and forms an ohmic contact with the N+ substrate layer.
[0021] Specifically, the thickness of the P-body region is 1 - 20 um, and the spacing distance is 1 - 10 um.
[0022] Specifically, the thickness of the N+ region is 0.5 - 10 um.
[0023] Advantages of the present utility model:
[0024] The utility model proposes a new preparation scheme, which uses an etching process + a backfilling process to replace the diffusion process (ion implantation process). By controlling the etching rate, the thickness of the N+ region clamped by the P+ channel region and the P body region can be accurately controlled within 3 - 5 nm, expanding the design range of the N+ region thickness of this structure to cope with different application scenarios.
[0025] Compared with the planar gate vertical-conducting MOSFET with a traditional structure, innovatively, a thin N+ layer is formed between the P body region and the P+ channel region of the device. When no voltage is applied to the G electrode in the off state, the N+ layer is completely depleted and non-conductive under the clamping of the P body region and the P+ channel region. When a positive voltage is applied to the G electrode in the on state, an inversion layer conductive channel is formed in the P+ channel region on one side of the gate oxide. At the same time, due to the application of a positive voltage to the G electrode, the N+ layer clamped by the P body region and the P+ channel region changes from the completely depleted state to the normal conductive state. The N+ layer and the inversion layer conductive channel are in parallel to jointly bear the current flow of the device, reducing the on-resistance of the planar gate vertical-conducting MOSFET. Description of the Drawings
[0026] Figure 1 is the process flow chart of the utility model;
[0027] Figure 2 is the schematic cross-sectional structure diagram of the device in step S100;
[0028] Figure 3 is the schematic cross-sectional structure diagram of the device in step S200;
[0029] Figure 4 is the schematic cross-sectional structure diagram of preparing the gate trench 4 in the N+ region 3;
[0030] Figure 5 is the schematic cross-sectional structure diagram of preparing the P+ channel region 5 in the gate trench 4;
[0031] Figure 6 is the schematic cross-sectional structure diagram of preparing the gate dielectric;
[0032] Figure 7 is the schematic cross-sectional structure diagram of preparing polysilicon;
[0033] Figure 8 is the schematic cross-sectional structure diagram of preparing the isolation layer;
[0034] Figure 9 is the schematic cross-sectional structure diagram of opening a window on the isolation layer;
[0035] Figure 10 is the schematic cross-sectional structure diagram of preparing the S electrode and the G electrode;
[0036] Figure 11 is the schematic cross-sectional structure diagram of preparing the D electrode;
[0037] In the figure, 1 is an epitaxial wafer, 2 is a P body region, 3 is an N+ region, 4 is a gate trench, 5 is a P+ channel region, 6 is a gate dielectric, 7 is polysilicon, 8 is an isolation layer, 9 is an S-pole electrode, 10 is a G-pole electrode, 11 is a D electrode, 12 is an N+ substrate layer, and 13 is an N- breakdown voltage layer. Specific embodiments
[0038] Embodiments of the present invention will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary only for explaining the present invention and should not be construed as limiting the present invention.
[0039] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.
[0040] The present invention will be described below with reference to FIGS. 1-11;
[0041] A method for manufacturing a planar-gate MOSFET with multiple conductive channels includes the following steps:
[0042] Step S100, preparing a plurality of P body regions 2 arranged at intervals in the epitaxial wafer 1, as Figure 2 shown;
[0043] Step S110, using a photolithography process to protect the external region of the P body region 2 with a mask; forming a plurality of spaced P body regions 2 through a diffusion process or an ion implantation process;
[0044] Correspondingly, the epitaxial wafer 1 is an N-type epitaxial wafer, which is composed of an N+ substrate layer 12 and an N- breakdown voltage layer 13 from bottom to top. The thickness of the epitaxial wafer 1 is 100-2000 um, the thickness of the N+ substrate layer 12 is 90-1500 um, the thickness of the N- breakdown voltage layer 13 is 10-500 um, the thickness of the P body region 2 is 1-20 um, and the spacing distance is 1-10 um; the doping concentration range of N-type doping is 1e 14 .cm -3 -1e 20 .cm -3 , and the doping concentration range of P-type doping is 1e 15 .cm -3 -1e20 . cm -3 , which is related to the setting of relevant parameters and the electrical design of the device;
[0045] In this embodiment, the thickness of the epitaxial wafer 1 is 350 um, the thickness of the N+ substrate layer 13 is 300 um, and the doping concentration is 2e 19 . cm -3 , the thickness of the N- breakdown voltage layer 14 is 50 um, and the doping concentration is 1e 16 . cm -3 , the thickness of the P body region 2 is 5 um, the spacing distance is 2 um, and the doping concentration is 1e 18 . cm -3 , and the P body region 2 is prepared by using the ion implantation process.
[0046] Step S200, preparing a plurality of spaced N+ regions 3 in the P body region 2, as Figure 3 shown;
[0047] Step S210, using the photolithography process, protecting the external region of the N+ region 3 with a mask; forming a plurality of spaced N+ regions 3 through the diffusion process or the ion implantation process;
[0048] Correspondingly, the N+ region 3 extends downward from the top surface of the epitaxial wafer 1, its bottom surface is higher than the bottom surface of the P body region 2, the thickness is 0.5 - 10 um, and the doping concentration range is 1e 18 . cm -3 -1e 20 . cm -3 , which is related to the setting of relevant parameters and the electrical design of the device;
[0049] In this embodiment, the thickness of the N+ region 3 is 3 um, and the doping concentration is 2e 19. cm -3 , and the N+ region 3 is prepared by using the ion implantation process.
[0050] Step S300, preparing a gate trench 4 in the N+ region 3 and preparing a P+ channel region 5 in the gate trench 4; as Figure 4 、 5 shown;
[0051] Step S310, using the photolithography process, protecting the external region of the gate trench 4 with a mask, and preparing the gate trench 4 through the etching process;
[0052] Step S320, forming a P+ channel region 5 in the gate trench 4 through chemical vapor deposition;
[0053] Correspondingly, the gate trench 4 extends downward from the top surface of the epitaxial wafer 1, its bottom surface is higher than the bottom surface of the N+ region 3, the depth is set to 0.5 - 10 um, the P+ channel region 5 fills the gate trench 4, and the doping concentration range is 1e18 .cm -3 -1e 20 .cm -3 , which is related to the setting of relevant parameters and the electrical design of the device;
[0054] In this embodiment, the gate trench 4 is prepared by an etching process, the depth of the gate trench 4 is 2.99 um, the P+ channel region 5 is prepared by chemical vapor deposition, and the doping concentration is 3e 18. cm -3 , and the thickness of the N+ region 3 below the P+ channel region 5 is 10 nm.
[0055] Step S400, a gate dielectric 6 is prepared on the epitaxial wafer 1, and a plurality of polysilicons 7 are prepared at intervals on the gate dielectric 6 above the P+ channel region 5, as Figure 6 , 7 shown;
[0056] Step S410, a gate dielectric 6 is prepared on the epitaxial wafer 1 using a thermal oxidation technique;
[0057] Step S420, through a photolithography process, the external region of the P+ channel region 5 is protected using a mask, and polysilicon 7 is prepared on the gate dielectric 6 above the P+ channel region 5 through chemical vapor deposition;
[0058] Correspondingly, the material of the gate dielectric 6 is SiO2, the thickness is set to 40 - 500 nm, and the thickness of the polysilicon 7 is set to 100 nm - 5 um;
[0059] In this embodiment, 80 nm of SiO2 is prepared as the gate dielectric 6 using a thermal oxidation technique, and 500 nm of polysilicon 7 is prepared using chemical vapor deposition.
[0060] Step S500, an isolation layer 8 is deposited on the gate dielectric 6 and the polysilicon 7, as Figure 8 shown;
[0061] And windows are opened at the N+ region 3 and the polysilicon 7, as Figure 9 shown, and the S - pole electrode 9 and the G - pole electrode 10 are respectively prepared, as Figure 10 shown;
[0062] Step S510, an isolation layer 8 is prepared by chemical vapor deposition, the external regions of the N+ region 3 and the polysilicon 7 are protected using a mask through a photolithography process, and windows are opened at the N+ region 3 and the polysilicon 7 using an etching process;
[0063] Step S520, corresponding S - pole electrode 9 and G - pole electrode 10 are prepared at the windows opened at the N+ region and the polysilicon 7 through a lift - off process or an etching process;
[0064] Accordingly, the isolation layer 8 plays a protective role, and its material is SiO2 or Si3N4. The thickness is set to 10 - 5000 nm. Window opening is performed using ICP dry etching, and the window opening depth is greater than the sum of the thicknesses of the isolation layer 8 and the gate dielectric 6. The S - pole electrode 9 extends downward from the top surface of the isolation layer 8, connects with the N+ region 3 and the P - body region 2, and forms an ohmic contact. The G - pole electrode 10 extends downward from the top surface of the isolation layer 8, connects with the polysilicon 7, and forms an ohmic contact;
[0065] In this embodiment, Si3N4 is used as the isolation layer 8, the thickness is set to 200 nm, window opening is performed using ICP dry etching, the window opening depth is 300 nm, and Al / Ti two - layer metal is used to prepare the S - pole electrode 9 and the G - pole electrode 10.
[0066] Step S600, prepare the D - pole electrode 11 at the bottom of the epitaxial wafer, and the entire device is fabricated; as Figure 11 shown;
[0067] Step S610, prepare the D - pole electrode 11 at the bottom of the epitaxial wafer 1 through a thinning process and a back - metallization process, and the entire device is fabricated;
[0068] Accordingly, the epitaxial wafer 1 is thinned using a thinning process, and the D - pole electrode 11 is prepared using a back - metallization process. The D - pole electrode 11 connects with the N+ substrate layer 12 and forms an ohmic contact;
[0069] In this embodiment, the 350 - um - thick epitaxial wafer 1 is thinned to 180 um using a thinning process, and Al / Ti two - layer metal is used to prepare the D - pole electrode 11, and the entire device is fabricated.
[0070] A planar - gate MOSFET with multiple conductive channels includes, from bottom to top in sequence, a D - pole electrode 11, an epitaxial wafer 1, a polysilicon 7, and an isolation layer 8;
[0071] On the top of the epitaxial wafer 1 are provided:
[0072] P - body regions 2, several of which are provided and spaced from each other, located within the N - breakdown voltage layer 13, respectively extending downward from the top surface of the epitaxial wafer 1, and the bottom surface thereof is higher than the bottom surface of the N - breakdown voltage layer 13;
[0073] N+ regions 3, several of which are provided, respectively located within the P - body regions 2, respectively extending downward from the top surface of the epitaxial wafer 1, and the bottom surface thereof is higher than the bottom surface of the P - body region 2;
[0074] Gate trenches 4, several of which are provided, respectively extending downward from the top surface of the corresponding N+ region 3, and the bottom surface thereof is higher than the bottom surface of the N+ region 3;
[0075] The P+ channel region 5 fills the gate trench 4. One side of the N+ region 3 and one side of the P+ channel region 5 are respectively in a straight line in the vertical direction with one side of the P body region 2.
[0076] In the P body region 2, a structure of P+ channel region 5, N+ region 3, and P body region 2 is formed vertically from top to bottom along the region where the P+ channel region 5 is located. In this structure, the N+ region 3 is completely depleted by the P+ channel region 5 and the P body region 2 above and below it.
[0077] The gate dielectric 6 is located on the top surface of the epitaxial wafer 1.
[0078] A number of polysilicons 7 are provided and spaced from each other, and are respectively located on the top surface of the gate dielectric 6.
[0079] The isolation layer 8 is respectively provided on the top surface of the gate dielectric 6 and the top surface of the polysilicon 7. The isolation layer 8 on the top surface of the gate dielectric 6 is located between adjacent polysilicons 7.
[0080] The isolation layer 8 is provided with:
[0081] The S - pole electrode 9 extends downward from the top surface of the isolation layer 8 into the P body region 2 and is connected to the N+ region 3 and the P body region 2 to form an ohmic contact.
[0082] The G - pole electrode 10 extends downward from the top surface of the isolation layer 8 into the polysilicon 7 and forms an ohmic contact with the polysilicon 7.
[0083] It is further defined that the epitaxial wafer 1 includes an N+ substrate layer 12 and an N - voltage - resistant layer 13 connected from bottom to top. The D - pole electrode 11 is connected to the N+ substrate layer 12 to form an ohmic contact.
[0084] The utility model has the following advantages:
[0085] Integrating an additional gate-controlled conductive channel in a MOSFET through structural design is a novel approach. The inventor of the present utility model applied for a planar-gate MOSFET for reducing on-resistance and its manufacturing method on the same day. The utility model provides a structure and manufacturing method for integrating an additional gate-controlled conductive channel in a MOSFET. The P+ channel region 5 is prepared by using a diffusion process or an ion implantation process. When the thickness of the N+ region 3 clamped by the P+ channel region 5 and the P body region 2 is relatively large (greater than 100 nm), this method has the advantages of simple process and low cost. When the thickness of the N+ region 3 clamped by the P+ channel region 5 and the P body region 2 is less than 100 nm, it is necessary to precisely control the thickness of the P+ channel region 5 to ensure that the P+ channel region 5 and the P body region 2 are not connected, which will result in a low yield problem in actual operations. In response to this problem, the present utility model proposes a new manufacturing scheme, using an etching process + backfilling process to replace the diffusion process (ion implantation process). By controlling the etching rate, the thickness of the N+ region 3 clamped by the P+ channel region 5 and the P body region 2 can be precisely controlled within 3 - 5 nm, expanding the design range of the thickness of the N+ region 3 of this structure to cope with different application scenarios.
[0086] Compared with the planar-gate vertical-conducting MOSFET with a traditional structure, the present utility model innovatively forms a thin N+ layer between the P body region and the P+ channel region of the device. When the G electrode is not applied with voltage in the off state, the N+ layer is completely depleted and non-conductive under the clamping of the P body region and the P+ channel region. When the G electrode is applied with a positive voltage in the on state, an inversion-layer conductive channel is formed in the P+ channel region on the side of the gate oxide. At the same time, due to the application of a positive voltage to the G electrode, the N+ layer clamped by the P body region and the P+ channel region changes from a completely depleted state to a normal conductive state. The N+ layer and the inversion-layer conductive channel are connected in parallel to jointly bear the current flow of the device, reducing the on-resistance of the planar-gate vertical-conducting MOSFET.
[0087] Regarding the content disclosed in this case, the following points need to be further explained:
[0088] The accompanying drawings of the embodiments disclosed in this case only relate to the structures involved in the embodiments disclosed in this case, and other structures can refer to the general design;
[0089] Without conflict, the embodiments disclosed in this case and the features in the embodiments can be combined with each other to obtain new embodiments;
[0090] The above is only the specific implementation manners disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case shall be subject to the protection scope of the claims.
Claims
1. A planar-gate MOSFET, characterized in that, It includes a D - pole electrode (11), an epitaxial wafer (1), polysilicon (7), and an isolation layer (8) arranged successively from bottom to top; On the top of the said epitaxial wafer (1), there are provided: P - body regions (2), several of which are provided and spaced from each other, each extending downward from the top surface of the epitaxial wafer (1), and having a spacing from the bottom surface of the N - breakdown voltage layer (13) of the epitaxial wafer (1); N+ regions (3), several of which are provided, spaced within the P - body regions (2), and extending downward from the top surface of the epitaxial wafer (1); P+ channel regions (5), several of which are provided, each extending downward along one side from the top surface of the N+ region (3); A gate dielectric (6), located on the top surface of the epitaxial wafer (1); The polysilicon (7) is provided in several and spaced from each other, each located on the top surface of the gate dielectric (6) above the P+ channel region (5); The isolation layer (8) is respectively provided on the top surface of the gate dielectric (6) and the top surface of the polysilicon (7); the isolation layer (8) on the top surface of the gate dielectric (6) is located between adjacent polysilicons (7); Inside the isolation layer (8), there are provided: An S - pole electrode (9), extending downward from the top surface of the isolation layer (8) into the P - body region (2), and connecting with the N+ region (3) and the P - body region (2) to form an ohmic contact; A G - pole electrode (10), extending downward from the top surface of the isolation layer (8) into the polysilicon (7), and forming an ohmic contact with the polysilicon (7).
2. The planar-gate MOSFET according to claim 1, wherein The epitaxial wafer (1) includes an N+ substrate layer (12) and an N - breakdown voltage layer (13) connected from bottom to top.
3. A planar-gate MOSFET according to claim 2, wherein At the bottom of the substrate layer (12), there is a D - pole electrode (11), which forms an ohmic contact with the N+ substrate layer (12).
4. A planar-gate MOSFET according to claim 1, characterized in that, The thickness of the P - body region (2) is 1 - 20 μm, and the spacing distance is 1 - 10 μm.
5. A planar-gate MOSFET according to claim 1, characterized in that, The thickness of the N+ region (3) is 0.5 - 10 μm.