Semiconductor device and chip
By using multiple sources to connect to conductive channels in HEMT devices, the manufacturing difficulty and volume increase caused by air bridges are solved, and the miniaturization and efficient production of semiconductor devices and chips are achieved.
Patent Information
- Application Number
- CN202422249103.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-13
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-09-13
AI Technical Summary
The existing HEMT devices with multi-gate structures realize interconnection of different sources through air bridges, resulting in increased manufacturing difficulty, low chip yield, increased volume and cumbersome production process, making it difficult to achieve miniaturization.
A plurality of sources are used to connect to the first conductive channel and the second conductive channel, and the second conductive channel is located in the epitaxial layer to achieve interconnection between the sources, avoid air bridges, simplify processing flow and reduce device volume.
It reduces processing difficulty, improves yield, reduces waste of production materials, simplifies the chip production process, and realizes the miniaturization of semiconductor devices and chips.
Smart Images
Figure CN223067436U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device and a chip. Background Art
[0002] A high electron mobility transistor (HEMT), also known as a modulation-doped field effect transistor (MODFET), is a type of field effect transistor and is widely used in circuit design and manufacturing such as power amplifiers and low-noise amplifiers. It is an important device in modern microwave integrated circuits. To improve the output power of a chip and increase the transmission distance of a signal, using a multi-gate structure HEMT device is the most direct and effective way.
[0003] However, for existing multi-gate structure HEMT devices, air bridges are usually used to realize the interconnection of different source electrodes, resulting in an increase in the volume of the HEMT device, which is not conducive to the miniaturization of the HEMT device. Summary of the Utility Model
[0004] This application provides a semiconductor device and a chip, which can avoid setting air bridges and is conducive to realizing the miniaturization of the semiconductor device.
[0005] This application provides a semiconductor device, including:
[0006] An epitaxial layer, including a first conductive channel and a second conductive channel, where the first conductive channel is disposed near a first side of the epitaxial layer;
[0007] A gate, a source electrode, and a drain electrode disposed on the first side, where there are multiple gate electrodes, source electrodes, and drain electrodes, and each source electrode is respectively connected to the first conductive channel and the second conductive channel, and each drain electrode is connected to the first conductive channel.
[0008] In some possible implementation manners, the epitaxial layer further includes a first barrier layer, a second barrier layer, and a buffer layer;
[0009] The first conductive channel is disposed between the first barrier layer and the second barrier layer, and the second conductive channel is disposed between the second barrier layer and the buffer layer.
[0010] In some possible implementation manners, a first two-dimensional electron gas is formed at an interface between the first barrier layer and the first conductive channel.
[0011] In some possible implementation manners, a second two-dimensional electron gas is formed at an interface between the second barrier layer and the second conductive channel.
[0012] In some possible embodiments, the source electrode penetrates through the first barrier layer, the first conductive channel, the second barrier layer, and the second conductive channel in sequence from the first side, and extends to the side of the buffer layer close to the second conductive channel.
[0013] In some possible embodiments, the drain electrode penetrates through the first barrier layer and the first conductive channel in sequence from the first side, and extends to the side of the second barrier layer close to the first conductive channel.
[0014] In some possible embodiments, the gate electrode is disposed on the side of the first barrier layer away from the first conductive channel.
[0015] In some possible embodiments, the gate electrode includes a T-shaped gate structure or a square gate structure.
[0016] In some possible embodiments, the epitaxial layer further includes a second side opposite to the first side, and a through hole is formed in the second side, and the through hole is opposite to one of the source electrodes;
[0017] The semiconductor device further includes a back gold layer, the back gold layer is attached to the second side and the inner wall of the through hole, and the back gold layer is connected to the source electrode opposite to the through hole.
[0018] In addition, the present application also provides a chip, including the semiconductor device provided in each of the above embodiments.
[0019] Advantages of the present application: In the semiconductor device provided by the present application, a second conductive channel in a constant conduction state is provided in the epitaxial layer, and multiple source electrodes can be interconnected through the second conductive channel. Thus, the processing difficulty of the semiconductor device can be significantly reduced, and the processing efficiency can be improved. In addition, the second conductive channel is located in the epitaxial layer, which can significantly reduce the volume of the semiconductor device, reduce the space occupation, and realize the miniaturization of the semiconductor device. At the same time, the problem of air bridge breakage can also be avoided. When the semiconductor device is applied to a chip, there is no need to provide a protective layer and other structures, which can simplify the chip manufacturing process, facilitate chip encapsulation, improve chip production capacity, and also improve the chip yield, reduce waste of production materials. In addition, it is also beneficial to realize the miniaturization of the chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.
[0021] Figure 1 Shows a schematic structural diagram of an existing multi-gate HEMT device;
[0022] Figure 2 Shows a schematic structural diagram of a semiconductor device in some embodiments;
[0023] Figure 3 Shows a partial schematic structural diagram of a semiconductor device in some embodiments.
[0024] Description of main component symbols:
[0025] 1000 - Semiconductor device;
[0026] 100 - Epitaxial layer; 101 - First side; 102 - Second side; 103 - Through hole; 110 - First barrier layer; 120 - First conductive channel; 130 - Second barrier layer; 140 - Second conductive channel; 150 - Buffer layer; 160 - Substrate; 171 - First two-dimensional electron gas; 172 - Second two-dimensional electron gas;
[0027] 210 - Source electrode; 220 - Drain electrode; 230 - Gate electrode;
[0028] 300 - Back gold layer;
[0029] 2100 - Air bridge. Detailed implementation manners
[0030] The embodiments of the present application will be described in detail below. Examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.
[0031] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application.
[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.
[0033] In this application, unless otherwise clearly specified and defined, terms such as "installed", "connected", "joined", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0034] In this application, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.
[0035] Combined Figure 1 As shown, as disclosed in the background art of this application, in existing HEMT devices with a multi-gate structure, the interconnection between different source electrodes 210 is usually achieved through an air bridge 2100. However, using the air bridge 2100 to achieve the interconnection between different source electrodes 210 has the following problems:
[0036] First, since the air bridge 2100 needs to be erected between two source electrodes 210, there will be a certain processing difficulty, which increases the manufacturing difficulty of the HEMT device and raises the production cost.
[0037] Second, since the air bridge 2100 is prone to problems such as breakage, the yield of the chips applied in the HEMT device is low, which easily causes waste of production materials.
[0038] Third, since the air bridge 2100 is erected between two source electrodes 210 and is located outside the epitaxial layer 100, it will increase the height of the HEMT device, and then lead to an increase in the overall volume of the HEMT device, which is not conducive to the miniaturization of the HEMT device.
[0039] IV. For plastic encapsulated chips, in order to avoid the breakage of the air bridge 2100, it is necessary to add a protective layer, which makes the manufacturing process of HEMT devices cumbersome, increases the production cost, and also leads to a further increase in the volume of HEMT devices, which is not conducive to the miniaturization of HEMT devices.
[0040] To solve the above problems, an embodiment of the present application provides a semiconductor device 1000, which can adopt a method different from that of the air bridge 2100 to realize the interconnection between different source electrodes 210. Among them, the semiconductor device 1000 can be a HEMT device.
[0041] As Figure 2 shown, the semiconductor device 1000 includes an epitaxial layer 100, a gate 230, a source electrode 210, and a drain 220.
[0042] Among them, the epitaxial layer 100 may include a first side 101 and a second side 102 arranged opposite to each other. In addition, the epitaxial layer 100 further has a first conductive channel 120 and a second conductive channel 140, and the first conductive channel 120 may be closer to the first side 101 than the second conductive channel 140.
[0043] The gate 230, the source electrode 210, and the drain 220 are all disposed on the first side 101 of the epitaxial layer 100. And there are multiple gate 230, source electrode 210, and drain 220. Among them, each source electrode 210 can be respectively connected to the first conductive channel 120 and the second conductive channel 140, and each drain 220 is connected to the first conductive channel 120.
[0044] In the embodiment, the first conductive channel 120 is disposed close to the gate 230 and can be modulated by the gate 230, that is, the gate 230 controls the conduction and cutoff of the first conductive channel 120. The second conductive channel 140 is far from the gate 230 and can be not modulated by the gate 230. The second conductive channel 140 can be in a constant conduction state to realize the interconnection between multiple source electrodes 210.
[0045] In the embodiment of the present application, the interconnection between multiple source electrodes 210 can be realized through the second conductive channel 140, and the second conductive channel 140 is located in the epitaxial layer 100. Compared with the air bridge 2100 in the traditional method, the present application can significantly reduce the processing difficulty of the semiconductor device 1000 and improve the processing efficiency. In addition, since the second conductive channel 140 is located in the epitaxial layer 100, the volume of the semiconductor device 1000 can be significantly reduced, the space occupation can be reduced, and the miniaturization of the semiconductor device 1000 can be realized. At the same time, the problem of breakage of the air bridge 2100 can also be avoided. When the semiconductor device 1000 is applied to a chip, there is no need to set up a protective layer and other structures, which can simplify the chip manufacturing process, facilitate the plastic encapsulation of the chip, improve the chip production capacity, and also improve the chip yield, reduce the waste of production materials. In addition, it is also beneficial to realize the miniaturization of the chip.
[0046] As Figure 2 shown, in some embodiments, the epitaxial layer 100 further includes a first barrier layer 110, a second barrier layer 130, and a buffer layer 150. The first conductive channel 120 may be located between the first barrier layer 110 and the second barrier layer 130, and the second conductive channel 140 may be located between the second barrier layer 130 and the buffer layer 150.
[0047] In some embodiments, the first barrier layer 110 may be an aluminum gallium nitride (AlGaN) layer, and the first conductive channel 120 may be a gallium nitride (GaN) layer. A first two-dimensional electron gas 171 may be formed at the interface between the first conductive channel 120 and the first barrier layer 110, enabling the transmission of electrical signals.
[0048] In other embodiments, the first barrier layer 110 may also be an indium gallium phosphide (InGaP) layer, and the first conductive channel 120 may also be an aluminum gallium arsenide (AlGaAs) layer.
[0049] In some embodiments, the second barrier layer 130 may be an aluminum gallium nitride (AlGaN) layer, and the second conductive channel 140 may be a gallium nitride (GaN) layer. A second two-dimensional electron gas 172 may be formed at the interface between the second conductive channel 140 and the second barrier layer 130, enabling the transmission of electrical signals.
[0050] In other embodiments, the second barrier layer 130 may also be an indium gallium phosphide (InGaP) layer, and the second conductive channel 140 may also be an aluminum gallium arsenide (AlGaAs) layer.
[0051] In some embodiments, the material for forming the buffer layer 150 may include, but is not limited to, nitrides or a combination of group III-V materials, such as aluminum nitride (AlN), indium nitride (InN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium gallium nitride (AlInGaN), etc.
[0052] In other embodiments, the epitaxial layer 100 may further include a substrate 160, and the substrate 160 may be disposed on a side of the buffer layer 150 away from the second conductive channel 140. Among them, the material for forming the substrate 160 may include, but is not limited to, silicon nitride (SiN), silicon carbide (SiC), or sapphire and other materials.
[0053] As Figure 3 shown, in other embodiments, the epitaxial layer 100 may further include a first barrier layer 110, a first conductive channel 120, a second barrier layer 130, a second conductive channel 140, and a substrate 160 that are sequentially stacked. Among them, the first barrier layer 110 may be disposed close to the first side 101, and the substrate 160 may be disposed close to the second side 102.
[0054] Of course, in some other embodiments, the epitaxial layer 100 may further include structural layers such as a nucleation layer (not shown in the figure), an insertion layer (not shown in the figure), etc., which can enable the semiconductor device 1000 to have better performance.
[0055] As Figure 2 shown, in some embodiments, the gate 230 may be selected as a T-shaped gate structure. The gate 230 may be disposed on a side of the first barrier layer 110 away from the first conductive channel 120.
[0056] In some other embodiments, the gate 230 may also be a square gate structure.
[0057] In the embodiments, the gate 230 may be set to two, three, six, eight or other numbers as needed, and multiple gates 230 may be sequentially arranged at intervals.
[0058] As Figure 2 shown, in some embodiments, the source electrode 210 may sequentially penetrate through the first barrier layer 110, the first conductive channel 120, the second barrier layer 130, and the second conductive channel 140 from the first side 101 of the epitaxial layer 100, and extend to a portion of the buffer layer 150 close to the second conductive channel 140. Accordingly, the source electrode 210 may be respectively connected to the first conductive channel 120 and the second conductive channel 140.
[0059] In addition, multiple source electrodes 210 may be arranged staggeredly with multiple gates 230. In some embodiments, two gates 230 may be arranged between two adjacent source electrodes 210.
[0060] As Figure 2 shown, in some embodiments, the drain electrode 220 may sequentially penetrate through the first barrier layer 110 and the first conductive channel 120 from the first side 101 of the epitaxial layer 100, and extend to a portion of the second barrier layer 130 close to the first conductive channel 120. Accordingly, the drain electrode 220 may be connected to the first conductive channel 120.
[0061] In the embodiments, multiple drain electrodes 220 may be respectively disposed between the gates 230 and the source electrodes 210. In some embodiments, one drain electrode 220 may be distributively arranged between two gates 230 among two adjacent source electrodes 210. Between the adjacent source electrode 210 and the drain electrode 220, one gate 230 may be distributively arranged correspondingly, and the conduction and cutoff between the pair of source electrode 210 and the drain electrode 220 may be controlled by the gate 230.
[0062] As Figure 2 shown, in some embodiments, a through hole 103 may be formed on the second side 102 of the epitaxial layer 100. The through hole 103 may extend along the thickness direction of the epitaxial layer 100 and extend to face a source electrode 210. Accordingly, the source electrode 210 opposite to the through hole 103 may be exposed through the through hole 103.
[0063] The semiconductor device 1000 further includes a back gold layer 300. The back gold layer 300 can be attached to the second side 102 of the epitaxial layer 100. And the back gold layer 300 can cover the inner wall of the through hole 103 and be connected to the source electrode 210 opposite to the through hole 103. Thus, the source electrode 210 can be grounded through the back gold layer 300, the grounding inductance of the source electrode 210 can be reduced, the frequency characteristics of the semiconductor device 1000 can be improved, and thereby the gain and efficiency of the semiconductor device 1000 at high frequencies can be enhanced. In some embodiments, the material of the back gold layer 300 may include, but is not limited to, metal materials such as gold (Au) or copper (Cu).
[0064] In some other embodiments, the source electrode 210 can also be grounded through a package bonding wire.
[0065] An embodiment also provides a chip, which may include the semiconductor device 1000 provided in the embodiment. Among them, the chip can be a chip structure such as a power amplifier chip or a low noise amplifier chip.
[0066] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0067] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.
Claims
1. A semiconductor device, characterized in that, Comprising: An epitaxial layer (100) including a first conductive channel (120) and a second conductive channel (140), wherein the first conductive channel (120) is disposed near a first side of the epitaxial layer (100); A gate (230), a source (210), and a drain (220) disposed on the first side, wherein there are a plurality of the gate (230), the source (210), and the drain (220), each of the sources (210) is respectively connected to the first conductive channel (120) and the second conductive channel (140), and each of the drains (220) is connected to the first conductive channel (120).
2. The semiconductor device according to claim 1, wherein, The epitaxial layer (100) further includes a first barrier layer (110), a second barrier layer (130), and a buffer layer (150); The first conductive channel (120) is disposed between the first barrier layer (110) and the second barrier layer (130), and the second conductive channel (140) is disposed between the second barrier layer (130) and the buffer layer (150).
3. The semiconductor device according to claim 2, wherein A first two-dimensional electron gas (171) is formed at an interface between the first barrier layer (110) and the first conductive channel (120).
4. The semiconductor device according to claim 2, wherein, A second two-dimensional electron gas (172) is formed at an interface between the second barrier layer (130) and the second conductive channel (140).
5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The source (210) sequentially penetrates the first barrier layer (110), the first conductive channel (120), the second barrier layer (130), and the second conductive channel (140) from the first side and extends to a side of the buffer layer (150) close to the second conductive channel (140).
6. The semiconductor device according to any one of claims 2 to 4, characterized in that, The drain (220) sequentially penetrates the first barrier layer (110) and the first conductive channel (120) from the first side and extends to a side of the second barrier layer (130) close to the first conductive channel (120).
7. The semiconductor device according to any one of claims 2 to 4, characterized in that, The gate (230) is disposed on a side of the first barrier layer (110) away from the first conductive channel (120).
8. The semiconductor device according to claim 1, characterized in that, The gate (230) includes a T-shaped gate structure or a square gate structure.
9. The semiconductor device according to claim 1, wherein, The epitaxial layer (100) further includes a second side opposite to the first side, and a through hole (103) is formed in the second side, and the through hole (103) is opposite to one of the sources (210); The semiconductor device further includes a back gold layer (300), the back gold layer (300) is attached to the second side and an inner wall of the through hole (103), and the back gold layer (300) is connected to the source (210) opposite to the through hole (103).
10. A chip, characterized in that, Including the semiconductor device according to any one of claims 1 to 9.