Low-resistance fast-response VDMOS device

Abstract

The utility model relates to the technical field of power semiconductor devices, and discloses a low-resistance fast-response VDMOS device, which comprises an N + substrate, a drain electrode and an N + region, a layer of N + substrate is deposited on the upper surface of the drain electrode, an N buffer region is arranged on the upper surface of the N + substrate, a layer of N-drift region is grown on the upper surface of the N buffer region, the N-drift region is a silicon wafer, and the silicon wafer is a silicon wafer. At least two continuous diffusion region P-body regions are arranged at the upper part in the N-drift region, a P + region and an N + region are formed in each P-body region, and the P + region and the N + region have the same depth; two conductive regions are arranged below a U groove, the conductive regions are P-type semiconductors, a second conductive doped region is arranged around each conductive region, a first conductive doped region is arranged between the two second conductive doped regions, and the concentrations of the first conductive doped region and the second conductive doped region are different, so that when the device works, current can move downwards more quickly, the current circulation rate is high, and the reliability of the device is improved. And the response speed of the device to the command is higher.

Description

Technical Field

[0001] The utility model relates to the technical field of power semiconductor devices, and more specifically discloses a low-resistance and fast-response VDMOS device. Background Art

[0002] Semiconductor is a material with conductivity between that of metals and insulators.

[0003] VDMOS is a type of power semiconductor device. VDMOS (vertical double-diffused metal-oxide semiconductor field-effect transistor) combines the advantages of bipolar transistors and ordinary MOS devices. Whether for switching applications or linear applications, VDMOS is an ideal power device. VDMOS is mainly applied to motor speed regulation, inverters, uninterruptible power supplies, electronic switches, high-fidelity audio, automotive electrical appliances, and electronic ballasts, etc.

[0004] Since the 1980s, the rapidly developing very large scale integrated circuit technology has injected new vitality into high-voltage and high-current semiconductors, and a batch of new voice-controlled power amplifier devices have emerged. The most representative product among them is the VDMOS power transistor. Under the control of an appropriate gate voltage, the semiconductor surface is inverted to form a conductive channel, and thus an appropriate amount of current flows between the drain and the source.

[0005] Existing VDMOS devices have problems such as large on-resistance and slow switching speed under conditions of high voltage, high current, etc., which affect their performance and application scope. Therefore, a low-resistance and fast-response VDMOS device is designed. Summary of the Invention

[0006] The utility model provides a low-resistance and fast-response VDMOS device, which can solve the problems of large on-resistance and slow switching speed existing in existing VDMOS devices under conditions of high voltage, high current, etc.

[0007] To solve the above technical problems, according to one aspect of the present utility model, more specifically, a low-resistance and fast-response VDMOS device is provided, which includes an N+ substrate, a drain electrode, and an N+ region. A layer of the N+ substrate is deposited on the upper surface of the drain electrode. The upper surface of the N+ substrate has an N buffer region. An N- drift region is grown on the upper surface of the N buffer region. The N- drift region is a silicon wafer. There is a continuous diffusion region P-body region above the interior of the N- drift region. The P-body region has at least two. A P+ region and the N+ region are formed inside each P-body region, and the P+ region and the N+ region have the same depth, and the sides of the N+ region and the P+ region are in contact. A U-groove is formed by downward depression inside the N- drift region. A gate electrode is disposed inside the U-groove. There are two conductive regions inside the N- drift region and below the U-groove. The conductive regions are P-type semiconductors. There is a second conductive doping region around each conductive region, and there is a first conductive doping region between the two second conductive doping regions.

[0008] In some embodiments, as a preferred technical solution, there is an N well inside the N- drift region and on the side far from the gate electrode, and the upper surface of the N well is in contact with the lower surface of a part of the P-body region.

[0009] In some embodiments, as a preferred technical solution, a gate dielectric layer is provided on the upper surface of the gate electrode, and the lower surface sides of the gate dielectric layer are also in contact with the upper parts of the P-body region and the N+ region at the same time.

[0010] In some embodiments, as a preferred technical solution, a source electrode wraps around the outside of the gate dielectric layer. The gate dielectric layer is a gate oxide layer, and the dielectric constant of the gate dielectric layer is 22 F / m - 25 F / m.

[0011] In some embodiments, as a preferred technical solution, Al ions are implanted into the P-body region, and P ions are implanted into the N well.

[0012] In some embodiments, as a preferred technical solution, the second conductive doping region is doped with N ions, and the first conductive doping region is doped with P ions.

[0013] In some embodiments, as a preferred technical solution, the first conductive doping region is triangular.

[0014] The beneficial effects of the low-resistance and fast-response VDMOS device of the present utility model are as follows:

[0015] In the present utility model, two conductive regions are provided below the U-groove. The conductive regions are P-type semiconductors. There is a second conductive doping region around each conductive region, and there is a first conductive doping region between the two second conductive doping regions. The concentrations of the first and second conductive doping regions are different. When the device is working, the current can move downward more quickly, the current flow rate is high, and the device responds to commands faster.

[0016] In the N-drift region of the present utility model, an N well is provided, and P ions are implanted into the N well. The N well improves the on-state characteristics of the device, has a small resistance, can conduct current better and reduce power loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The present utility model will be further described in detail below with reference to the drawings and specific implementation methods.

[0018] Figure 1 is a schematic structural diagram of the present utility model;

[0019] Figure 2 is a partially enlarged schematic structural diagram of the present utility model.

[0020] In the figure: 1, N+ substrate; 2, drain; 3, first conductive doping region; 4, conductive region; 5, second conductive doping region; 6, N buffer region; 7, N-drift region; 8, N well; 9, P-body region; 10, P+ region; 11, N+ region; 12, gate dielectric layer; 13, gate; 14, source; 15, U-groove. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0022] According to the attached Figure 1-2, a low-resistance and fast-response VDMOS device is provided, including an N+ substrate 1, a drain 2 and an N+ region 11. A layer of N+ substrate 1 is deposited on the upper surface of the drain 2. The N+ substrate 1 is a highly doped layer. The upper surface of the N+ substrate 1 has an N buffer region 6. A layer of N- drift region 7 is grown on the upper surface of the N buffer region 6. The N- drift region 7 is a silicon wafer. There is a continuous diffusion region P-body region 9 above the interior of the N- drift region 7. There are at least two P-body regions 9. A P+ region 10 and an N+ region 11 are formed inside each P-body region 9, and the P+ region 10 and the N+ region 11 have the same depth, and the sides of the N+ region 11 and the P+ region 10 are in contact. An U-groove 15 is formed by downward depression inside the N- drift region 7. A gate 13 is arranged inside the U-groove 15. There are two conductive regions 4 inside the N- drift region 7 and below the U-groove 15. The conductive regions 4 are P-type semiconductors. There is a second conductive doping region 5 around each conductive region 4. There is a first conductive doping region 3 between the two second conductive doping regions 5. There is an N well 8 inside the N- drift region 7 and on the side far from the gate 13. The upper surface of the N well 8 is in contact with the lower surface of part of the P-body region 9. The N well 8 can improve the on-resistance of the device. A gate dielectric layer 12 is arranged on the upper surface of the gate 13, and the lower surface sides of the gate dielectric layer 12 are also in contact with the upper parts of the P-body region 9 and the N+ region 11 at the same time. The gate dielectric layer 12 plays an isolation role to avoid leakage current of the gate 13. The outside of the gate dielectric layer 12 is wrapped with a source 14. The gate dielectric layer 12 is a gate oxide layer. The thickness of the gate dielectric layer 12 is 0.01um - 0.03um, and the dielectric constant of the gate dielectric layer 12 is 22F / m - 25F / m. The gate dielectric layer 12 improves the reliability of the VDMOS device and has a high resistance.

[0023] In this embodiment, Al ions are implanted into the P-body region 9, and P ions are implanted into the N well 8.

[0024] In this embodiment, the second conductive doping region 5 is doped with N ions, and the doping concentration is 2*10 3 cm -3 , the first conductive doping region 3 is doped with P ions, and the doping concentration is 2*10 4 cm -3 , and the doping concentration of the first conductive doping region 3 is greater than that of the second conductive doping region 5. By doping P ions and N ions, the current flow rate is high, which is beneficial to improving the working efficiency of the device, and the VDMOS device reacts faster.

[0025] In this utility model, two conductive regions 4 are provided below the U-groove 15. The conductive regions 4 are P-type semiconductors. There is a second conductive doping region 5 around each conductive region 4, and there is a first conductive doping region 3 between the two second conductive doping regions 5. The concentrations of the first and second conductive doping regions are different. When the device works, the current can move downward more quickly, the current flow rate is high, and the device responds to commands faster. An N-well 8 is provided inside the N-drift region 7. The N-well 8 improves the on-state characteristics of the device, has a small resistance, can conduct current better and reduce power loss.

[0026] In this embodiment, the first conductive doping region 3 is triangular, and the conductive region 4 is isosceles trapezoidal.

[0027] The working principle of this utility model is as follows:

[0028] By providing two conductive regions 4 below the U-groove 15. The conductive regions 4 are P-type semiconductors. There is a second conductive doping region 5 around each conductive region 4, and there is a first conductive doping region 3 between the two second conductive doping regions 5. The concentrations of the first and second conductive doping regions are different. When the device works, the current can move downward more quickly, the current flow rate is high, and the device responds to commands faster. An N-well 8 is provided inside the N-drift region 7. P ions are implanted in the N-well 8. The N-well 8 increases the on-resistance of the device, has a small resistance, can conduct current better and reduce power loss.

[0029] All electrical components mentioned herein are electrical components that exist in reality.

[0030] Of course, the above description is not a limitation of this utility model, and this utility model is not limited to the above examples. Changes, modifications, additions or substitutions made by those of ordinary skill in the art within the scope of the essence of this utility model also belong to the protection scope of this utility model.

Claims

1. A low-resistance and fast-response VDMOS device, characterized in that, It includes an N+ substrate (1), a drain (2), and an N+ region (11). A layer of the N+ substrate (1) is deposited on the upper surface of the drain (2). The upper surface of the N+ substrate (1) has an N buffer region (6). A layer of an N- drift region (7) is grown on the upper surface of the N buffer region (6). The N- drift region (7) is a silicon wafer. Above the interior of the N- drift region (7), there is a continuous diffused region P-body region (9). There are at least two P-body regions (9). Inside each P-body region (9), a P+ region (10) and the N+ region (11) are formed. The P+ region (10) and the N+ region (11) have the same depth, and the sides of the N+ region (11) and the P+ region (10) are in contact. An internal U-groove (15) is formed by downward depression inside the N- drift region (7). A gate (13) is arranged inside the U-groove (15). Two conductive regions (4) are provided inside the N- drift region (7) and below the U-groove (15). The conductive regions (4) are P-type semiconductors. There is a second conductive doping region (5) around each conductive region (4). There is a first conductive doping region (3) between the two second conductive doping regions (5).

2. A low-resistance fast-response VDMOS device according to claim 1, characterized in that On one side of the interior of the N- drift region (7) and away from the gate (13), there is an N well (8). The upper surface of the N well (8) is in contact with the lower surface of part of the P-body region (9).

3. A low-resistance and fast-response VDMOS device according to claim 1, characterized in that, A gate dielectric layer (12) is provided on the upper surface of the gate (13). The lower surface on both sides of the gate dielectric layer (12) is also in contact with the upper parts of the P-body region (9) and the N+ region (11) at the same time.

4. A low-resistance and fast-response VDMOS device according to claim 3, characterized in that, The outside of the gate dielectric layer (12) is wrapped with a source electrode (14). The gate dielectric layer (12) is a gate oxide layer. The dielectric constant of the gate dielectric layer (12) is 22 F / m - 25 F / m.

5. A low-resistance and fast-response VDMOS device according to claim 2, characterized in that Al ions are implanted into the P-body region (9), and P ions are implanted into the N well (8).

6. A low-resistance and fast-response VDMOS device according to claim 4, characterized in that, The second conductive doping region (5) is doped with N ions, and the first conductive doping region (3) is doped with P ions.

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