SD card batch testing device

Abstract

The utility model discloses an SD (Secure Digital) card batch testing device, which relates to the technical field of SD card batch testing and comprises a server case, a server mainboard and an SD card test backboard are fixedly arranged in the server case, a plurality of PCIe slots are formed in the server mainboard, a plurality of special backboard slot interfaces are formed in a front panel of the SD card test backboard, and a plurality of Slim sockets are formed in a rear panel of the SD card test backboard; a PCIe Regiver card is inserted into each PCIe slot, and each PCIe Regiver card is connected to the Slim socket through a plurality of special high-speed cables; an SD card test daughter board is inserted into each special backboard slot interface, a plurality of SD card seats electrically connected with the special backboard slot interfaces are sequentially arranged on each SD card test daughter board in parallel, and the SD card seats are used for clamping SD cards to be tested. According to the utility model, the full-rate test of a large batch of SD cards in a high-temperature state can be realized with low cost and high efficiency.

Description

Technical Field

[0001] The utility model relates to the technical field of SD card batch testing, and particularly relates to an SD card batch testing device. Background Art

[0002] The statements here only provide the background art related to the utility model, and do not necessarily constitute the prior art.

[0003] An SD card (Secure Digital Memory Card) is a new type of storage device designed to meet the requirements in various aspects such as security, capacity, performance, and usage environment. SD cards are usually mass-produced, and it is necessary to test the produced SD cards to ensure the effectiveness of their performance.

[0004] Currently, most of the traditional SD card function tests based on the embedded platform adopt manual testing methods, that is, manually operating the plugging and unplugging of the SD card, video playback in the card, read and write speed testing, etc. Their efficiency is low, and it is difficult to cover all error scenarios comprehensively. For example, traditional SD card production tests are all based on conventional temperatures, lacking tests for unconventional application scenarios such as industrial or security applications, and cannot be applied to all scenarios. Moreover, when facing the testing of a large number of produced SD cards, multiple devices are required for processing, the cost is high, and it is impossible to centrally manage all devices, summarize the results, and analyze the status.

[0005] In addition, currently, the relay platform-based method can also be used to implement SD card testing, but this testing method also requires additional hardware devices, and these hardware devices cannot simulate all scenarios when the SD card is actually reading and writing. Therefore, all scenarios when the SD card is in use cannot be covered during testing, and this testing method also cannot meet the testing pressure on the SD card (such as high temperature, full-speed read and write interfaces, etc.). Summary of the Utility Model

[0006] Aiming at the above problems and defects existing in the prior art, the utility model provides an SD card batch testing device, which provides a testing environment with pressure (including high temperature, full-speed read and write interfaces) for the production testing and finished product screening of industrial SD cards, and realizes the full-speed testing of a large number of SD cards at high temperature with low cost and high efficiency. It can comprehensively cover all read and write scenarios of the SD card and improve the adaptability of the SD card to the industrial environment.

[0007] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0008] An SD card batch testing device, including a server chassis; a server motherboard and an SD card test backplane are fixedly arranged in the server chassis. A plurality of PCIe slots are arranged on the server motherboard. A plurality of dedicated backplane slot interfaces are arranged on the front panel of the SD card test backplane, and a plurality of Slim sockets are arranged on the rear panel. A Cotex CPU electrically connected to the dedicated backplane slot interfaces and the Slim sockets is arranged on the SD card test backplane;

[0009] A PCIe Retimer card is inserted into each PCIe slot, and each PCIe Retimer card is connected to a Slim socket through a plurality of dedicated high-speed cables; an SD card test daughter board is inserted into each dedicated backplane slot interface, and a plurality of SD card seats electrically connected to the dedicated backplane slot interfaces are sequentially arranged in parallel on each SD card test daughter board, and the SD card seats are used for clamping the SD cards to be tested.

[0010] In a further technical solution, brackets are arranged on both sides of the SD card test backplane. The brackets are fixedly installed on the inner side surface of the server chassis through screws, and when the SD card test backplane is installed, the interior of the server chassis is divided into two parts of space, front and rear.

[0011] In a further technical solution, a temperature control module is arranged on the SD card test backplane, and the temperature control module is arranged in the front part of the server chassis where the SD card test daughter board is located.

[0012] In a further technical solution, the temperature control module includes a controller, a ceramic sheet and a fan. The controller is electrically connected to the Cotex CPU on the SD card test backplane, or the controller is directly integrated into the Cotex CPU on the SD card test backplane.

[0013] In a further technical solution, the front side surface of the server chassis is an SD card chassis panel, and a plurality of SD card insertion openings are evenly arranged on the SD card chassis panel. The plurality of SD card insertion openings correspond to the plurality of SD card seats one by one.

[0014] In a further technical solution, the PCIe slot is a 16-channel slot.

[0015] In a further technical solution, the dedicated high-speed cable adopts a Slim line.

[0016] In a further technical solution, the PCIe Retimer card is used to convert the PCIe signal issued by the server motherboard into a Slim signal.

[0017] In a further technical solution, a current detection sensor is connected in series in the circuit where each SD card socket on the SD card test daughter board is electrically connected to the dedicated backplane slot interface, and the current detection sensor is used to collect and monitor the voltage and power consumption of the SD card.

[0018] In a further technical solution, a dedicated communication protocol is configured in the dedicated backplane slot interface.

[0019] Compared with the prior art, the present utility model has the following beneficial effects:

[0020] 1. The present utility model provides an SD card batch testing device for the production testing and finished product screening of industrial SD cards. By designing a test backplane with a temperature control module and multiple test daughter boards, and each test daughter board is provided with multiple SD card sockets, so as to provide a test environment with pressure (including high temperature and full-speed read / write interfaces), and realize the full-speed testing of a large number of SD cards at high temperature with low cost and high efficiency. It can comprehensively cover all read / write scenarios of the SD card and improve the adaptability of the SD card to the industrial environment.

[0021] 2. Compared with the traditional embedded SD card testing system which can only test a single SD card, its testing cost is high. When it is necessary to achieve the throughput of testing a large number of SD cards simultaneously, it requires extremely high costs. At the same time, it also requires network management and a lumped server for background management, and a dedicated rack for assembly, with an extremely high total cost. The SD card batch testing device provided by the present utility model only needs one system or device to achieve lower-cost testing and can effectively reduce the system complexity.

[0022] 3. Compared with the traditional SD card testing system which can only test at normal temperature and requires sampling with dedicated expensive equipment when high and low temperatures are required, the SD card batch testing device provided by the present utility model can perform read / write / erase operations of various modes and speeds on each produced and screened SD card at a specified temperature to achieve pressure testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The specification drawings constituting a part of the present utility model are used to provide a further understanding of the present utility model. The schematic embodiments of the present utility model and their descriptions are used to explain the present utility model and do not constitute an improper limitation to the present utility model.

[0024] Figure 1 is a schematic structural diagram of the SD card batch testing device of the present utility model;

[0025] Figure 2 is a schematic structural diagram of the SD card test backplane in the SD card batch testing device of the present utility model, where (a) is a schematic front panel diagram of the SD card test backplane, and (b) is a schematic rear panel diagram of the SD card test backplane;

[0026] Figure 3 is the circuit schematic diagram when the SD card batch testing device described in the present utility model conducts testing;

[0027] Figure 4 is the circuit connection schematic diagram of the current detection sensor in the SD card test sub-board of the present utility model;

[0028] Figure 5 is the circuit connection schematic diagram of the SD card socket in the present utility model.

[0029] Among them, 1. Upper cover of the server chassis; 2. Server chassis; 3. PCIe Retimer card; 4. Server power supply; 5. Server motherboard; 6. SD card test backplane; 7. SD card chassis panel; 8. SD card test sub-board; 9. Temperature control module; 10. Dedicated backplane slot interface; 11. Cortex communication interface; 12. Slim socket; 13. Power supply interface; 14. SD card socket. Detailed implementation manners

[0030] It should be noted that the following detailed description is illustrative and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs.

[0031] It should be noted that the terms used herein are only for describing the specific implementation manners and are not intended to limit the exemplary implementation manners according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "include" and / or "comprise" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0032] Aiming at the traditional method of testing SD cards using an embedded test system / platform for testing, where its batch testing operation is complex and multiple units need to be cascaded during testing, resulting in a high system complexity and cost, and the fact that this system cannot achieve high and low temperature testing, the present utility model provides an SD card batch testing device, as Figure 1 shown. This device includes a server chassis 2, in which a server motherboard 5 and an SD card test backplane 6 are fixedly arranged. Among them, the server motherboard 5 can also be called a PC motherboard. The server motherboard 5 is provided with an electrically connected CPU and a memory module, and a test program is stored in the memory module. The CPU retrieves the test program in the memory module and drives the operation of the test program; the server motherboard 5 is provided with a plurality of PCIe slots electrically connected to the CPU, as Figure 2As shown in the figure, a plurality of dedicated backplane slot interfaces 10 are provided on the front panel of the SD card test backplane 6, and a plurality of Slim sockets 12 are provided on the rear panel. A Cotex CPU is provided in the SD card test backplane, and the Cotex CPU is electrically connected to the dedicated backplane slot interface 10 and the Slim socket 12.

[0033] Furthermore, a PCIe Retimer card 3 is inserted into each PCIe slot correspondingly. Each PCIe Retimer card is connected to the Slim socket of the test backplane through multiple dedicated high-speed cables. The PCIe Retimer card is used to convert the PCIe signal (i.e., the test signal of the test program) issued by the server motherboard into a Slim signal and transmit it to the test backplane through the dedicated high-speed cable. In this embodiment, the dedicated high-speed cable adopts a Slim data cable. Slim is a high-speed data cable with an interface adapted to PCIe, which is used to transmit the PCIe signal to the test backplane with low loss. Based on the above design, through the high-performance processor CPU on the server motherboard, combined with the high-bandwidth data channel PCIe, the ultra-low latency of the data channel is guaranteed, so as to achieve full rate. Compared with the existing distributed and embedded test systems, the rate of this test device and method in this embodiment can basically reach no loss, and full-rate testing is achieved by ensuring the system bandwidth.

[0034] Furthermore, for the SD card test backplane 6, an SD card test daughter board 8 is inserted into each dedicated backplane slot interface 10 correspondingly. A plurality of SD card seats 14 electrically connected to the dedicated backplane slot interface 10 are arranged in parallel on each SD card test daughter board 8 in sequence. The SD card seat 14 is used to insert the SD card to be tested. Preferably, for the SD card test daughter board 8, a connection interface matching the dedicated backplane slot interface 8 is provided on the daughter board, and each SD card seat 14 on the daughter board is electrically connected to the connection interface, which is convenient for transmitting the test signal to the SD card seat through the dedicated backplane slot interface.

[0035] Specifically, in the present utility model, a total of 4 PCIe slots are provided on the server motherboard, and the PCIe slots are 16-channel slots. The 4 PCIe Retimer cards inserted into each PCIe slot convert the PCIe signal in the server motherboard into a Slim signal; as Figure 2 and Figure 3As shown in the figure, there are 8 Slim sockets (or Slim interfaces) on the SD card test backplane. All PCIe Retimer cards are connected to the 8 Slim sockets on the SD card test backplane through 8 Slim cables. Since 4 SD card test daughter boards are respectively inserted into 4 dedicated backplane slot interfaces of the SD card test backplane, the test signals are converted and transmitted to the SD card test daughter boards through the SD card test backplane; the SD card test daughter boards convert the high-speed signals inside them into SD card interface signals and transmit them to 16 SD card holders arranged on the SD card test daughter boards. At the same time, the SD card voltage and power consumption of each terminal (i.e., the SD card holder) are monitored, so as to realize the read, write and erase operations of various mode data of 64 or 128 SD cards.

[0036] Furthermore, as Figure 3 shown, each SD card test daughter board (also called SD card wiping daughter board) is provided with a current detection sensor, that is, a current detection sensor is connected in series in the circuit (this circuit is arranged on the SD card test daughter board and includes a connection interface) where each SD card holder 14 is electrically connected to the dedicated backplane slot interface 10; the current detection sensor is electrically connected to the dedicated backplane slot interface, and a dedicated communication protocol is configured in the dedicated backplane slot interface 10. Specifically, the dedicated communication protocol includes a variety of existing communication protocols, including communication protocols based on TI's INA226 and multiple existing standards such as PCA9554. These communication protocols are all dedicated, and the objectives achieved by the present utility model can be achieved only by executing according to this protocol. In addition, in the present utility model, the current detection sensor adopted in the SD card test daughter board uses an INA226 chip to collect and monitor the voltage and power consumption of the SD card. As Figure 4 shown, the chip is electrically connected to the dedicated backplane slot interface and the SD card holder. The INA226 chip U1001 obtains the current value of the measurement resistor R1021 (i.e., the SD card holder in this embodiment) according to the voltage difference between the IN+ and IN- ends, and collects the output voltage value through VBUS, so as to obtain the power consumption and voltage passing through the measurement resistor R1021. In addition, it is connected to the dedicated backplane slot interface through the SDA and SCL dedicated communication interfaces and transmitted to the Cortex CPU. Among them, there are various deformation forms of the design of the above circuit, including but not limited to I2C, SPI, UART, etc.

[0037] Specifically, after the PCIe signal (i.e., the test signal) in the server motherboard is converted into a Slim signal by the PCIe Retimer card, it is transferred through a dedicated high-speed cable (i.e., the Slim cable) to the Slim socket on the rear panel of the SD card test backplane. The high-speed test signal (i.e., the Slim signal) is transferred to multiple dedicated backplane slot interfaces 10 by the Cotex CPU on the SD card test backplane. On this basis, the SD card test daughter board is inserted into the dedicated backplane slot interface on the front panel of the SD card test backplane. This slot interface uses a dedicated communication protocol to transmit the high-speed test signal to the SD card socket. In this way, the SD card test backplane receives the test signal. At the same time, the monitoring information of the SD card is transmitted to the Cotex CPU of the SD card test backplane through this dedicated communication protocol, so as to realize the monitoring of the power consumption voltage of the SD card in the test daughter board.

[0038] As another implementation, since there are multiple standards for SD cards, if the SD card to be tested is lower than the SD6.0 standard, a Bridge chip for converting PCIe to SD card can be added to the SD card test backplane, and this Bridge chip is electrically connected to the Cotex CPU; if the SD card to be tested is of the Express standard, the PCIe signal can be directly connected to the SD card socket. As Figure 5 shown, the SD card socket is used for the test of SD card insertion, and it is compatible with currently released SD card standards such as SD3.0, SD4.0, SD7.0, etc., and also supports the latest SD9.1 standard.

[0039] In addition, a server power supply 4 is also provided in the above-mentioned server chassis 2. The server power supply 4 is arranged at the rear of the server chassis and has multiple outputs. It is electrically connected to the server motherboard and the SD card test backplane respectively to supply power to each circuit board. Based on the above design, the server power supply 4 outputs to the SD card test backplane to supply power to the SD card test backplane (the Slim data cable only transmits PCIe data and does not transmit power for power supply). A power supply interface 13 is also provided on the above-mentioned SD card test backplane, and power is connected to the SD card test daughter board through this power supply interface; a power supply circuit is provided in the SD card test daughter board, and this power supply circuit is electrically connected to the power supply interface and the SD card socket. A power conversion circuit is provided in this power supply circuit, and the input power is converted into various voltages required by the SD card through the power conversion circuit. Among them, this power conversion circuit is an existing conventional circuit and is a general technology in this field, so it will not be elaborated here.

[0040] Based on the above design, since the dedicated backplane slot interface uses a dedicated communication protocol, the Cotex CPU can obtain the voltage and power consumption values of each SD card in the test daughter board through this interface (the present utility model uses the I2C interface); a Cortex communication interface 11 is also provided on the SD card test backplane. The SD card test backplane aggregates the received voltage and power consumption values of each SD card and transmits them to the server test control software background through the Cortex communication interface or network interface or USB interface, etc., compares them with the target values and makes records to complete the test of the SD card to be tested.

[0041] Furthermore, brackets are provided on both sides of the above-mentioned SD card test backplane. The brackets are fixedly installed on the inner side of the server chassis through screws. When the SD card test backplane is installed, the interior of the server chassis is divided into two parts of space, the part where the front panel of the SD card test backplane is located is the front part of the space, and a SD card test daughter board is provided in the front part of the space. The part where the rear panel of the SD card test backplane is located is the rear part of the space, and a server power supply and a server motherboard are provided in the rear part of the space.

[0042] Furthermore, the front side of the above-mentioned server chassis is a SD card chassis panel 7. The SD card chassis panel 7 is close to multiple SD card test daughter boards inside, and multiple SD card insertion ports are evenly arranged on the SD card chassis panel. The multiple SD card insertion ports respectively correspond to multiple SD card seats on the SD card test daughter board; one end of the SD card test daughter board is inserted into the dedicated backplane slot interface of the SD card test backplane, and the other end is fixedly screwed to the front side of the server chassis (i.e., the SD card chassis panel 7). As another implementation manner, the server chassis upper cover 1 is fixedly covered on the upper part of the server chassis by bolts to ensure the internal temperature circulation of the chassis during normal operation. Through the above design, the stability of each circuit board inside the server chassis is guaranteed, and the strength of the device is improved.

[0043] In addition, a temperature control module 9 is also provided on the SD card test backplane. The temperature control module 9 is arranged in the front part of the server chassis where the SD card test daughter board is located. The temperature control module 9 includes a controller, a ceramic sheet and a fan. Among them, the controller is electrically connected to the Cotex CPU on the SD card test backplane, or the controller is directly integrated into the Cotex CPU on the test backplane. The temperature control module is controlled by the Cotex CPU to control the heating of the ceramic sheet and the heat dissipation of the fan, so that the SD card area enters the heating or cooling state, and the temperature range of the SD card area is controlled, so as to realize the read and write test of the SD card under a specified temperature environment.

[0044] In the present utility model, through the above settings, the temperature of the working environment of the SD card can be adjusted from room temperature to 70 degrees. On this basis, a dedicated test software / program is built into the server motherboard to control the test script to start after the environmental temperature of the SD card reaches the target value, so as to realize the full-performance read-write-erase operations on 64 or 128 SD cards simultaneously.

[0045] Although the specific implementation manners of the present utility model are described above in conjunction with the accompanying drawings, they are not limitations on the protection scope of the present utility model. Those skilled in the art should understand that, based on the technical solutions of the present utility model, various modifications or deformations that can be made by those skilled in the art without creative efforts are still within the protection scope of the present utility model.

Claims

1. An SD card batch testing device, characterized in that, It includes a server chassis; a server motherboard and an SD card test backplane are fixedly arranged in the server chassis. A plurality of PCIe slots are provided on the server motherboard. A plurality of dedicated backplane slot interfaces are provided on the front panel of the SD card test backplane, and a plurality of Slim sockets are provided on the rear panel. A Cotex CPU electrically connected to the dedicated backplane slot interfaces and the Slim sockets is provided on the SD card test backplane; the temperature control module is controlled by the Cotex CPU to control the heating of the ceramic sheet and the heat dissipation of the fan. A PCIe Retimer card is inserted into each PCIe slot, and each PCIe Retimer card is connected to a Slim socket through a plurality of dedicated high-speed cables; an SD card test daughter board is inserted into each dedicated backplane slot interface, and a plurality of SD card holders electrically connected to the dedicated backplane slot interfaces are sequentially arranged in parallel on each SD card test daughter board, and the SD card holders are used for inserting the SD cards to be tested.

2. The SD card batch testing device according to claim 1, wherein, Supports are provided on both sides of the SD card test backplane, and the supports are fixedly installed on the inner side surface of the server chassis through screws, and the SD card test backplane divides the inner space of the server chassis into two parts, front and rear, when installed.

3. The SD card batch testing device according to claim 2, wherein A temperature control module is provided on the SD card test backplane, and the temperature control module is arranged in the front part space of the server chassis where the SD card test daughter board is located.

4. The SD card batch testing device according to claim 3, wherein The temperature control module includes a controller, a ceramic sheet and a fan. The controller is electrically connected to the Cotex CPU on the SD card test backplane, or the controller is directly integrated in the Cotex CPU on the SD card test backplane.

5. The SD card batch testing device according to claim 1, wherein, The front side surface of the server chassis is an SD card chassis panel, and a plurality of SD card insertion openings are evenly arranged on the SD card chassis panel, and the plurality of SD card insertion openings correspond to the plurality of SD card holders one by one.

6. The SD card batch testing device according to claim 1, wherein The PCIe slot is a 16-channel slot.

7. The SD card batch testing device according to claim 1, wherein, The dedicated high-speed cable uses a Slim line.

8. The SD card batch testing device according to claim 1, characterized in that, The PCIe Retimer card is used to convert the PCIe signal sent by the server motherboard into a Slim signal.

9. The SD card batch testing device according to claim 1, wherein A current detection sensor is connected in series in the circuit where each SD card holder on the SD card test daughter board is electrically connected to the dedicated backplane slot interface, and the current detection sensor is used to collect and monitor the voltage and power consumption of the SD card.

10. The SD card batch testing device according to claim 9, wherein, A dedicated communication protocol is configured in the dedicated backplane slot interface.

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