Pin multiplexing circuit, system and motor controller
Through the pin multiplexing circuit design, the shielding module is used to turn on shielding at high levels, which solves the problem of affecting circuit functions caused by pin multiplexing, and achieves a reduction in the number of pins and an improvement in circuit integration.
Patent Information
- Application Number
- CN202422213933.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-09
AI Technical Summary
In integrated applications of analog-to-digital converters and comparators, pin multiplexing causes problems that circuit function implementation is affected.
Through the pin multiplexing circuit design, including multiplexing pins, sampling and holding modules, comparison modules and shielding modules, the shielding module is used to turn on the shielding when the sampling and holding module output is high to avoid the incorrect voltage signal affecting the output of the comparison module.
It effectively reduces the number of pins, improves the integration of the circuit, and avoids misjudgment and incorrect shutdown of circuit functions, ensuring the normal operation of the circuit.
Smart Images
Figure CN223080021U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of circuit design, and particularly to a pin multiplexing circuit, a system and a motor controller. Background Art
[0002] In contemporary electronic engineering practice, pursuing the simplicity and cost-effectiveness of circuit design is a common goal of engineers. To achieve this goal, how to minimize components while still realizing functions has become an issue to be considered. In the integrated application of an analog-to-digital converter (ADC) and a comparator (CMP), reducing the required number of pins in the design through pin multiplexing can simplify the circuit board layout and also help reduce material and manufacturing costs. However, although pin multiplexing brings many benefits, it also introduces new challenges. The most important problem is whether the reduced components affect the realization of the functions of the circuit itself.
[0003] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solution of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Utility Model
[0004] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide a pin multiplexing circuit, which is used to solve the problems in the integrated application of an analog-to-digital converter and a comparator in the prior art, such as reducing the required number of pins through pin multiplexing but affecting the realization of circuit functions.
[0005] To achieve the above object and other related objects, the present utility model provides a pin multiplexing circuit, including: a multiplexing pin, a sample-and-hold module, a comparison module, and a shielding module;
[0006] The multiplexing pin is respectively connected to the first input end of the sample-and-hold module and the first input end of the comparison module;
[0007] The second input end of the comparison module is connected to a first voltage, and the output end is connected to the first input end of the shielding module, comparing the voltage magnitudes of the first input end and the second input end of the comparison module and obtaining a comparison result;
[0008] The first output end of the sample-and-hold module is connected to the second input end of the shielding module, sampling and holding the output signal of the first input end;
[0009] The control terminal of the shielding module is connected to a control signal, and based on the control signal, a logical judgment is made on the output signal of the sampling and holding module. When the output signal of the sampling and holding module is at a low level, the shielding is turned off and the output signal of the comparison module is output. Also, when the output signal of the sampling and holding module is at a high level, the shielding is turned on and the output signal is turned off.
[0010] Optionally, the shielding module includes a first AND gate and a second AND gate; the first input terminal of the first AND gate serves as the second input terminal of the shielding module, and the second input terminal is connected to the control signal; the first input terminal of the second AND gate serves as the first input terminal of the shielding module, and the second input terminal receives the output signal of the first AND gate after inversion, and the output terminal serves as the output terminal of the shielding module.
[0011] Optionally, the shielding module further includes an inverter; the inverter is disposed between the output terminal of the first AND gate and the second input terminal of the second AND gate.
[0012] Optionally, the control signal is set to a high-level signal.
[0013] Optionally, the pin multiplexing circuit further includes a quantization and encoding module; the input terminal of the quantization and encoding module is connected to the output terminal of the sampling and holding module, and the output terminal outputs a quantized and encoded digital signal.
[0014] To achieve the above and other related objectives, the present invention provides a pin multiplexing system, including: a control signal generation circuit, a channel control signal generation circuit, and the pin multiplexing circuit as described above;
[0015] The sampling and holding module includes a first input terminal and n second input terminals; n is an integer greater than or equal to 1;
[0016] The channel control signal generation circuit is connected to the control terminal of the sampling and holding module, and generates a control switching instruction to control the corresponding input terminal of the sampling and holding module to be turned on and start sampling;
[0017] The control signal generation circuit is connected to the control terminal of the sampling and holding module, and generates the control signal based on the switching instruction received by the control terminal; wherein, the switching instruction is set to be generated when any second input terminal of the sampling and holding module is switched to the first input terminal.
[0018] To achieve the above and other related objectives, the present invention provides a motor controller, including: a motor controller, a voltage converter, a three-phase gate driver, a motor, and a back electromotive force detector; the motor controller includes a timer and the pin multiplexing circuit as described above;
[0019] When the pin multiplexing circuit includes a quantization and encoding module; the multiplexed pin is connected to the output terminal of the back electromotive force detector; the output terminals of the comparison module and the quantization and encoding module are both connected to the input terminal of the timer; the timer performs overcurrent protection based on the output result of the comparison module; the timer obtains a phase control signal based on the output result of the quantization and encoding module;
[0020] The three-phase gate driver receives the phase control signal and converts it into three-phase winding signals to control the torque and speed of the motor;
[0021] The motor is connected to the output terminal of the three-phase gate driver and rotates based on the winding signals;
[0022] The back electromotive force detector is connected to the output terminal of the three-phase gate driver and is used to detect the corresponding back electromotive force;
[0023] The voltage converter is connected to the motor controller and the three-phase gate driver and is used to convert the external voltage into an internal voltage and supply power.
[0024] As described above, the pin multiplexing circuit, system, and motor controller of the present utility model have the following beneficial effects:
[0025] By multiplexing pins in the integrated application of the analog-to-digital converter and the comparator, the present utility model reduces the required number of pins, saves components, and improves the circuit integration level; at the same time, the present utility model solves the problem that the reduction of the number of pins affects the realization of the circuit function. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 It shows a waveform simulation diagram after multiplexing pins of a sampling and holding module and a comparison module.
[0027] Figure 2 It shows a schematic framework diagram of the pin multiplexing circuit of the present utility model.
[0028] Figure 3 It shows a first schematic structural diagram of the pin multiplexing circuit of the present utility model.
[0029] Figure 4 It shows a second schematic structural diagram of the pin multiplexing circuit of the present utility model.
[0030] Figure 5 It shows a schematic structural diagram of the motor controller of the present utility model.
[0031] Figure 6 It shows waveforms of the sampling and holding module and the comparison module before and after multiplexing pins using the pin multiplexing circuit of the present utility model.
[0032] Figure 7 It shows the waveform simulation diagram of the sampling and holding module and the comparison module sharing pins of the present utility model.
[0033] Element label description
[0034] 1 Motor controller
[0035] 11 Motor controller
[0036] 110 Pin multiplexing circuit
[0037] 111 Multiplexed pin
[0038] 112 Sampling and holding module
[0039] 113 Comparison module
[0040] 114 Shielding module
[0041] 1141 First AND gate
[0042] 1142 Second AND gate
[0043] 1143 Inverter
[0044] 115 Quantization and coding module
[0045] 110a Timer
[0046] 12 Voltage converter
[0047] 13 Three-phase gate driver
[0048] 131 Three-phase full-bridge inverter circuit
[0049] 14 Motor
[0050] 15 Back electromotive force detector Specific implementation manners
[0051] The following uses specific specific examples to illustrate the implementation manners of the present utility model. Those skilled in the art can easily understand other advantages and effects of the present utility model from the content disclosed in this specification. The present utility model can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present utility model.
[0052] Please refer to Figures 1 to 7It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present utility model. Therefore, only the components related to the present utility model are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0053] In the applications of analog-to-digital converters (ADCs) and comparators (CMPs), by setting the pin multiplexing, not only can space be saved, but also the overall efficiency of the system can be improved. However, in some applications, the sampling pin of the ADC and the current protection P terminal of the CMP share the same pin (PIN). This design strategy allows voltage sampling and current protection monitoring to be performed simultaneously on the same pin. Such pin multiplexing can significantly reduce the number of pins required, thereby saving circuit board space and reducing costs. However, this multiplexing scheme also has certain risks. When the ADC switches from a high-voltage channel to a low-voltage channel for sampling, as Figure 6 shown in part A, assuming that the sampling module 112 first samples a high-voltage signal (such as the second input terminal samples a high-voltage signal), when switching to a new input channel, since the sample-and-hold module 112 will maintain a certain level state for a certain period of time, it may in turn affect the voltage state of the multiplexed pin 111, resulting in the comparison module 112 and the sample-and-hold module 113, which should have changed synchronously. At the moment after the channel switching is completed, an abnormal voltage is detected at the first input terminal of the comparison module shared with this multiplexed pin, such as Figure 6 shown in part B, thereby erroneously triggering the current protection mechanism. The simulation diagram of the specific process is as Figure 1 shown. It can be observed that during the switching process of the sample-and-hold module (such as Figure 1 when sampling through the sampling excitation signal), the comparison module will output a wrong comparison result due to the high-voltage signal continuously maintained by the sample-and-hold module, resulting in a misjudgment of it.
[0054] Based on this, as Figure 2 shown, this embodiment provides a pin multiplexing circuit 110, which ensures that when the sampled pin maintains a high level, it will not affect the comparison module 113 from regarding the wrong voltage signal as an overvoltage, resulting in the circuit being wrongly turned off, through the setting of the shielding module 114.
[0055] As Figure 2 shown, a pin multiplexing circuit 110 provided in this embodiment includes: a multiplexed pin 111, a sample-and-hold module 112, a comparison module 113, and a shielding module 114.
[0056] As Figure 2As shown, the multiplexing pin 111 is respectively connected to the first input end of the sample and hold module 112 and the first input end of the comparison module 113.
[0057] Specifically, in this embodiment, the multiplexing pin 111 serves as the common pin for the first input end of the sample and hold module 112 and the first input end of the comparison module 113. Compared with connecting the first input end of the sample and hold module 112 and the first input end of the comparison module 113 through two separate pins, this embodiment can further reduce the number of pins, effectively improve the circuit integration degree, and will not affect the realization of the circuit's own functions.
[0058] As Figure 2 shown, the second input end of the comparison module 113 is connected to a first voltage, and the output end is connected to the first input end of the shielding module 114.
[0059] Specifically, in this embodiment, the first voltage serves as a reference voltage. The comparison module 113 compares the voltage signal received at the first input end with the first voltage, obtains a comparison result and outputs it to the shielding module 114. When the shielding module 114 turns off the shielding, the comparison result is output through the shielding module 114; when the shielding module 114 turns on the shielding, the comparison result will not be output, so as to solve the problem that the circuit is wrongly turned off because an incorrect voltage signal is regarded as an overvoltage.
[0060] In this embodiment, the first input end of the comparison module 113 is set as the P end, and the second input end is set as the N end. In this embodiment, the comparison module 113 is set as an overcurrent (overvoltage) protection module, which compares the collected voltage signal with the reference voltage. When the collected voltage signal is higher than the reference voltage, it outputs a comparison result to the subsequent circuit to turn off the entire circuit and avoid damaging components.
[0061] As Figure 2 shown, the first output end of the sample and hold module 112 is connected to the second input end of the shielding module 114.
[0062] Specifically, the sample and hold module 112 collects the signal of the multiplexing pin and holds and outputs it. The shielding module 114 determines the output signal of the sample and hold module 112 to ensure that the sample and hold module 112 will not affect the output of the comparison module 113 during the period of continuously holding a high voltage, causing the current protection function to be accidentally triggered.
[0063] In this embodiment, one of the first output terminals in the sample-and-hold module 112 is connected to the shielding module 114, and cooperates with the control signal to control the opening or closing of the shielding of the shielding module 114. At the same time, the second output terminal in the sample-and-hold module 112 further outputs the held signal to the subsequent circuit for subsequent processing.
[0064] As Figure 2 shown, the control terminal of the shielding module 114 is connected to the control signal, and based on the control signal, a logical judgment is made on the output signal of the sample-and-hold module 112, and is used to turn off the shielding and output the output signal of the comparison module 113 when the output signal of the sample-and-hold module 112 is at a low level, and, when the output signal of the sample-and-hold module 112 is at a high level, turn on the shielding and turn off the output signal.
[0065] Specifically, as Figure 3 shown, the shielding module 114 includes a first AND gate 1141 and a second AND gate 1142; the first input terminal of the first AND gate 1141 serves as the second input terminal of the shielding module 114, and the second input terminal is connected to the control signal; the first input terminal of the second AND gate 1142 serves as the first input terminal of the shielding module 114, and the second input terminal receives the output signal of the first AND gate after inversion, and the output terminal serves as the output terminal of the shielding module 114.
[0066] In this embodiment, the control signal is set as a high-level signal. By setting two AND gates, when it is detected that the sample-and-hold module 112 outputs a high level, the shielding signal outputs a high level and is inverted to output a low level to ensure that the second AND gate 1142 will not transmit the output result of the comparison module 113. That is: in this embodiment, by simultaneously detecting the output signals of the sample-and-hold module 112 and the comparison module 113, the output of the comparison module 113 is avoided when the sample-and-hold module 112 outputs a high level.
[0067] As an example, the shielding module 114 further includes an inverter 1143; the inverter 1143 is disposed between the output terminal of the first AND gate 1141 and the second input terminal of the second AND gate 1142. In this embodiment, the shielding signal is inverted and output to the second AND gate 1143 through the inverter 1143. Actually, other ways can also be set to adjust the signal level, and this embodiment is not limited thereto.
[0068] It should be noted that the specific setting of the shielding module 114 is not limited to this embodiment, and any setting that can achieve switching the level of the sample-and-hold module 112, especially when switching from a high level to a low level, may cause the comparison module 113 to misjudge that its current is too large and shield the output of the comparison module 113 is within the protection scope of this embodiment.
[0069] As Figure 2 shown, the pin multiplexing circuit further includes a quantization encoding module 115; an input end of the quantization encoding module 115 is connected to an output end of the sample-and-hold module 112, and a digital signal after quantization encoding is output from the output end.
[0070] Specifically, in this embodiment, the sample-and-hold module 112 and the quantization encoding module 115 cooperate together to implement the function of converting an analog signal into a digital signal.
[0071] This embodiment provides a pin multiplexing system, including: a control signal generation circuit (not shown in the figure), a channel control signal generation circuit (not shown in the figure), and the above-mentioned pin multiplexing circuit 110.
[0072] The sample-and-hold module 112 includes a first input end and n second input ends; n is an integer greater than or equal to 1; the channel control signal generation circuit is connected to a control end of the sample-and-hold module 112 to generate a control switching instruction to control the corresponding input end of the sample-and-hold module 112 to be turned on and start sampling; the control signal generation circuit is connected to the control end of the sample-and-hold module 112 to generate the control signal based on the switching instruction received by the control end; wherein, the switching instruction is set to be generated when any second input end of the sample-and-hold module 112 is switched to the first input end.
[0073] In this embodiment, the control signal is generated by the control signal generation circuit. By detecting the control instruction sent by the channel control signal generation circuit to the sample-and-hold module 112, it is determined that when each second input end is switched to the first input end, it is necessary to ensure that the performance of the common pin 111 is stable and the current will not be shut down due to overcurrent protection caused by misjudgment. In another embodiment, the control signal can be always set to a high level to ensure that the voltage continuously sampled by the sample-and-hold module 112 can always be detected.
[0074] As Figure 5 shown, this embodiment provides a motor controller 1, including: a motor controller 11, a voltage converter 12, a three-phase gate driver 13, a motor 14, and a back electromotive force detector 15; the motor controller 11 includes a timer 110a and the above-mentioned pin multiplexing circuit 110.
[0075] As Figure 5As shown, when the pin multiplexing system 110 includes the quantization and encoding module 115; the multiplexed pin 111 is connected to the output end of the back electromotive force detector 15; the output ends of both the comparison module 113 and the quantization and encoding module 115 are connected to the input end of the timer 110a; the timer 110a performs overcurrent protection based on the output result of the comparison module 113; the timer 110a obtains a phase control signal based on the output result of the quantization and encoding module 115;
[0076] As Figure 5 shown, the three-phase gate driver 13 receives the phase control signal and converts it into a three-phase winding signal, thereby controlling the torque and speed of the motor 14.
[0077] Specifically, in this embodiment, the three-phase winding signals of the three-phase gate driver 13 are output to the motor 14 through the three-phase full-bridge inverter circuit 131 to control the movement of the motor. In the three-phase inverter, by means of the pulse width modulation duty ratio of the timer and / or the level regulation method, the upper transistor of a certain phase inverter is turned on, and at the same time, the lower transistor of a certain phase inverter is turned on, ultimately to control the rotation of the motor.
[0078] As Figure 5 shown, the motor 14 is connected to the output end of the three-phase gate driver 13 and rotates based on the three-phase winding signal.
[0079] As Figure 5 shown, the back electromotive force detector 15 is connected to the output end of the three-phase gate driver 13 and is used to detect the corresponding back electromotive force.
[0080] In this embodiment, setting to collect and output the back electromotive force of the output signal of the three-phase full-bridge inverter circuit 131 is actually to collect the back electromotive force on a certain conducting branch and output it to the corresponding multiplexed pin 111.
[0081] As Figure 5 shown, the voltage converter 12 is connected to the motor controller 11 and the three-phase gate driver 13 and is used to convert the external voltage into an internal voltage and supply power. In this embodiment, the voltage converter 12 is set to reduce the amplitude of the external voltage and convert it into a second voltage to supply power internally.
[0082] Next, the working process of the motor controller 1 will be described in conjunction with Figure 5 as follows:
[0083] In this embodiment, based on the motor controller 11, a three-phase gate driver 13 is driven to generate corresponding three-phase winding signals, and then the torque and speed of the motor 14 are controlled. Among them, the back electromotive force detector 15 is used to detect the back electromotive force of the motor 14. Since the specific back electromotive force is directly related to the position and speed of the rotor of the motor 14, by monitoring the back electromotive force in real time, the accurate position and speed of the rotor can be deduced to achieve sensorless control. The back electromotive force signal is output to the comparison module 113 and the sample and hold module 112 respectively through the multiplexing pin 111. On the one hand, the comparison module 113 determines overcurrent (overvoltage) and outputs the comparison result to the timer 110a. On the other hand, analog-to-digital conversion is performed through the sample and hold module 112 and the quantization and encoding module 115 to output the state of the back electromotive force to the timer 110a, so as to adjust the rotation of the motor according to the result of the back electromotive force.
[0084] It should be noted that, in this embodiment, the multiplexing pin 111 serves as both the acquisition pin for overcurrent protection and the sampling pin for analog-to-digital conversion. In actual settings, the acquisition pin for overcurrent protection can be set at any position in the circuit that requires overcurrent protection. Similarly, the sampling pin position for analog-to-digital conversion can also be set according to needs. The specific setting is not limited to this embodiment. As long as at least one pin of the comparison module 113 for current protection and the sample and hold module 112 is multiplexed based on the setting method of this embodiment, it falls within the protection scope of this embodiment.
[0085] In addition, the pin multiplexing circuit 11 of this embodiment is not limited to the application field of the motor controller 1. As long as it is an integrated application of an analog-to-digital converter (ADC) and a comparator (CMP), it is applicable to the pin multiplexing circuit 11 of this embodiment.
[0086] Based on the pin multiplexing circuit 11 of this embodiment, as shown in Figure 6 part C, through the shielding signal generated by the shielding module 114, the comparison module will continuously perform comparisons and obtain corresponding comparison results (including non-overvoltage and overvoltage). In this embodiment, comparisons will be continuously performed 5 times to obtain 5 comparison results and output them internally. And based on the shielding module 114 of this embodiment, it will block the wrong output of the output signal of the comparison module 113 (the overvoltage result in part B) and shield it from being output, avoiding the wrong perceived overvoltage result from being perceived subsequently, causing the overall circuit to shut down, and ensuring the normal operation of the circuit. The specific working simulation process is as shown in Figure 7 When the sample and hold module receives the sampling excitation signal and starts sampling, through the setting of the shielding module, it is ensured that the first input terminal of the comparison module can output stably without being affected.
[0087] In summary, the present utility model provides a pin multiplexing circuit, a system and a motor controller. The pin multiplexing circuit includes: a multiplexing pin, a sample and hold module, a comparison module and a shielding module; the multiplexing pin is respectively connected to the first input end of the sample and hold module and the first input end of the comparison module; the output end of the comparison module is connected to the first input end of the shielding module; the first output end of the sample and hold module is connected to the second input end of the shielding module; the control end of the shielding module is connected to a control signal, and based on the control signal, a logical judgment is made on the output signal of the sample and hold module. When the output signal of the sample and hold module is at a high level, the shielding is turned on and the output signal is turned off. By multiplexing pins in the integrated application of an analog-to-digital converter and a comparator, the present utility model reduces the number of required pins, saves components, and improves the circuit integration level. At the same time, the present utility model solves the problem that the reduction of the number of pins affects the realization of the circuit function. Therefore, the present utility model effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0088] The above embodiments are only illustrative of the principles and effects of the present utility model and are not intended to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present utility model should still be covered by the claims of the present utility model.
Claims
1. A pin multiplexing circuit, characterized in that, The pin multiplexing circuit at least includes: a multiplexing pin, a sample and hold module, a comparison module, and a shielding module; The multiplexing pin is respectively connected to the first input end of the sample and hold module and the first input end of the comparison module; The second input end of the comparison module is connected to a first voltage, and the output end is connected to the first input end of the shielding module, comparing the voltage magnitudes of the first input end and the second input end of the comparison module and obtaining a comparison result; The first output end of the sample and hold module is connected to the second input end of the shielding module, sampling and holding the output signal of the first input end; The control end of the shielding module is connected to a control signal, logically judging the output signal of the sample and hold module based on the control signal, turning off the shielding and outputting the output signal of the comparison module when the output signal of the sample and hold module is at a low level, and turning on the shielding and turning off the output signal when the output signal of the sample and hold module is at a high level.
2. The pin multiplexing circuit according to claim 1, wherein: The shielding module includes a first AND gate and a second AND gate; The first input end of the first AND gate serves as the second input end of the shielding module, and the second input end is connected to the control signal; The first input end of the second AND gate serves as the first input end of the shielding module, the second input end receives the output signal of the first AND gate after inversion, and the output end serves as the output end of the shielding module.
3. The pin multiplexing circuit according to claim 2, wherein: The shielding module further includes an inverter; the inverter is arranged between the output end of the first AND gate and the second input end of the second AND gate.
4. The pin multiplexing circuit according to claim 1, wherein: The control signal is set as a high-level signal.
5. The pin multiplexing circuit according to claim 1, wherein: The pin multiplexing circuit further includes a quantization and encoding module; the input end of the quantization and encoding module is connected to the output end of the sample and hold module, and the output end outputs a quantized and encoded digital signal.
6. A pin multiplexing system, characterized in that, The pin multiplexing system includes a control signal generation circuit, a channel control signal generation circuit, and the pin multiplexing circuit according to any one of claims 1 to 5; The sample and hold module includes one first input end and n second input ends; n is an integer greater than or equal to 1; The channel control signal generation circuit is connected to the control end of the sample and hold module, generating a control switching instruction to control the corresponding input end of the sample and hold module to be turned on and start sampling; The control signal generation circuit is connected to the control end of the sample and hold module, generating the control signal based on the switching instruction received by the control end; wherein, the switching instruction is set to be generated when any second input end of the sample and hold module is switched to the first input end.
7. A motor controller, characterized in that, The motor controller includes a motor controller, a voltage converter, a three-phase gate driver, a motor, and a back electromotive force detector; the motor controller includes a timer and the pin multiplexing circuit according to any one of claims 1 to 5; When the pin multiplexing circuit includes a quantization and encoding module; the multiplexed pin is connected to the output end of the back electromotive force detector; the output ends of the comparison module and the quantization and encoding module are both connected to the input end of the timer; the timer performs overcurrent protection based on the output result of the comparison module; the timer obtains a phase control signal based on the output result of the quantization and encoding module; The three-phase gate driver receives the phase control signal and converts it into three-phase winding signals to control the torque and speed of the motor; The motor is connected to the output end of the three-phase gate driver and rotates based on the winding signals; The back electromotive force detector is connected to the output end of the three-phase gate driver and is used to detect the corresponding back electromotive force; The voltage converter is connected to the motor controller and the three-phase gate driver and is used to convert the external voltage into an internal voltage and supply power.