Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure includes a plurality of nanostructures formed over a substrate and a gate structure formed on the nanostructures. The semiconductor structure includes a source / drain structure formed adjacent to the gate structure and an inner spacer layer between the gate structure and the source / drain structure. The semiconductor structure includes a barrier layer adjacent to the inner spacer layer, and the barrier layer is between the inner spacer layer and the nanostructure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor technology, and more particularly to a semiconductor structure having a barrier layer. Background Art

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can simultaneously support more increasingly complex and sophisticated functions. As a result, the integrated circuit (IC) industry has been trending towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing the IC size (e.g., the minimum IC feature size), thereby improving production efficiency and reducing associated costs. However, such miniaturization has also increased the complexity of IC processes. Therefore, achieving continuous development of IC devices and their performance requires similar development of IC processes and technologies.

[0003] Recently, multi-gate devices have been introduced in an attempt to improve gate control, reduce off-state current, and reduce the short-channel effect (SCE) by increasing gate-channel coupling. However, the integration of multi-gate device fabrication can be challenging. Summary of the Utility Model

[0004] A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate and a gate structure formed over the nanostructures. The semiconductor structure includes a source / drain structure formed adjacent to the gate structure and an inner spacer layer located between the gate structure and the source / drain structure. The semiconductor structure includes a barrier layer adjacent to the inner spacer layer, and the barrier layer is located between the inner spacer layer and the nanostructures.

[0005] In some embodiments, the barrier layer directly contacts the plurality of nanostructures and the source / drain structure.

[0006] In some embodiments, the barrier layer is formed on an outer sidewall surface of the plurality of nanostructures.

[0007] In some embodiments, the barrier layer is located between the inner spacer layer and the source / drain structure.

[0008] In some embodiments, the inner spacer layer has a curved surface protruding towards the gate structure, and the barrier layer is formed on the curved surface of the inner spacer layer. In some embodiments, a sidewall surface of the barrier layer is aligned with a sidewall surface of the inner spacer layer.

[0009] A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures formed above a substrate and an inner spacer layer located between two adjacent nanostructures. The semiconductor structure includes a source / drain structure formed adjacent to the inner spacer layer and a blocking layer adjacent to the inner spacer layer. The blocking layer extends from a first position between the inner spacer layer and the nanostructure to a second position between the nanostructure and the source / drain structure.

[0010] In some embodiments, the inner spacer layer has a first surface facing away from the source / drain structure and a second surface facing the source / drain structure, and the blocking layer directly contacts the second surface. In some embodiments, the blocking layer directly contacts the first surface and the second surface.

[0011] In some embodiments, the semiconductor structure further includes: a gate structure located between two adjacent nanostructures; and an oxide layer located between the gate structure and the source / drain structure.

[0012] At least one embodiment of the present utility model has the following advantages or technical effects: a blocking layer is formed between the inner spacer layer and the S / D structure to act as a termination layer, which can reduce unwanted diffusion problems and prevent damage to the S / D structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The various aspects of the present disclosure will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practices in the industry, various components are not drawn to scale and are only used for illustration. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure.

[0014] Figures 1A to 1E is a perspective view showing a semiconductor structure at an intermediate manufacturing stage according to some embodiments.

[0015] Figures 2A to 2K is according to some embodiments, showing along Figure 1E a cross-sectional view of the semiconductor structure shown in A-A' in the middle manufacturing stage.

[0016] Figure 3 is according to some embodiments, showing Figure 2G an enlarged cross-sectional view of region A of the semiconductor structure shown.

[0017] Figure 4 is an enlarged cross-sectional view of region A of the semiconductor structure according to some embodiments.

[0018] Figure 5 is an enlarged cross-sectional view of region A of the semiconductor structure according to some embodiments.

[0019] Figure 6 According to some embodiments, an enlarged cross-sectional view of region A of a semiconductor structure is shown.

[0020] Figure 7 According to some embodiments, an enlarged cross-sectional view of region A of a semiconductor structure is shown.

[0021] Figure 8 According to some embodiments, an enlarged cross-sectional view of region A of a semiconductor structure is shown.

[0022] Figure 9 According to some embodiments, an enlarged cross-sectional view of region A of a semiconductor structure is shown.

[0023] Figure 10 According to some embodiments, an enlarged cross-sectional view of region A of a semiconductor structure is shown.

[0024] Wherein the reference numerals are explained as follows:

[0025] 100a / 100b / 100c / 100d / 100e / 100f / 100g / 100h: Semiconductor structure

[0026] 102: Substrate

[0027] 104: Fin structure

[0028] 104B: Base fin structure

[0029] 106: First semiconductor material layer

[0030] 108: Second semiconductor material layer

[0031] 108’: Nanostructure

[0032] 110: Mask structure

[0033] 112: Pad oxide layer

[0034] 114: Nitride layer

[0035] 116: Isolation structure

[0036] 118: dummy gate structure

[0037] 120: dummy gate dielectric layer

[0038] 122: dummy gate electrode layer

[0039] 124: hard mask layer

[0040] 126: gate spacer (layer)

[0041] 127: source / drain recess

[0042] 128: Fin spacer (layer)

[0043] 129: Notch

[0044] 130: Oxide layer

[0045] 132: Inner spacer layer

[0046] 133: Cavity

[0047] 134: Barrier layer

[0048] 136: Source / drain structure

[0049] 138: Contact etch stop layer

[0050] 139: Trench

[0051] 140: Interlayer dielectric layer

[0052] 141: Gap

[0053] 142: Gate structure

[0054] 144: Interface layer

[0055] 146: Gate dielectric layer

[0056] 148: Gate electrode layer

[0057] 150: Etch stop layer

[0058] 152: Dielectric layer

[0059] 154: Silicide layer

[0060] 156: Source / drain contact structure

[0061] 158: Liner

[0062] 160: Barrier layer

[0063] L1: Length

[0064] S1: First pitch

[0065] T1: First thickness. Detailed implementation mode

[0066] Numerous embodiments or examples are provided below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of the embodiments of the present disclosure. Of course, these are merely examples and are not intended to limit the embodiments of the present disclosure. For example, when it is described that a first element is formed on a second element, embodiments where the first and second elements are in direct contact may be included, and embodiments where additional elements are formed between the first and second elements so that they are not in direct contact may also be included. In addition, the embodiments of the present disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations being discussed.

[0067] The present disclosure describes various embodiments. In the respective schematic diagrams and exemplary embodiments, like reference numerals denote like elements. It should be understood that additional steps may be provided before, during, and / or after the method, and other embodiments of the method may replace or omit some of the steps.

[0068] The gate-all-around (GAA) transistor structure described below can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine lithography processes with self-alignment processes to create, for example, a pattern with a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the GAA structure.

[0069] The fins described below can be patterned by any suitable method. For example, one or more lithography processes (including double patterning or multiple patterning processes) can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine lithography processes with self-alignment processes to create, for example, a pattern with a smaller pitch than that obtained using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to pattern the fins.

[0070] Embodiments of a semiconductor structure and a method of forming the same are provided. A nanostructure is formed on a substrate, and a gate structure surrounds the nanostructure. A source / drain (S / D) structure is adjacent to the gate structure, and an inner spacer layer is located between the gate structure and the S / D structure. A barrier layer is formed between the inner spacer layer and the S / D structure to act as a termination layer. The barrier layer is used to prevent or reduce the diffusion of dopants in the S / D structure and to prevent damage to the S / D structure during the formation process of the nanostructure (or channel layer). In addition, the barrier layer can be part of the nanostructure (or channel layer). Due to the reduction of unwanted diffusion problems and damage to the S / D structure, the gate control of the semiconductor structure is improved. Therefore, the performance of the semiconductor structure can be enhanced. Depending on the context, the S / D structure or the S / D region can refer to the source or the drain individually or jointly.

[0071] Figures 1A to 1E According to some embodiments, a perspective view of a semiconductor structure 100a at an intermediate manufacturing stage is illustrated. As Figure 1A shown, a first semiconductor material layer 106 and a second semiconductor material layer 108 are formed over a substrate 102.

[0072] The substrate 102 can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the substrate 102 can include elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials can include, but are not limited to, crystalline silicon, polysilicon, amorphous silicon, germanium (Ge), and / or diamond (C). Compound semiconductor materials can include, but are not limited to, silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb). Alloy semiconductor materials can include, but are not limited to, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP).

[0073] In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are alternately stacked over the substrate 102. In some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layer 106 is made of silicon germanium (SiGe), and the second semiconductor material layer 108 is made of silicon. It should be noted that although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure may include a greater or lesser number of first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure may include two to five first semiconductor material layers 106 and second semiconductor material layers.

[0074] The first semiconductor material layer 106 and the second semiconductor material layer 108 may be formed by using low-pressure chemical vapor deposition (LPCVD), an epitaxial growth process, another suitable method, or a combination of the above. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor-phase epitaxy (VPE).

[0075] According to some embodiments, as Figure 1B shown, after the first semiconductor material layer 106 and the second semiconductor material layer 108 are formed into a semiconductor material stack over the substrate 102, the semiconductor material stack is patterned to form the fin structure 104. In some embodiments, the fin structure 104 includes a base fin structure 104B and a semiconductor material stack of the first semiconductor material layer 106 and the second semiconductor material layer 108.

[0076] In some embodiments, the patterning process includes forming a mask structure 110 over the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multi-layer structure. The multi-layer structure includes a pad oxide layer 112 and a nitride layer 114 formed over the pad oxide layer 112. The pad oxide layer 112 may be made of silicon oxide formed by thermal oxidation or chemical vapor deposition (CVD). The nitride layer 114 may be made of silicon nitride and formed by CVD, such as LPCVD or plasma-enhanced chemical vapor deposition (PECVD).

[0077] According to some embodiments, as Figure 1C shown, after forming the fin structure 104, an isolation structure 116 is formed around the fin structure 104, and the mask structure 110 is removed. According to some embodiments, the isolation structure 116 is configured to electrically isolate the active regions (e.g., the fin structure 104) of the semiconductor structure 100a, and is also referred to as a shallow trench isolation (STI) component.

[0078] The isolation structure 116 can be formed by depositing an insulating layer over the substrate 102 and recessing the insulating layer such that the fin structure 104 protrudes from the isolation structure 116. In some embodiments, the isolation structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination of the foregoing. In some embodiments, a dielectric liner (not shown) can be formed before forming the isolation structure 116, and the dielectric liner is made of silicon nitride, and the isolation structure formed over the dielectric liner is made of silicon oxide.

[0079] According to some embodiments, as Figure 1D shown, after forming the isolation structure 116, a dummy gate structure 118 is formed across the fin structure 104 and extends over the isolation structure 116. The dummy gate structure 118 can be used to define the source / drain regions and the channel region of the resulting semiconductor structure 100a.

[0080] In some embodiments, the dummy gate structure 118 includes a dummy gate dielectric layer 120 and a dummy gate electrode layer 122. In some embodiments, the dummy gate dielectric layer 120 is made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), hafnium dioxide (HfO2), hafnium zirconium oxide (HfZrO), hafnium silicon oxide (HfSiO), hafnium titanium oxide (HfTiO), hafnium aluminum oxide (HfAlO), or a combination of the foregoing. In some embodiments, the dummy gate dielectric layer 120 is formed using thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), another suitable method, or a combination of the foregoing.

[0081] In some embodiments, the dummy gate electrode layer 122 is made of a conductive material. In some embodiments, the conductive material includes polysilicon (poly-Si), polysilicon germanium (poly-SiGe), metal nitride, metal silicide, metal, or a combination of the foregoing. In some embodiments, the dummy gate electrode layer 122 is formed using CVD, PVD, or a combination of the foregoing.

[0082] In some embodiments, a hard mask layer 124 is formed over the dummy gate structure 118. In some embodiments, the hard mask layer 124 includes multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide, and the nitride layer is silicon nitride.

[0083] The formation of the dummy gate structure 118 may include conformally forming a dielectric material as the dummy gate dielectric layer 120. Thereafter, a conductive material may be formed over the dielectric material as the dummy gate electrode layer 122, and a hard mask layer 124 may be formed over the conductive material. Then, the dielectric material and the conductive material may be patterned through the hard mask layer 124 to form the dummy gate structure 118.

[0084] According to some embodiments, as Figure 1E shown, after the dummy gate structure 118 is formed, gate spacers 126 are formed along and covering opposite sidewalls of the dummy gate structure 118, and fin spacers 128 are formed along and covering opposite sidewalls of the source / drain regions of the fin structure 104.

[0085] The gate spacers 126 may be configured to separate the source / drain structures from the dummy gate structure 118 and support the dummy gate structure 118, and the fin spacers 128 may be configured to limit the lateral growth of the subsequently formed source / drain structures and support the fin structure 104.

[0086] In some embodiments, the gate spacers 126 and the fin spacers 128 are formed of a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), and / or combinations thereof. The formation of the gate spacers 126 and the fin spacers 128 may include: conformally depositing a dielectric material to cover the dummy gate structure 118, the fin structure 104, and the isolation structure 116 over the substrate 102, and performing an anisotropic etching process, such as dry plasma etching, to remove the dielectric layer covering the top surfaces of the dummy gate structure 118, the top surface of the fin structure 104, and the top surface of a portion of the isolation structure 116.

[0087] Figures 2A to 2K is according to some embodiments, showing a cross-sectional view of the semiconductor structure 100a at an intermediate manufacturing stage along Figure 1E the A-A' shown in

[0088] As Figure 2A shown, the gate spacer layer 126 is formed on both side surfaces of the dummy gate structure 118.

[0089] Next, according to some embodiments, as Figure 2BAs shown, after forming the gate spacer layer 126, the source / drain (S / D) regions of the fin structure 104 are recessed to form source / drain (S / D) recesses 127. Specifically, according to some embodiments, the first semiconductor material layer 106 and the second semiconductor material layer 108 that are not covered by the dummy gate structure 118 and the gate spacer layer 126 are removed.

[0090] In some embodiments, the fin structure 104 is recessed by performing an etching process. The etching process can be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 118 and the gate spacer layer 126 are used as an etching mask during the etching process.

[0091] After that, according to some embodiments, as Figure 2C shown, after forming the S / D recesses 127, the first semiconductor material layer 106 exposed by the S / D recesses 127 is laterally recessed to form notches 129.

[0092] In some embodiments, an etching process is performed on the semiconductor structure 100a to laterally recess the first semiconductor material layer 106 of the fin structure 104 from the S / D recesses 127. In some embodiments, during the etching process, the first semiconductor material layer 106 has a greater etching rate (or etching amount) than the second semiconductor material layer 108, thereby forming notches 129 between the adjacent second semiconductor material layers 108. In some embodiments, the etching process is an isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination of the foregoing.

[0093] Next, according to some embodiments, as Figure 2D shown, after the etching process, an oxide layer 130 is formed in the notches 129. The oxide layer 130 is a native oxide layer. After the etching process, the semiconductor structure 100a is exposed to the atmosphere (e.g., broken vacuum), and a native oxide layer 130 is formed in the notches 129. In some embodiments, the material of the first semiconductor material layer 106 is silicon germanium (SiGe), and the material of the oxide layer 130 is silicon germanium oxide (SiGeO x ).

[0094] Next, according to some embodiments, as Figure 2E shown, an inner spacer layer 132 is formed in the notches 129 between the second semiconductor material layers 108. In addition, the inner spacer layer 132 is formed on the oxide layer 130. The oxide layer 130 is located between the inner spacer layer 132 and the second semiconductor material layer 108.

[0095] According to some embodiments, the inner spacer layer 132 is configured to separate the source / drain structures formed in subsequent manufacturing processes from the gate structure.

[0096] In some embodiments, the inner spacer layer 132 is made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxicarbonitride (SiOCN), or a combination of the foregoing. In some embodiments, the inner spacer layer 132 is formed by a deposition process such as a CVD process, an ALD process, another suitable process, or a combination of the foregoing.

[0097] After that, according to some embodiments, as Figure 2F shown, an etching process is performed to remove a portion of the oxide layer 130 to form a cavity 133. After the etching process, an annealing process is performed. The annealing process is configured to remove unwanted products generated during the etching process. The cavity 133 is surrounded by the inner spacer layer 132 and the second semiconductor layer 108.

[0098] In some embodiments, the etching process is a dry etch. In some embodiments, the etching process is performed by using an etchant including hydrofluoric acid (HF), ammonia (NH3), hydrogen chloride (HCl), nitrogen trifluoride (NF3), hydrogen (H2), or a suitable material. In some embodiments, the annealing process is performed at a temperature in the range of about 90 degrees Celsius to about 200 degrees Celsius. When the temperature of the annealing process is within the above range, unwanted products can be effectively removed.

[0099] In some embodiments, a portion of the oxide layer 130 is removed to form a cavity. In some other embodiments, the entire oxide layer 130 is removed. The length of the cavity 133 in the horizontal direction is L1. In some embodiments, the length L1 of the cavity 133 is in the range of about 0.5 nanometers (nm) to about 7 nanometers.

[0100] Next, according to some embodiments, as Figure 2G shown, after the etching process, a barrier layer 134 is formed in the cavity 133, and after the formation of the barrier layer 134, a source / drain (S / D) structure 136 is formed in the S / D recess 127. The S / D structure 136 is formed on the barrier layer 134 and is in direct contact with the barrier layer 134.

[0101] The barrier layer 134 is configured to serve as a termination layer to prevent dopant diffusion of the S / D structure 136 into the nanostructure 108' (formed later, in Figure 2I to improve gate control. In addition, the barrier layer 134 with dopants can be in the nanostructure 108' (formed later, in Figure 2IReduce parasitic resistance and delay the etching rate during the formation of

[0102] In addition, the barrier layer 134 has a high etching selectivity with respect to the first semiconductor layer 106. Thus, when the first semiconductor layer 106 is removed by the etching process in Figure 2I (nanostructure 108' formation step), the barrier layer 134 is not removed. In some embodiments, the barrier layer 134 can be part of the nanostructure (or channel layer).

[0103] In some embodiments, the barrier layer 134 includes silicon (Si), silicon germanium (SiGe), doped silicon, doped silicon germanium, or another suitable material. In some embodiments, the barrier layer 134 is doped to form a doped barrier layer 134. The doped barrier layer 134 includes silicon doped with boron (B), silicon arsenide (SiAs), silicon phosphide (SiP), or other suitable materials. In some embodiments, the doping concentration of the dopant in the barrier layer 134 is in the range of about 1x10 20 centimeters -3 to about 5x10 21 centimeters -3 In some embodiments, the barrier layer 134 includes silicon (Si), and the S / D structure 136 includes silicon germanium (SiGe). In some embodiments, the barrier layer 134 includes silicon germanium (SiGe), the S / D structure 136 includes silicon germanium (SiGe), and the germanium concentration of the barrier layer 134 is less than the germanium concentration of the S / D structure 136. In some embodiments, the germanium concentration of the barrier layer 134 is in the range of about 1% to about 10%, and the germanium concentration of the S / D structure 136 is in the range of about 11% to about 70%.

[0104] In some embodiments, the barrier layer 134 does not contain germanium (Ge) atoms. In some embodiments, the barrier layer 134 does not contain oxygen (O) atoms. In some embodiments, the thickness of the barrier layer 134 is in the range of about 0.2 nanometers to about 3 nanometers.

[0105] In some embodiments, the barrier layer 134 is formed by a CVD process, a furnace process, an ALD process, or another suitable process. In some embodiments, the barrier layer 134 is formed in the cavity 133 and selectively formed on the epitaxial region. Thus, the barrier layer 134 is formed on the first semiconductor layer 106 and the second semiconductor layer 108.

[0106] In some embodiments, a barrier layer 134 is formed on the inner spacer layer 132, and an etching process is performed to remove a portion of the barrier layer 134 formed on the inner spacer layer 132. In this way, the barrier layer 134 can be "selectively" formed on certain regions. It should be noted that the inner spacer layer 132 is made of an amorphous material rather than an epitaxial material, so the adhesion between the barrier layer 134 and the inner spacer layer 132 is poor, and thus the portion of the barrier layer 134 formed on the inner spacer layer 132 can be easily removed by the etching process.

[0107] In some embodiments, the S / D structure 136 is made of any suitable material, such as germanium (Ge), silicon (Si), gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), silicon phosphide (SiP), silicon carbide (SiC), silicon carbide phosphide (SiCP), or a combination of the foregoing. In some embodiments, the S / D structure 136 is formed using an epitaxial growth process, such as molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), vapor phase epitaxy (VPE), another suitable epitaxial growth process, or a combination of the foregoing.

[0108] In some embodiments, the S / D structure 136 is in-situ doped during the epitaxial growth process. For example, the S / D structure 136 can be epitaxially grown silicon germanium (SiGe) doped with boron (B). For example, the S / D structure 136 can be epitaxially grown silicon (Si) doped with carbon to form a silicon:carbon (Si:C) source / drain component, epitaxially grown silicon (Si) doped with phosphorus to form a silicon:phosphorus (Si:P) source / drain component, or epitaxially grown silicon (Si) doped with both carbon and phosphorus to form a silicon carbon phosphorus (SiCP) source / drain component. In some embodiments, the S / D structure 136 is doped in one or more implantation processes after the epitaxial growth process.

[0109] Next, according to some embodiments, as Figure 2H shown, after the S / D structure 136 is formed, a contact etch stop layer (CESL) 138 is conformally formed to cover the S / D structure 136, and an interlayer dielectric (ILD) layer 140 is formed above the CESL 138.

[0110] In some embodiments, the CESL 138 is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination of the foregoing. The dielectric material for the CESL 138 can be conformally deposited over the semiconductor structure by CVD, ALD, another application method, or a combination of the foregoing.

[0111] The ILD layer 140 can include multiple layers made of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or another suitable low dielectric constant dielectric material. The ILD layer 140 can be formed by CVD, PVD, ALD, or other suitable processes.

[0112] According to some embodiments, as Figure 2H shown, after depositing the CESL 138 and the ILD layer 140, a planarization process (such as CMP or etch-back process) can be performed until the dummy gate electrode layer 122 of the dummy gate structure 118 is exposed.

[0113] Next, according to some embodiments, as Figure 2I shown, the dummy gate structure 118 is removed to form a trench 139, and the first semiconductor material layer 106 is removed to form a gap 141. In this way, a nanostructure 108' (or channel layer 108') having a second semiconductor material layer 108 is formed.

[0114] It should be noted that in some embodiments, while removing the first semiconductor layer 106, the Figure 2H shown oxide layer 130 is completely removed. In some embodiments, the first semiconductor layer 106 is made of silicon germanium (SiGe), the oxide layer 130 is made of silicon germanium oxide (SiGeO x )), and the oxide layer 130 and the first semiconductor layer 106 are removed simultaneously.

[0115] In some other embodiments, Figure 2H the shown oxide layer 130 in is not completely removed, and the remaining oxide layer 130 is formed between the gate structure 142 and the inner spacer layer 132.

[0116] The removal process may include one or more etching processes. For example, when the dummy gate electrode layer 122 is polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the dummy gate electrode layer 122. Subsequently, plasma dry etching, dry chemical etching, and / or wet etching can be used to remove the dummy gate dielectric layer 120. The first semiconductor material layer 106 can be removed by performing a selective wet etching process such as an ammonia hydroxide-hydrogen peroxide-water mixture (APM) etching process. For example, the wet etching process uses an etchant such as ammonium hydroxide (NH4OH), TMAH, ethylenediamine pyrocatechol (EDP), and / or potassium hydroxide (KOH) solution. In some embodiments, the upper portion of the gate spacer layer 126 is also removed.

[0117] After that, according to some embodiments, as Figure 2J shown, a gate structure 142 is formed in the trench 139 and the gap 141. Specifically, according to some embodiments, the dummy gate structure 118 and the first semiconductor material layer 106 are removed to form a nanostructure 108' having a second semiconductor material layer 108. The S / D structure 136 is attached to the nanostructure 108'.

[0118] After forming the nanostructure 108', a gate structure 142 surrounding the nanostructure 108' (or the channel layer 108') is formed. According to some embodiments, the gate structure 142 wraps around the nanostructure 108' to form a fully wrapped gate transistor structure. In some embodiments, the gate structure 142 includes an interface layer 144, a gate dielectric layer 146', and a gate electrode layer 148.

[0119] In some embodiments, the interface layer 144 is an oxide layer formed around the nanostructure 108' and on top of the base fin structure 104B. In some embodiments, the interface layer 144 is formed by performing a heat treatment.

[0120] In some embodiments, a gate dielectric layer 146 is formed over the interface layer 144 such that the nanostructure 108' is surrounded (e.g., wrapped) by the gate dielectric layer 146. Additionally, according to some embodiments, the gate dielectric layer 146 also covers the sidewalls of the gate spacer layer 126 and the inner spacer layer 132. In some embodiments, the gate dielectric layer 146 is made of one or more layers of dielectric materials, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), aluminum oxide (Al2O3), titanium oxide (TiO2), hafnium oxide - aluminum oxide alloy (HfO2 - Al2O3 alloy), other suitable high - dielectric - constant dielectric materials, or a combination of the foregoing. In some embodiments, the gate dielectric layer 146 is formed using CVD, ALD, another suitable method, or a combination of the foregoing.

[0121] In some embodiments, a gate electrode layer 148 is formed over the gate dielectric layer 146. In some embodiments, the gate electrode layer 148 is made of one or more layers of conductive materials, such as aluminum, copper, titanium, tantalum, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, another suitable material, or a combination of the foregoing. In some embodiments, the gate electrode layer 148 can be formed by CVD, ALD, electroplating, or another suitable method, or a combination of the foregoing. Other conductive layers (such as work - function metal layers) can also be formed in the gate structure 142, although they are not shown in the figures. In some embodiments, the n - type work - function layer includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination of the foregoing. In some embodiments, the p - type work - function layer includes titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), molybdenum nitride (MoN), tungsten nitride (WN), ruthenium (Ru), or a combination of the foregoing.

[0122] After forming the interface layer 144, the gate dielectric layer 146, and the gate electrode layer 148, a planarization process (such as CMP or etch - back process) can be performed until the ILD layer 140 is exposed.

[0123] Then, according to some embodiments, as Figure 2KAs shown, an etch stop layer 150 is formed over the gate structure 142, and a dielectric layer 152 is formed over the etch stop layer 150. Then, an S / D contact structure 156 is formed over the S / D structure 136.

[0124] In some embodiments, the contact opening may be formed through the contact etch stop layer 138, the interlayer dielectric layer 140, the etch stop layer 150, and the dielectric layer 152 to expose the top surface of the S / D structure 136, and the silicide layer 154 and the S / D contact structure 156 may be formed in the contact opening. The contact opening may be formed using a lithography process and an etching process. Additionally, some portions of the S / D structure 136 exposed by the contact opening may also be etched during the etching process.

[0125] After forming the contact opening, the silicide layer 154 may be formed by forming a metal layer over the top surface of the S / D structure 136 and annealing the metal layer to react the metal layer with the S / D structure 136. The unreacted metal layer may be removed after forming the silicide layer 154.

[0126] Then, a liner layer 158, a barrier layer 160, and the S / D contact structure 156 are formed over the silicide layer 154 in the contact opening, and a polishing process is performed. According to some embodiments, as Figure 2K shown, the top surface of the S / D contact structure 156 is substantially flush with the top surface of the dielectric layer 152.

[0127] In some embodiments, the etch stop layer 150 is made of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination of the foregoing. The dielectric material for the etch stop layer 150 may be conformally deposited over the semiconductor structure by performing CVD, ALD, another applicable method, or a combination of the foregoing.

[0128] In some embodiments, the dielectric layer 152 may include multiple layers made of various dielectric materials such as silicon oxide, silicon nitride, silicon oxynitride, phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), or another suitable low dielectric constant dielectric material. The dielectric layer 152 may be formed by CVD, PVD, ALD, or other applicable processes.

[0129] In some embodiments, the S / D contact structure 156 is made of a conductive material, the conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt (Co), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide (Cu5Si), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbonitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), another suitable conductive material, or a combination of the foregoing. In some embodiments, the liner layer 158 is made of silicon nitride, but any other suitable dielectric may be used as an alternative.

[0130] In some embodiments, the barrier layer 160 is made of tantalum nitride, but other materials such as tantalum, titanium, titanium nitride, etc. may also be used. The liner layer 158, the barrier layer 160, and the S / D contact structure 156 may be formed using deposition processes such as CVD, PVD, plasma-enhanced chemical vapor deposition (PECVD), plasma enhanced physical vapor deposition (PEPVD), ALD, or another suitable deposition process.

[0131] In some embodiments, the top surface of the S / D contact structure 156 is higher than the top surface of the gate structure 142, and the top surface of the S / D contact structure 156 is substantially flush with the dielectric layer 152. In some embodiments, the height difference between the S / D contact structure 156 and the gate structure 142 is substantially flush with the height of the dielectric layer 152.

[0132] If an oxide layer 130 (such as SiGeO x ) is formed in the cavity 133 between the inner spacer layer 132 and the S / D structure 136, the dopants of the S / D structure 136 will diffuse into the nanostructure 108' (or channel layer), and the gate control of the semiconductor structure 100a will deteriorate. Additionally, if oxygen (O) atoms of the oxide layer 130 (such as SiGeO x ) diffuse into the nanostructure 108' (or channel layer), the mobility of the nanostructure 108' (or channel layer) will be reduced. To prevent unwanted diffusion problems, the cavity 133 is filled with a barrier layer 134, and the barrier layer 134 acts as a termination layer to prevent the dopants of the S / D structure 136 from diffusing into the nanostructure 108' (or channel layer).

[0133] Furthermore, if an oxide layer 130 (such as SiGeO x) Then, during the formation process of the nanostructure 108' (as Figure 2I shown), as the first semiconductor layer 106 is removed, the oxide layer 130 is easily removed. The removal of the oxide layer 130 will cause defects, and the etchant of the etching process used to remove the first semiconductor layer 106 will damage the S / D structure 136 through the defects. To reduce or prevent the damage of the S / D structure 136, the oxide layer 130 is replaced with a barrier layer 134. The barrier layer 134 has a high etching selectivity with respect to the first semiconductor layer 106, and the barrier layer 134 will not be removed during the formation process of the nanostructure 108' (as Figure 2I shown).

[0134] By forming the barrier layer 134 between the inner spacer layer 132 and the S / D structure 136, the diffusion problem of the dopants in the S / D structure 136 can be reduced, thereby improving the gate control. In addition, since the barrier layer 134 has a high etching selectivity with respect to the first semiconductor layer 106 after the formation process of the nanostructure 108' (as Figure 2I shown), the S / D structure 136 will not be damaged. Therefore, the performance of the semiconductor structure 100a is improved.

[0135] In some embodiments, one of the nanostructures 108' has a first thickness Tl in the vertical direction. In some embodiments, the first thickness T1 ranges from about 3 nanometers to about 8 nanometers. In some embodiments, the first spacing S1 between two adjacent nanostructures 108' ranges from about 3 nanometers to about 12 nanometers.

[0136] Figure 3 is an enlarged cross-sectional view of region A of the semiconductor structure 100a shown in accordance with some embodiments as Figure 2G shown.

[0137] As Figure 3 shown, the barrier layer 134 is located between the inner spacer layer 132 and the nanostructure 108'. In addition, the barrier layer 134 is in direct contact with the nanostructure 108' and the S / D structure 136. Furthermore, the sidewall surface of the barrier layer 134 is aligned with the sidewall surface of the inner spacer layer 132. The barrier layer 134 is located directly below the gate spacer layer 126.

[0138] Figure 4 is an enlarged cross-sectional view of region A of the semiconductor structure 100b shown in accordance with some embodiments. Figure 4 The semiconductor structure 100b includes elements similar to or the same as those of the Figure 2J semiconductor structure 100a. Figure 4 is similar to Figure 2JThe difference is that the remaining oxide layer 130 is formed between the gate structure 142 and the inner spacer layer 132. More specifically, during the removal of the first semiconductor layer 106, the oxide layer 130 is not completely removed. The remaining oxide layer 130 is in direct contact with the interface layer 144 of the gate structure 142 and the gate dielectric layer 146. In Figure 2I After the nanostructures 108' are formed in Figure 2H The thickness of the remaining oxide layer 130 is less than the thickness of the oxide layer 130 in

[0139] Figure 5 FIG. is a magnified cross-sectional view of region A of the semiconductor structure 100c according to some embodiments. Figure 5 The semiconductor structure 100c of Figure 5 includes elements similar to or the same as those of the semiconductor structure 100a of Figure 2J The difference from

[0140] is that a barrier layer 134 is formed on the outer sidewall surface of the nanostructures 108'. The barrier layer 134 is in direct contact with the sidewall surface of the nanostructures 108' facing the S / D structure 136. More specifically, the barrier layer 134 extends from a first position to a second position, and the first position is between the inner spacer layer 132 and the nanostructures 108', while the second position is between the nanostructures 108' and the S / D structure 136. The barrier layer 134 may have a plurality of separated portions separated by the inner spacer layer 132.

[0141] Figure 6 FIG. is a magnified cross-sectional view of region A of the semiconductor structure 100d according to some embodiments. Figure 6 The semiconductor structure 100d of Figure 5 includes elements similar to or the same as those of the semiconductor structure 100c of Figure 6 The difference from Figure 5 is that the remaining oxide layer 130 is formed between the gate structure 142 and the inner spacer layer 132. The remaining oxide layer 130 is in direct contact with the interface layer 144 of the gate structure 142 and the gate dielectric layer 146.

[0142] Figure 7 FIG. is a magnified cross-sectional view of region A of the semiconductor structure 100e according to some embodiments. Figure 7 The semiconductor structure 100e of Figure 2J includes elements similar to or the same as those of the semiconductor structure 100a of Figure 7 The difference from Figure 2J is that the barrier layer 134 is formed on the outer sidewall surface of the nanostructures 108' and on the outer sidewall surface of the inner spacer layer 132.

[0143] The inner spacer layer 132 has a first surface facing the gate structure 142 and a second surface facing the S / D structure 136. The barrier layer 134 is in direct contact with the second surface of the inner spacer layer 132. In other words, the barrier layer 134 is located between the inner spacer layer 132 and the S / D structure 136. The barrier layer 134 is a continuous layer extending in the vertical direction.

[0144] Figure 8 According to some embodiments, an enlarged cross-sectional view of region A of the semiconductor structure 100f is shown. Figure 8 The semiconductor structure 100f includes elements similar to or the same as those of Figure 7 the semiconductor structure 100e. Figure 8 The difference from Figure 7 is that a remaining oxide layer 130 is formed between the gate structure 142 and the inner spacer layer 132. The remaining oxide layer 130 is in direct contact with the interface layer 144 and the gate dielectric layer 146 of the gate structure 142.

[0145] Figure 9 According to some embodiments, an enlarged cross-sectional view of region A of the semiconductor structure 100g is shown. Figure 9 The semiconductor structure 100g includes elements similar to or the same as those of Figure 2J the semiconductor structure 100a. Figure 9 The difference from Figure 2J is that the top surface, bottom surface, and sidewall surfaces of the inner spacer layer 132 are surrounded by the barrier layer 134. The inner spacer layer 132 has a first surface facing the gate structure 142 and a second surface facing the S / D structure 136. The barrier layer 134 is in direct contact with the first surface and the second surface of the inner spacer layer 132. In other words, the inner spacer layer 132 has a curved surface protruding toward the gate structure 142, and the barrier layer 134 is formed on the curved surface of the inner spacer layer 132.

[0146] Figure 10 According to some embodiments, an enlarged cross-sectional view of region A of the semiconductor structure 100h is shown. Figure 10 The semiconductor structure 100h includes elements similar to or the same as those of Figure 9 the semiconductor structure 100g. Figure 10 The difference from Figure 9 is that a remaining oxide layer 130 is formed between the gate structure 142 and the inner spacer layer 132. The remaining oxide layer 130 is in direct contact with the interface layer 144 and the gate dielectric layer 146 of the gate structure 142.

[0147] The blocking layer 134 plays many roles. The blocking layer 134 can be a termination layer to prevent or reduce the diffusion of dopants in the S / D structure 136 and protect the S / D structure 136 from being damaged. The blocking layer 134 can be part of a nanostructure (or channel layer).

[0148] In some embodiments, the blocking layer 134 is formed between the inner spacer layer 132 and the nanostructure 108'. In some embodiments, the blocking layer 134 is formed between the inner spacer layer 132 and the S / D structure 136.

[0149] The blocking layer 134 is in direct contact with the sidewall surface of the nanostructure 108' facing the S / D structure 136. More specifically, the blocking layer 134 extends from a first position between the inner spacer layer 132 and the nanostructure 108' to a second position between the nanostructure 108' and the S / D structure 136. The blocking layer 134 can have Figure 5 and Figure 6 multiple separated portions as shown, and the separated portions are separated by the inner spacer layer 132.

[0150] The inner spacer layer 132 has a first surface facing the gate structure 142 and a second surface facing the S / D structure 136. The blocking layer 134 is in direct contact with the second surface of the inner spacer layer 132. In other words, the blocking layer 134 is located between the inner spacer layer 132 and the S / D structure 136. As Figure 7 and Figure 8 shown, the blocking layer 134 is a continuous layer extending in the vertical direction.

[0151] It should be noted that, in some embodiments, while removing the first semiconductor layer 106, the oxide layer 130 as Figure 2H shown is completely removed. In some embodiments, the first semiconductor layer 106 is made of silicon germanium (SiGe), the oxide layer 130 is made of silicon germanium oxide (SiGeO x )), and the oxide layer 130 is removed simultaneously with the first semiconductor layer 106. In some other embodiments, Figure 2H the oxide layer 130 as shown is not completely removed, and the remaining oxide layer 130 is formed between the gate structure 142 and the inner spacer layer 132.

[0152] It should be noted that Figures 1A to 10 the same elements in Figures 1A to 10 can be represented by the same element symbols, and can include similar or the same materials and can be formed by similar or the same processes; therefore, for the sake of brevity, these redundant details are omitted. Additionally, although Figures 1A to 10The structures disclosed herein are not limited to the method, but can exist independently as a structure separate from the method. Similarly, although Figures 1A to 10 the method shown is not limited to the disclosed structures, but can exist independently of these structures. In addition, according to some embodiments, the above nanostructures can include nanowires, nanosheets, and other applicable nanostructures.

[0153] In addition, although the disclosed method is illustrated and described below as a series of actions or events, it should be understood that in some other embodiments, the illustrated order of such actions or events can be changed. For example, some actions can occur in a different order or simultaneously with other actions or events other than those shown and / or described above. In addition, not all of the shown actions may be required to implement one or more aspects or embodiments described above. In addition, one or more of the above actions can be performed in one or more separate actions and / or stages.

[0154] In addition, the terms "substantially", "essentially", "substantial", and "about" used above explain small variations and can vary in different technologies and can be within the deviation range understood by those skilled in the art. For example, when used in combination with an event or situation, these terms can refer to the situation where the event or situation occurs exactly and the situation where the event or situation occurs very close to it.

[0155] An embodiment for forming a semiconductor structure is provided. A nanostructure is formed on a substrate, and a gate structure surrounds the nanostructure. The S / D structure is adjacent to the gate structure, and an inner spacer layer is located between the gate structure and the S / D structure. A native oxide layer is formed before forming the inner spacer layer, and a part of the native oxide layer is removed to form a cavity. Then, a barrier layer is formed in the cavity to serve as a termination layer. The barrier layer is used to prevent or reduce the diffusion of dopants in the S / D structure and prevent damage to the S / D structure. In addition, the barrier layer can be part of the nanostructure (or channel layer). Since the unwanted diffusion problem and the damage to the S / D structure are reduced, the gate control of the semiconductor structure is improved. Therefore, the performance of the semiconductor structure can be improved.

[0156] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures formed above a substrate and a gate structure formed on the nanostructures. The semiconductor structure includes a source / drain structure formed adjacent to the gate structure and an inner spacer layer located between the gate structure and the source / drain structure. The semiconductor structure includes a barrier layer adjacent to the inner spacer layer, and the barrier layer is located between the inner spacer layer and the nanostructures.

[0157] In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate and an inner spacer layer located between two adjacent nanostructures. The semiconductor structure includes a source / drain structure formed adjacent to the inner spacer layer and a barrier layer adjacent to the inner spacer layer. The barrier layer extends from a first position between the inner spacer layer and the nanostructure to a second position between the nanostructure and the source / drain structure.

[0158] In some embodiments, a method of forming a semiconductor structure is provided. The method includes forming a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, with the first semiconductor layers and the second semiconductor layers stacked alternately. The method further includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layer and a portion of the second semiconductor layer to form a recess. The method includes removing another portion of the second semiconductor layer to form a notch between two adjacent first semiconductor layers, and forming an oxide layer after forming the notch. The method includes forming an inner spacer layer in the notch and removing a portion of the oxide layer to form a cavity. The method includes forming a barrier layer in the cavity, and the barrier layer is located between the inner spacer layer and the first semiconductor layer.

[0159] The foregoing outlines components of several embodiments so that those skilled in the art of the present disclosure can more readily understand the perspective of the embodiments of the present disclosure. Those skilled in the art of the present disclosure should understand that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art of the present disclosure should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: Multiple nanostructures formed above a substrate; A gate structure formed on the multiple nanostructures; A source / drain structure formed adjacent to the gate structure; An inner spacer layer located between the gate structure and the source / drain structure; And A barrier layer adjacent to the inner spacer layer, wherein the barrier layer is located between the inner spacer layer and the multiple nanostructures.

2. The semiconductor structure according to claim 1, wherein, Wherein the barrier layer directly contacts the multiple nanostructures and the source / drain structure.

3. The semiconductor structure according to claim 1 or 2, characterized in that, Wherein the barrier layer is formed on an outer sidewall surface of the multiple nanostructures.

4. The semiconductor structure according to claim 1, characterized in that, Wherein the barrier layer is located between the inner spacer layer and the source / drain structure.

5. The semiconductor structure according to claim 1, wherein Wherein the inner spacer layer has a curved surface protruding towards the gate structure, and the barrier layer is formed on the curved surface of the inner spacer layer.

6. The semiconductor structure according to claim 1, wherein Wherein a sidewall surface of the barrier layer is aligned with a sidewall surface of the inner spacer layer.

7. A semiconductor structure, characterized in that, Comprising: Multiple nanostructures formed above a substrate; An inner spacer layer located between two adjacent ones of the nanostructures; A source / drain structure formed adjacent to the inner spacer layer; And A barrier layer adjacent to the inner spacer layer, wherein the barrier layer extends from a first position to a second position, the first position being between the inner spacer layer and the multiple nanostructures, and the second position being between the multiple nanostructures and the source / drain structure.

8. The semiconductor structure according to claim 7, wherein, Wherein the inner spacer layer has a first surface facing away from the source / drain structure and a second surface facing the source / drain structure, and the barrier layer directly contacts the second surface.

9. The semiconductor structure according to claim 8, wherein, Wherein the barrier layer directly contacts the first surface and the second surface.

10. The semiconductor structure according to claim 7, wherein, Further comprising: A gate structure located between two adjacent ones of the nanostructures; And An oxide layer located between the gate structure and the source / drain structure.

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