Optoelectronic device and semiconductor device

Abstract

Some implementations described herein provide an optoelectronic device and a semiconductor device including a multi-layer photodiode structure having a plurality of sensing structures formed from one or more quantum effect structures (e.g., formed from multiple layers of quantum effect structures). A plurality of sensing structures including sidewalls in contact with a substrate of an optoelectronic device may be stacked and include overlapping portions. Via the use of a multi-layer photodiode structure comprising a plurality of sensing structures, quantum length is increased relative to another photodiode structure comprising a single planar sensing structure formed from one layer of a quantum effect structure.

Description

Technical Field

[0001] Some embodiments of the present disclosure provide optoelectronic devices and semiconductor devices. Background Art

[0002] Complementary metal oxide semiconductor (CMOS) image sensor (CIS) devices utilize photosensitive CMOS circuitry to convert light energy into electrical energy. The photosensitive CMOS circuitry may include a photodiode structure formed in a silicon substrate. When the photodiode structure is exposed to light, charges (referred to as photocurrent) are induced in the photodiode structure. The photodiode structure may be coupled to a switching transistor that samples the charges of the photodiode structure. Color may be determined by placing a filter over the photosensitive CMOS circuitry. Summary of the Utility Model

[0003] Some embodiments of the present disclosure provide an optoelectronic device, comprising: a substrate and a multi-layer photodiode structure. The multi-layer photodiode structure includes: a first sensing structure, a second sensing structure, an oxide structure, and a dielectric structure. The first sensing structure extends into the substrate, includes a first quantum effect structure, and has a plurality of sidewalls in direct contact with the substrate. The second sensing structure is above the first sensing structure and includes a second quantum effect structure. The oxide structure is below the second sensing structure and above the first sensing structure. The dielectric structure is above the oxide structure and below the second sensing structure.

[0004] Some embodiments of the present disclosure provide a semiconductor device, comprising: a first semiconductor die and a second semiconductor die. The first semiconductor die includes: a first substrate and a pixel sensor. The pixel sensor includes: a multi-layer photodiode structure and a second quantum effect structure. The multi-layer photodiode structure includes: a first sensing structure and a second sensing structure. The first sensing structure extends into the first substrate, includes a first quantum effect structure, and has a plurality of sidewalls in direct contact with the first substrate. The second sensing structure is above the first sensing structure and includes a second quantum effect structure. The second semiconductor die is bonded to the first semiconductor die below the first semiconductor die and includes: a second substrate and a logic integrated circuit system. The logic integrated circuit system is on or within the second substrate.

[0005] Some embodiments of the present disclosure provide an optoelectronic device. The optoelectronic device includes a substrate, a multilayer photodiode structure, and an electromagnetic wave transmission region. The multilayer photodiode structure includes a first sensing structure, a second sensing structure, and an oxide structure. The first sensing structure extends into the substrate, includes a first quantum effect structure, and has a plurality of sidewalls in direct contact with the substrate. The second sensing structure is above the first sensing structure and includes a second quantum effect structure. The oxide structure is below the second sensing structure and above the first sensing structure. The electromagnetic wave transmission region is vertically configured, includes the first sensing structure, and has the same width as the first sensing structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Some aspects of the present disclosure are described in the accompanying Figure 1 The following detailed description is best understood when read together. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a schematic diagram of an example environment in which the systems and / or methods described herein may be implemented;

[0008] Figure 2 is a schematic diagram of an example semiconductor structure described herein;

[0009] Figure 3 is a schematic diagram of an example semiconductor die package described herein;

[0010] Figures 4A to 4D is a schematic diagram of an example implementation of a multilayer photodiode structure described herein;

[0011] Figures 5A to 5L A schematic diagram of an example implementation described herein;

[0012] Figure 6 For the purposes of this article Figure 1 A schematic diagram of example components of one or more devices in;

[0013] Figure 7 is a flow chart of an example process associated with forming the multilayer photodiode structure described herein.

[0014]

Explanation of symbols

[0015] 100: Environment

[0016] 102:Deposition tools / processing tools

[0017] 104:Exposure Tools / Processing Tools

[0018] 106: Development tools / processing tools

[0019] 108: Etching tool / Processing tool

[0020] 110: Planarization tool / Processing tool

[0021] 112: Electroplating tool / Processing tool

[0022] 114: Ion implantation tool / Processing tool

[0023] 116: Bonding / Stripping tool / Processing tool

[0024] 118: Wafer / die transfer tool

[0025] 200: Pixel array

[0026] 202: Pixel sensor

[0027] 202a, 202b, 202c, 202d: Pixel sensor

[0028] 300: Optoelectronic device

[0029] 302a, 302b: Semiconductor device

[0030] 304: Bonding interface

[0031] 306a, 306b: Contact

[0032] 308a, 308b: Dielectric region

[0033] 310a, 310b: Metallization layer

[0034] 312a, 312b: Substrate

[0035] 314: Multilayer photodiode structure

[0036] 314a, 314b, 314c, 314d: Multilayer photodiode structure

[0037] 316a, 316b, 316c: Sensing structure

[0038] 318a, 318b: Electromagnetic wave

[0039] 320: Bonding pad

[0040] 322: Dielectric layer

[0041] 324: Microlens layer

[0042] 326: Logic integrated circuit system

[0043] 400: Example implementation

[0044] 402: Electromagnetic wave transmission region

[0045] 404: Oxide structure

[0046] 406a, 406b: Dielectric structure

[0047] 408a, 408b: Bottom protrusions

[0048] 410: Epitaxial structure

[0049] 500: Implementation

[0050] 502, 508, 512: Cavities

[0051] 504, 510: Recessed areas

[0052] 506: Boundary

[0053] 600: Device

[0054] 610: Bus

[0055] 620: Processor

[0056] 630: Memory

[0057] 640: Input component

[0058] 650: Output component

[0059] 660: Communication component

[0060] 700: Process

[0061] 710, 720, 730, 740, 750, 760, 770: Blocks

[0062] D1, D2, D6: Thickness

[0063] D3, D4: Width

[0064] D5: Depth Detailed implementation manners

[0065] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0066] In addition, for ease of description, spatial relative terms, such as "below", "beneath", "lower", "above", "upper", and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another (one or more) element or feature. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0067] In some cases of optoelectronic devices, a photodiode structure includes a layer of a quantum structure such as germanium. Photons of light from the layer that enters the quantum structure may be absorbed and generate electron-hole pairs, which are separated by an electric field at a p-n junction, thereby generating a current (e.g., a photocurrent) that can be detected by an external circuit.

[0068] The thickness or length of the layer of the quantum structure, sometimes referred to as the "quantum length", affects the performance of the photodiode structure. For example, if the quantum length of the layer of the quantum structure is too short (e.g., the layer of the quantum structure is too thin), photons of light from the layer that enters the quantum structure may pass through the layer of the quantum structure without being absorbed, thereby reducing the sensitivity and / or energy conversion efficiency of the photodiode structure.

[0069] Some embodiments described herein provide an optoelectronic device that includes a multi-layer photodiode structure having a plurality of sensing structures formed by one or more quantum effect structures (e.g., formed by multiple layers of quantum effect structures). The plurality of sensing structures including a lower sensing structure (having sidewalls in contact with the substrate of the optoelectronic device) may be stacked and include overlapping portions. By using the multi-layer photodiode structure including the plurality of sensing structures, the quantum length is increased relative to another photodiode structure including a single planar sensing structure formed by a layer of a quantum effect structure.

[0070] In this way, the performance of the optoelectronic device including the multi-layer photodiode structure is improved relative to another optoelectronic device including a single planar sensing structure. By improving the performance of the optoelectronic device, the quality and reliability of the optoelectronic device for target applications and / or environments can be improved, thereby increasing the manufacturing yield and reducing the on-site failure rate. Increasing the manufacturing yield and reducing the on-site failure rate can reduce the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to support the market for consumer optoelectronic devices.

[0071] Figure 1 Schematic diagram of an example environment 100 for implementing the systems and / or methods described herein. As Figure 1As shown, environment 100 may include a plurality of semiconductor processing tools 102-116 and a wafer / die transfer tool 118. The plurality of semiconductor processing tools 102-116 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, an electroplating tool 112, an ion implantation tool 114, a bonding / stripping tool 116, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in semiconductor cleaning chambers, semiconductor fabs, semiconductor processing facilities, and / or manufacturing facilities and other examples.

[0072] The deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials on a substrate. In some implementations, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a low pressure CVD (LPCVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition tool (PEALD), or another type of CVD tool. In some implementations, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the example environment 100 includes multiple types of deposition tools 102.

[0073] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns for forming one or more semiconductor devices, can include a pattern for forming one or more structures in a semiconductor device, can include a pattern for etching respective portions in a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or an exposure tool of a similar type.

[0074] The development tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source, thereby developing the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the development tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the development tool 106 develops the pattern by dissolving the exposed or unexposed portions of the photoresist layer using a chemical developer.

[0075] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, a wafer, or a semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 can use plasma etching or plasma-assisted etching to etch one or more portions of the substrate, which can involve using an ionized gas to etch the one or more portions isotropically or directionally.

[0076] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool for grinding or planarizing a layer or surface of a deposited or electroplated material. The planarization tool 110 may utilize a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive grinding) to grind or planarize the surface of the semiconductor device. The planarization tool 110 may incorporate a polishing pad and a retainer ring (e.g., typically having a diameter larger than that of the semiconductor device) to utilize an abrasive and corrosive chemical slurry. The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retainer ring. The dynamic polishing head may rotate about different axes of rotation to remove material and homogenize any irregular topography of the semiconductor device, thereby making the semiconductor device flat or planar.

[0077] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion thereof using one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a composite material or alloy (e.g., tin - silver, tin - lead, and / or the like) electroplating device, and / or an electroplating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0078] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 may generate ions from a source material such as a gas or a solid in an arc chamber. The source material may be provided into the arc chamber, and an arc voltage may be released between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes may be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam may be directed towards the substrate such that the ions are implanted beneath the surface of the substrate.

[0079] The bonding / stripping tool 116 is a semiconductor processing tool capable of bonding together two or more wafers (or two or more semiconductor substrates, or two or more semiconductor devices). For example, the bonding / stripping tool 116 may include an eutectic bonding tool capable of forming an eutectic bond between two or more wafers. In these examples, the bonding / stripping tool 116 may heat two or more wafers to form an eutectic system between the materials of the two or more wafers. As another example, the bonding / stripping tool 116 may include a hybrid bonding tool, a direct bonding tool, and / or another type of bonding tool. In some implementations, the bonding / stripping tool 116 may heat two or more wafers to separate the two or more wafers.

[0080] The wafer / die transfer tool 118 may be included in a cluster tool or another type of tool including multiple processing chambers and may be used to transfer substrates and / or semiconductor devices between multiple processing chambers, transfer substrates and / or semiconductor devices between a processing chamber and a buffer, transfer substrates and / or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and / or transfer substrates or semiconductor devices between a processing chamber and a transfer carrier (e.g., a front opening unified pod (FOUP)), and other examples. In some implementations, the wafer / die transfer tool 118 may be included in the multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning processing chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or by-products from the substrate and / or semiconductor device) and multiple types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations).

[0081] One or more of the semiconductor processing tools 102-116 and / or the wafer / die transfer tool 118 may perform one or more of the series of semiconductor processing operations described herein. In some implementations, and by way of example, one or more of the series of semiconductor processing operations include forming an oxide structure over a substrate. One or more of the series of semiconductor processing operations include forming a first cavity through the oxide structure and into the substrate. One or more of the series of semiconductor processing operations include forming a first sensing structure in the first cavity, wherein forming the first sensing structure includes forming sidewalls that are in direct contact with the surface of the first cavity. One or more of the series of semiconductor processing operations include forming a dielectric structure over the first sensing structure. One or more of the series of semiconductor processing operations include forming a recessed region within the dielectric structure. One or more of the series of semiconductor processing operations include forming a second cavity that passes through the dielectric structure within the recessed region and through the oxide structure to the substrate. One or more of the series of semiconductor processing operations include forming a second sensing structure, the second sensing structure being over the recessed region and including a bottom protrusion that fills the second cavity to connect with the substrate, wherein forming the second sensing structure includes forming the second sensing structure over the first sensing structure. In some implementations, one or more of the semiconductor processing operations performed by the processing tools 102-116 and / or the wafer / die transfer tool 118 may correspond to one or more semiconductor processing operations in combination with Figures 5A to 5L and one or more semiconductor processing operations described elsewhere herein, and other examples.

[0082] Figure 1 The number and configuration of the devices shown in Figure 1 are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or devices with different configurations compared to those shown in Figure 1 Two or more of the devices shown in Figure 1 may be implemented within a single device, or Figure 1 the single device shown in Figure 1 may be implemented as multiple distributed devices. Additionally or alternatively, a set of devices (e.g., one or more devices) of the example environment 100 may perform one or more functions described as being performed by another set of devices of the example environment 100.

[0083] Figure 2 shows a top-down view of the pixel array 200. As Figure 2 shown, the pixel array 200 may include a plurality of pixel sensors 202. As Figure 2 further shown, the pixel sensors 202 may be in a grid configuration. In some implementations, the pixel sensors 202 are square-shaped (as shown in the example of Figure 2 ). In some implementations, the pixel sensors 202 include other shapes, such as circular shapes, octagonal shapes, rhombus shapes, and / or other shapes.

[0084] The pixel sensor 202 can be used to sense and / or accumulate incident light (e.g., light directed towards the pixel array 200). For example, the pixel sensor 202 can absorb and accumulate photons of the incident light in a photodiode structure. The accumulation of photons in the photodiode structure can generate charges representing the intensity or brightness of the incident light (e.g., a larger amount of charge can correspond to a greater intensity or brightness, and a lower amount of charge can correspond to a lower intensity or brightness).

[0085] The pixel array 200 can be electrically connected to a back-end-of-line (BEOL) metallization stack (not shown) of the image sensor. The BEOL metallization stack can electrically connect the pixel array 200 to a control circuitry system that can be used to measure the accumulation of incident light in the pixel sensor 202 and convert the measurement result into an electrical signal.

[0086] As described more fully in connection with Figures 3 to 7 and elsewhere herein, the pixel sensor 202 can include a combination of optical wave filters (e.g., optical wave filters that filter light of a target wavelength). For example, using an optical wave filter, the pixel sensor 202a can include a multi-layer photodiode structure that senses red visible (VIS) light waves (e.g., electromagnetic waves having wavelengths included in the range of about 620 nanometers to about 750 nanometers). Additionally or alternatively, the pixel sensor 202b can include a multi-layer photodiode structure that senses blue VIS light waves (e.g., electromagnetic waves having wavelengths included in the range of about 450 nanometers to about 495 nanometers). Additionally or alternatively, the pixel sensor 202c can include a multi-layer photodiode structure that senses green VIS light waves (e.g., electromagnetic waves having wavelengths included in the range of about 495 nanometers to about 570 nanometers). Additionally or alternatively, the pixel sensor 202d can include a multi-layer photodiode structure that senses NIR light waves (e.g., electromagnetic waves having wavelengths included in the range of about 750 nanometers to about 2500 nanometers).

[0087] As described above, Figure 2 is provided as an example. Other examples may differ from those regarding Figure 2 described.

[0088] Figure 3 is a schematic diagram of an example optoelectronic device 300 described herein. In some implementations, the optoelectronic device 300 corresponds to a three dimensional complementary metal oxide semiconductor image sensor (3D CIS) device, where the semiconductor devices 302a and 302b are stacked and / or vertically configured. As Figure 3As shown, semiconductor device 302a (e.g., a photonic semiconductor die) is bonded to semiconductor device 302b (e.g., a complementary metal oxide semiconductor (CMOS) die) through bonding interface 304. Bonding interface 304 may include contacts 306a and 306b bonded via eutectic bonding. Contacts 306a and 306b may include alloys such as aluminum-copper alloy (Al-Cu), aluminum-germanium alloy (Al-Ge), or copper-tin alloy (Cu-Sn) structures, among other examples.

[0089] As Figure 3 Further shown, semiconductor device 302a may include dielectric region 308a. Dielectric region 308a (e.g., an intermetal dielectric region) may include one or more layers of dielectric structures (e.g., iron oxide (Fe x O y ), zinc oxide (ZnO), silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, or another dielectric structure). One or more metallization layers 310a may be formed in and / or between dielectric region 308a. Metallization layer 310a may include bonding pads, conductive lines, and / or other types of conductive structures to electrically connect various regions in semiconductor device 302a and / or various regions in optoelectronic device 300 to one or more external devices and / or external packages. In some embodiments, metallization layer 310a may be referred to as a BEOL metallization stack and may include conductive structures such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof, among other examples.

[0090] Semiconductor device 302a may further include substrate 312a. In some embodiments, substrate 312a includes a semiconductor structure such as a silicon structure (Si) or a gallium arsenide (GaAs) structure, among other examples. In some embodiments, substrate 312a includes a dielectric structure such as an oxide structure, among other examples. Additionally or alternatively, and in some embodiments, substrate 312a conforms to a silicon-on-insulator (SOI) structure.

[0091] As Figure 3As shown in the detailed view, semiconductor device 302a includes a multi-layer photodiode structure 314. The multi-layer photodiode structure 314 included in a portion of pixel sensor 202 includes a plurality of sensing structures, such as sensing structure 316a (e.g., a lower sensing structure) and sensing structure 316b (e.g., a sensing structure above sensing structure 316a). Sensing structures 316a and 316b can each be formed of a quantum effect structure, such as a germanium structure (Ge), a silicon germanium structure (SiGe), a type-III structure, a type-V structure, or another suitable quantum effect structure. In some implementations, sensing structures 316a and 316b include the same quantum effect structure. In some implementations, sensing structures 316a and 316b include different individual quantum effect structures. In some implementations, as Figure 3 As shown in the enlarged view of, the sidewall of sensing structure 316a contacts substrate 312a (e.g., the sidewall of sensing structure 316a interfaces with the sidewall of a cavity formed in substrate 312a).

[0092] As described in connection with Figures 5A to 5L more particularly, after forming a cavity and / or groove in substrate 312a (and / or other layers of multi-layer photodiode structure 314) using optical lithography and etching processes, a selective epitaxial growth process can be used to form the quantum effect structures of sensing structures 316a and / or 316b. However, other formation techniques can be used, such as formation via a direct epitaxial growth process, formation after surface treatment of substrate 312a and / or other layers of multi-layer photodiode structure 314a, and other examples.

[0093] In some implementations, each of sensing structures 316a and 316b includes multiple types of ions to form a p-n junction or a p-i-n junction (e.g., a junction between a p-type region, an intrinsic (or undoped) type region, and an n-type region). For example, sensing structure 316a and / or 316b can be doped with an n-type dopant to form individual n-type regions within sensing structure 316a and / or 316b. Additionally or alternatively, sensing structure 316a and / or 316b can be doped with a p-type dopant to form individual p-type regions within sensing structure 316a and / or 316b.

[0094] As Figure 3 As shown in the detailed view of, electromagnetic waves 318a and 318b (e.g., light waves) are shown passing through multi-layer photodiode structure 314. Electromagnetic wave 318a passes through sensing structure 316a and sensing structure 316b. Within multi-layer photodiode structure 314, the quantum length of electromagnetic wave 318a corresponds to the sum of the thickness D1 of sensing structure 316a and the thickness D2 of sensing structure 316b.

[0095] In addition, the electromagnetic wave 318b passes through the sensing structure 316b. Within the multi-layer photodiode structure 314, the quantum length of the electromagnetic wave 318b corresponds to the thickness D2 of the sensing structure 316b.

[0096] Thus, with respect to another photodiode structure including another sensing structure formed of a single layer of a quantum structure (e.g., for the electromagnetic waves 318a and 318b in such a photodiode structure, the effective quantum length is D1+D1 or D2+D2), the effective quantum lengths (e.g., D1+D2+D2) of the multi-layer photodiode structure 314 for the electromagnetic waves 318a and 318b are increased.

[0097] In this way, with respect to another optoelectronic device including a sensing structure formed of a single layer of a quantum effect structure, the performance (e.g., sensitivity) of the optoelectronic device 300 including the multi-layer photodiode structure 314 is improved. By improving the performance of the optoelectronic device 300, the quality and reliability of the optoelectronic device 300 for a target application and / or environment can be increased, thereby increasing the manufacturing yield and reducing the in-field failure rate. Increasing the manufacturing yield and reducing the in-field failure rate can reduce the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to support the market for the optoelectronic device 300.

[0098] The thickness ranges of the sensing structure 316a and the sensing structure 316b can be similar. For example, in some implementations, each of the thickness D1 and the thickness D2 is included in the range of about 1 micron to about 10 microns.

[0099] In some implementations, thickness D2 is smaller than thickness D1. Additionally or alternatively, the ratio of D2:D1 may be included in the range of about 1:2 to about 1:1. If the ratio of D2:D1 is included in the range of about 1:2 to about 1:1, the effective quantum length of the multi-layer photodiode structure 314 can be sufficiently extended to meet the quantum effect performance threshold value (e.g., the sensitivity threshold value of the optoelectronic device 300). Additionally or alternatively, if the ratio of D2:D1 is in the range of about 1:2 to about 1:1, the size of the multi-layer photodiode structure 314 can be such that the multi-layer photodiode structure 314 is spatially compatible with other integrated circuit systems included in the optoelectronic device 300. Additionally or alternatively, if the ratio of D2:D1 is in the range of about 1:2 to about 1:1, the cost of the optoelectronic device 300 can be viable. If the ratio of D2:D1 is less than about 1:2, the effective quantum length of the multi-layer photodiode structure 314 may not be sufficiently extended to meet the quantum effect performance threshold value. If the ratio of D2:D1 is greater than about 1:1, the cost and / or efficiency of manufacturing the optoelectronic device 300 may increase. Additionally or alternatively, and if the ratio of D2:D1 is greater than about 1:1, the size of the multi-layer photodiode structure 314 can be such that the multi-layer photodiode structure 314 is not spatially compatible with other integrated circuit systems included in the optoelectronic device 300. However, other values and ranges of thicknesses D1 and D2, as well as the ratio of D2:D1, are within the scope of the present disclosure.

[0100] The semiconductor device 302a may include additional features, such as a fixed lens or a modulating lens, to focus and / or distribute electromagnetic waves (e.g., electromagnetic waves 318a, 318b, and / or other similar electromagnetic waves) between sensing structures (e.g., sensing structures 316a and / or 316b, and / or other similar sensing structures), thereby tuning or enhancing the performance of the multi-layer photodiode structure 314. Focusing and / or distributing electromagnetic waves may include focusing and / or distributing electromagnetic waves to pass through the center or the edge of the sensing structure, and other examples.

[0101] As Figure 3 shown, the semiconductor device 302a includes bonding pads 320. The bonding pads 320 may contact one or more metallization layers 310a in the dielectric region 308a. The bonding pads 320 may include a conductive structure, such as gold, silver, aluminum, copper, aluminum copper, titanium, tantalum, titanium nitride, tantalum nitride, tungsten, metal alloys, other metals, or combinations thereof. The bonding pads 320 may provide an electrical connection between the metallization layers 310a of the optoelectronic device 300 and an external device and / or an external package.

[0102] In some implementations, as Figure 3As shown, semiconductor device 302a includes a dielectric layer 322 over a multilayer photodiode structure 314. In some embodiments, dielectric layer 322 includes a structure such as a tin nitride (TiN) structure or an oxide such as a silicon dioxide (SiO2) structure. In some embodiments, portions of dielectric layer 322 are part of a color filter array (CFA) structure. Additionally or alternatively, and in some embodiments, portions of dielectric layer 322 are part of a hard mask (HM) structure.

[0103] As Figure 3 further shown, a microlens layer 324 is included over and / or on dielectric layer 322. Microlens layer 324 may include a plurality of microlenses. Specifically, microlens layer 324 may include individual microlenses for pixel sensors in a pixel sensor array (e.g., each of the pixel sensors 202 included in pixel array 200).

[0104] As Figure 3 further shown, semiconductor device 302b may include a dielectric region 308b. Dielectric region 308b (e.g., an intermetal dielectric region) may include one or more layers of a dielectric structure (e.g., silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), carbon-doped silicon oxide, or another dielectric structure). One or more metallization layers 310b may be formed in and / or between dielectric region 308b. Metallization layers 310b may include bonding pads, conductive lines, and / or other types of conductive structures to electrically connect the various regions of semiconductor device 302b and / or the various regions of optoelectronic device 300 to one or more external devices and / or external packages. In some embodiments, metallization layers 310b may be referred to as a BEOL metallization stack and may include conductive structures such as gold, copper, silver, cobalt, tungsten, metal alloys, or combinations thereof, among other examples.

[0105] Semiconductor device 302b may further include a substrate 312b. In some embodiments, substrate 312b includes a semiconductor structure such as a silicon structure (Si) or a gallium arsenide structure (GaAs), among other examples. As Figure 3 further shown, semiconductor device 302b includes a logic integrated circuit system 326 in or on substrate 312b. In some embodiments, logic integrated circuit system 326 is electrically connected to multilayer photodiode structure 314 via a bonding interface 304 (e.g., via contacts 306a and 306b).

[0106] AsFigure 3 As shown, a device (e.g., optoelectronic device 300) includes a first semiconductor die (e.g., semiconductor device 302a). The first semiconductor die includes a first substrate (e.g., substrate 312a) and a pixel sensor (e.g., pixel sensor 202). The pixel sensor includes a multi-layer photodiode structure (e.g., multi-layer photodiode structure 314), including a first sensing structure extending into the first substrate, where the first sensing structure includes a first quantum effect structure and has sidewalls in direct contact with the first substrate. The multi-layer photodiode structure includes a second sensing structure above the first sensing structure and including a second quantum effect structure. The device includes a second semiconductor die (e.g., semiconductor device 302b) bonded below and to the first semiconductor die. The second semiconductor die includes a second substrate (e.g., substrate 312b) and a logic integrated circuit system (e.g., logic integrated circuit system 326) on or within the second substrate.

[0107] Although Figure 3 the optoelectronic device 300 corresponds to a stacked device (e.g., semiconductor device 302a stacked on semiconductor device 302b), the structures and / or features described in conjunction with Figure 3 may be included in other types of optoelectronic devices (frontside illumination sensor (FSI) devices or backside illumination sensor (BSI) devices, and other examples).

[0108] As described above, Figure 3 is provided as an example. Other examples may differ from those described with respect to Figure 3 described.

[0109] Figures 4A to 4D is a schematic diagram of an example implementation 400 of the multi-layer photodiode structure described herein. The multi-layer photodiode structure may correspond to the multi-layer photodiode structure 314 described in conjunction with Figure 3 and elsewhere herein. Figures 4A to 4D shows different configurations of the multi-layer photodiode structure 314 relative to an electromagnetic wave transmission region 402 (e.g., the electromagnetic transmission region for electromagnetic waves 318a and 318b) including a sensing structure 316a and having a width substantially the same as that of the sensing structure 316a.

[0110] In Figure 4A the multi-layer photodiode structure 314a, the electromagnetic wave transmission region 402 includes the sensing structure 316a and a portion of the sensing structure 316b (e.g., the sensing structure 316b extending laterally into the electromagnetic wave transmission region 402).

[0111] InFigure 4A In [reference], the sensing structure 316a extends into the substrate 312a. The sidewalls of the multi-layer photodiode structure 314a are in contact (e.g., directly in contact) with the substrate 312a. As described in connection with Figure 5B and Figure 5C more particularly, the sidewalls of the sensing structure 316a (e.g., the first sensing structure) can be in contact with the sidewalls of a cavity formed in the substrate 312a. Additionally, the sensing structure 316b (e.g., the second sensing structure) is above the sensing structure 316a (e.g., the first sensing structure).

[0112] As Figure 4A further shown in [reference], the electromagnetic wave transmission region 402 has a width D3 that is substantially the same as that of the sensing structure 316a. As an example, the width D3 can be in the range of about 1 micron to about 10 microns. If the width D3 is in the range of about 1 micron to about 10 microns, the electromagnetic wave transmission region 402 can provide sufficient width to detect electromagnetic waves (e.g., electromagnetic waves 318a and 318b), thereby improving the performance of the multi-layer photodiode structure 314a. Additionally or alternatively, and if the width D3 is in the range of about 1 micron to about 10 microns, the size of the multi-layer photodiode structure 314 can keep the size (and cost) of the optoelectronic device (e.g., optoelectronic device 300) including the multi-layer photodiode structure 314 within a variable range. If the width D3 is less than about 1 micron, the sensing structure 316a and / or the electromagnetic wave transmission region 402 may span an area insufficient to detect electromagnetic waves (e.g., electromagnetic waves 318a and 318b), and thus reduce the performance of the multi-layer photodiode structure 314a. If the width D3 is greater than about 10 microns, the size (and cost) of the optoelectronic device (e.g., optoelectronic device 300) including the multi-layer photodiode structure 314a may increase. However, other values and ranges of the width D3 are within the scope of this disclosure.

[0113] The multi-layer photodiode structure 314a includes an oxide structure 404 that is below the sensing structure 316b and above the sensing structure 316a. The oxide structure 404 can include a silica structure (SiO2), among other examples.

[0114] Additionally, the multi-layer photodiode structure 314a includes a dielectric structure 406a (e.g., the first layer of the dielectric structure) above the oxide structure 404. The dielectric structure 406a can include a silicon nitride structure (SiN), among other examples.

[0115] As Figure 4A further shown in [reference], the sensing structure 316b includes a bottom protrusion 408a (e.g., the first bottom protrusion), and the bottom protrusion extends through the dielectric structure 406a, through the oxide structure 404, and reaches the substrate. As described in connection withFigure 5F and Figure 5G More specifically, the bottom-side protrusion 408a may be formed during the epitaxial growth operation that begins to form the sensing structure 316b within the cavity through the dielectric structure 406a and the oxide structure 404.

[0116] As Figure 4B shown in the multi-layer photodiode structure 314b (second exemplary implementation) of Figure 4A , contrary to the multi-layer photodiode structure 314a of

[0117] the sensing structure 316b is included outside the electromagnetic wave transmission region 402. The multi-layer photodiode structure 314b may satisfy a performance range different from another performance range associated with the multi-layer photodiode structure 314a (e.g., a range bounded by a lower sensitivity threshold value and an upper sensitivity threshold value). Additionally or alternatively, the effective quantum length of the multi-layer photodiode structure 314b may be different from the effective quantum length associated with the multi-layer photodiode structure 314a. Figure 4C As Figure 4A shown in the multi-layer photodiode structure 314c (third exemplary implementation) of Figure 4B , compared with the multi-layer photodiode structure 314a of

[0118] Figure 4C and the multi-layer photodiode structure 314b of

[0119] the electromagnetic wave transmission region 402 includes a portion of the sensing structure 316c (e.g., a third sensing structure that laterally extends into the electromagnetic wave transmission region 402).

[0120] The multi-layer photodiode structure 314c can meet a performance range different from another performance range associated with the multi-layer photodiode structure 314a and / or the multi-layer photodiode structure 314b. Additionally or alternatively, the effective quantum length of the multi-layer photodiode structure 314c can be different from the effective quantum length associated with the multi-layer photodiode structure 314a and / or the multi-layer photodiode structure 314b.

[0121] As Figure 4D shown by the multi-layer photodiode structure 314d (fourth example implementation) of Figure 4C , contrary to the multi-layer photodiode structure 314c of

[0122] , the sensing structure 316c is within the electromagnetic wave transmission region 402. The multi-layer photodiode structure 314d can meet a performance range different from another performance range associated with the multi-layer photodiode structure 314a, the multi-layer photodiode structure 314b, and / or the multi-layer photodiode structure 314c. Additionally or alternatively, the effective quantum length of the multi-layer photodiode structure 314d can be different from the effective quantum length associated with the multi-layer photodiode structure 314a, the multi-layer photodiode structure 314b, and / or the multi-layer photodiode structure 314c. Figure 3 and Figures 4A to 4D described, in some implementations, an optoelectronic device (e.g., the optoelectronic device 300) includes a substrate (e.g., the substrate 312a). The optoelectronic device includes a multi-layer photodiode structure (e.g., the multi-layer photodiode structure 314), and the multi-layer photodiode structure includes a first sensing structure (e.g., the sensing structure 316a) extending into the substrate. The first sensing structure includes a first quantum effect structure and has a sidewall in direct contact with the substrate. The multi-layer photodiode structure includes a second sensing structure (e.g., the sensing structure 316b), and the second sensing structure is above the first sensing structure and includes a second quantum effect structure. The multi-layer photodiode structure includes an oxide structure (e.g., the oxide structure 404) below the second sensing structure and above the first sensing structure. The multi-layer photodiode structure includes a dielectric structure (e.g., the dielectric structure 406a) above the oxide structure and below the second sensing structure.

[0123] As described above, Figures 4A to 4D provided as an example. Other examples can be different from those regarding Figures 4A to 4D described.

[0124] Figures 5A to 5L is a schematic diagram of the example implementation 500 described herein. The implementation 500 can include a series of one or more semiconductor processing operations performed by one or more of the semiconductor processing tools 102 - 116 and / or the wafer / die transfer tool 118 of Figure 1 .

[0125] As shown Figure 5A in, an oxide structure 404 is formed above and / or on a substrate 312a. A deposition tool 102 can be used to deposit the oxide structure 404 (or another suitable dielectric structure) in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, a deposition operation of another type as described in combination Figure 1 with, and / or another suitable deposition operation. In some embodiments, a planarization tool 110 can be used to planarize the oxide structure 404 after depositing the oxide structure.

[0126] As an example, in some embodiments, the oxide structure 404 has a thickness of up to about 1 micron. However, other values and ranges of thickness are within the scope of the present disclosure.

[0127] As shown Figure 5B in, a cavity 502 is formed through the oxide structure 404 and into the substrate 312a. In some embodiments, a pattern in a photoresist layer is used to etch the oxide structure 404 and the substrate 312a to form the cavity 502. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the oxide structure 404. An exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. An etch tool 108 can be used to etch the oxide structure 404 and the substrate 312a based on the pattern to form the cavity 502. In some embodiments, the etch operation includes a plasma etch operation, a wet chemical etch operation, and / or another type of etch operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching the oxide structure 404 and the substrate 312a based on the pattern.

[0128] As an example, in some embodiments, the cavity 502 has a width of up to about 10 microns and a depth of up to about 10 microns. However, other values and ranges of width and depth are within the scope of the present disclosure.

[0129] As shown Figure 5C in, a sensing structure 316a is formed above and / or on the substrate 312a (e.g., within the cavity 502). The deposition tool 102 can be used to deposit a quantum effect structure in an epitaxial operation, a deposition operation of another type as described in combination Figure 1 with, and / or another suitable deposition operation to form the sensing structure 316a.

[0130] As shown Figure 5DAs shown, the sensing structure 316a is planarized. The planarization tool 110 can be used to planarize the sensing structure 316a using a CMP operation, in combination with Figure 1 the other type of planarization operation described, and / or another planarization operation. In some embodiments, planarizing the sensing structure 316a can include removing a portion of the oxide structure 404.

[0131] As Figure 5E shown, a dielectric structure 406a is formed above and / or on the oxide structure 404 and above and / or on the sensing structure 316a. The deposition tool 102 can be used to deposit the dielectric structure 406a in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, in combination with Figure 1 the other type of deposition operation described, and / or another suitable deposition operation. In some embodiments, the planarization tool 110 can be used to planarize the dielectric structure 406a after depositing the dielectric structure 406a.

[0132] As an example, in some embodiments, the dielectric structure 406a has a thickness of up to about 2 microns. However, other values and ranges of thickness are within the scope of the present disclosure.

[0133] As Figure 5F shown, a recessed region 504 is formed in the dielectric structure 406a. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric structure 406a to form the recessed region 504. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the dielectric structure 406a. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric structure 406a based on the pattern to form a groove in the dielectric structure 406a. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching the dielectric structure 406a based on the pattern.

[0134] In some embodiments ( Figure 4A of the multi-layer photodiode structure 314a, and other examples), as Figure 5F shown, the recessed region 504 extends across a boundary 506 corresponding to the outer edge of the sensing structure 316a such that the recessed region 504 overlaps the sensing structure 316a. In some embodiments ( Figure 4BIn the multi-layer photodiode structure 314b, and other examples, a recessed region 504 is included adjacent to the boundary 506 such that no portion of the recessed region 504 overlaps with the sensing structure 316a.

[0135] As Figure 5F As further shown in, in the recessed region 504, a cavity 508 is formed through the dielectric structure 406a and through the oxide structure 404 to the substrate 312a. In some implementations, a pattern in a photoresist layer is used to etch the dielectric structure 406a and the oxide structure 404 to form the cavity 508. In these implementations, the deposition tool 102 can be used to form a photoresist layer on the dielectric structure 406a. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric structure 406a and the oxide structure 404 based on the pattern to form the cavity 508. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for etching the oxide and the dielectric structure 406a and the oxide structure 404 based on the pattern.

[0136] In some implementations, the cavity 508 can be formed to have a width D4, and the width D4 is included in the range of about 0.1 micrometer to about 1.0 micrometer. Additionally or alternatively, the cavity 508 can be formed to have a depth D5, and the depth D5 is included in the range of about 0.1 micrometer to about 1.0 micrometer. If the width D4 and / or the depth D5 are in the range of about 0.1 micrometer to about 1.0 micrometer, the volume of the cavity 508 can be sufficient to initiate epitaxial growth for a quantum effect structure of another sensing structure (e.g., the sensing structure 316b). Additionally or alternatively, the aspect ratio of the cavity 508 can reduce defects (e.g., delamination, voids) within the quantum effect structure. If the cavity 508 has a width D4 and / or a depth D5 less than about 0.1 micrometer, the volume of the cavity 508 may not be sufficient to initiate epitaxial growth for the quantum effect structure of other sensing structures. If the cavity 508 has a width D4 and / or a depth D5 greater than about 1.0 micrometer, the aspect ratio of the cavity 508 may cause defects (e.g., delamination, voids) within the quantum effect structure. However, other values and ranges of the width D4 and the depth D5 are within the scope of the present disclosure.

[0137] As Figure 5G As shown in, a sensing structure 316b is formed above and / or on the dielectric structure 406a (e.g., within the recessed region 504). The deposition tool 102 can be used in an epitaxial operation, combinationFigure 1 Another type of deposition operation, and / or another suitable deposition operation, to deposit a quantum effect structure to form the sensing structure 316b. As Figure 5G shown, forming the sensing structure 316b includes forming a bottom protrusion 408a (e.g., within the cavity 508). The bottom protrusion 408a may have dimensions similar to those of the cavity 508 (e.g., width D4 and depth D5).

[0138] As Figure 5H shown, the sensing structure 316b is planarized. The planarization tool 110 can be used to planarize the sensing structure 316b using a CMP operation, in combination with Figure 1 another type of planarization operation, and / or another planarization operation.

[0139] As Figure 5I shown, an epitaxial structure 410 is formed above and / or on the sensing structure 316b. The deposition tool 102 can be used to deposit the epitaxial structure 410 in an epitaxial operation, in combination with Figure 1 another type of deposition operation, and / or another suitable deposition operation. In some embodiments, the planarization tool 110 can be used to planarize the epitaxial structure 410 after depositing the epitaxial structure 410.

[0140] As an example, in some embodiments, the epitaxial structure 410 has a thickness D6 that includes a range from about 4 microns to about 6 microns. If the thickness D6 includes a range from about 4 microns to about 6 microns, the risk of electrical leakage within a semiconductor device (e.g., semiconductor device 302a) that includes the epitaxial structure 410 may be reduced. Additionally or alternatively, if the thickness D6 includes a range from about 4 microns to about 6 microns, the cost of manufacturing the semiconductor device may be feasible. If the thickness D6 is less than about 4 microns, the leakage risk within the semiconductor device that includes the epitaxial structure 410 may increase. If the thickness D6 is greater than about 6 microns, the cost of manufacturing the semiconductor device may increase and be infeasible. However, other values and ranges of the thickness D6 are within the scope of the present disclosure.

[0141] As Figure 5I further shown, a dielectric structure 406b is formed above and / or on the epitaxial structure 410. The deposition tool 102 can be used to deposit the dielectric structure 406b in a PVD operation, an ALD operation, a CVD operation, an epitaxial operation, an oxidation operation, in combination with Figure 1 another type of deposition operation, and / or another suitable deposition operation. In some embodiments, the planarization tool 110 can be used to planarize the dielectric structure 406b after depositing the dielectric structure 406b.

[0142] As an example, in some implementations, the dielectric structure 406b has a thickness of up to about 2 microns. However, other values and ranges of thickness are within the scope of the present disclosure.

[0143] As Figure 5J shown, a recessed region 510 is formed in the dielectric structure 406b. In some implementations, a pattern in a photoresist layer is used to etch the dielectric structure 406b to form the recessed region 510. In these implementations, the deposition tool 102 can be used to form a photoresist layer on the dielectric structure 406b. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric structure 406b based on the pattern to form a groove in the dielectric structure 406b. In some implementations, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique for etching the dielectric structure 406b based on the pattern.

[0144] In some implementations ( Figure 4C of the multi-layer photodiode structure 314c and other examples), as Figure 5J shown, the recessed region 510 extends across a boundary 506 corresponding to the outer edge of the sensing structure 316a such that the recessed region 510 overlaps the sensing structure 316a. In some implementations ( Figure 4D of the multi-layer photodiode structure 314d, and other examples), the recessed region 510 is centered over the sensing structure 316a.

[0145] As Figure 5JAs further shown, in the recessed area 510, a cavity 512 is formed through the dielectric structure 406b and reaches the epitaxial structure 410. In some embodiments, the pattern in the photoresist layer is used to etch the dielectric structure 406b to form the cavity 512. In these embodiments, the deposition tool 102 can be used to form a photoresist layer on the dielectric structure 406b. The exposure tool 104 can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be used to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 can be used to etch the dielectric structure 406b based on the pattern to form the cavity 512. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for etching the oxide and the dielectric structure 406b.

[0146] In some embodiments, the cavity 512 can have dimensions similar to those of other cavities used to form the sensing structure (e.g., the cavity 508 for epitaxial growth of the sensing structure 316b). For example, the cavity 512 can be formed to have a width D4, and the width D4 is included in the range of about 0.1 micrometer to about 1.0 micrometer. Additionally or alternatively, the cavity 512 can be formed to have a depth D5, and the depth D5 is included in the range of about 0.1 micrometer to about 1.0 micrometer. If the width D4 and / or the depth D5 are in the range of about 0.1 micrometer to about 1.0 micrometer, the volume of the cavity 512 can be sufficient to initiate epitaxial growth of a quantum effect structure for another sensing structure (e.g., the sensing structure 316c). Additionally or alternatively, the aspect ratio of the cavity 512 can reduce defects (e.g., delamination, voids) within the quantum effect structure. If the cavity 512 has a width D4 and / or a depth D5 less than about 0.1 micrometer, the volume of the cavity 512 may not be sufficient to initiate epitaxial growth of a quantum effect structure for other sensing structures. If the cavity 512 has a width D4 and / or a depth D5 greater than about 1.0 micrometer, the aspect ratio of the cavity 512 may cause defects (e.g., delamination, voids) within the quantum effect structure. However, other values and ranges of the width D4 and the depth D5 are within the scope of the present disclosure.

[0147] As Figure 5K shown, a sensing structure 316c is formed above and / or on (e.g., within the recessed area 510) the epitaxial structure 410. The deposition tool 102 can be used to deposit a quantum effect structure to form the sensing structure 316c during an epitaxial operation, in combination with Figure 1 the other type of deposition operation described above, and / or another suitable deposition operation. As Figure 5KAs shown, forming the sensing structure 316c includes forming a bottom protrusion 408b (e.g., within the cavity 512). The bottom protrusion 408b may have dimensions similar to those of the cavity 512 (e.g., width D4 and depth D5).

[0148] As Figure 5L shown, the sensing structure 316c is planarized. A planarization tool 110 may be used to planarize the sensing structure 316c using a CMP operation, in combination with Figure 1 the other type of planarization operation described, and / or another planarization operation.

[0149] Figures 5A to 5L The implementation 500 shown is provided as an example. The implementation 500 may include additional semiconductor processing operations, fewer semiconductor processing operations, different semiconductor processing operations, or differently configured semiconductor processing operations compared to those shown. Additionally or alternatively, one or more semiconductor processing operations may be performed using techniques and / or semiconductor processing tools other than those described in combination with Figures 5A to 5L those shown. Figure 1 The techniques described and / or semiconductor processing tools other than those described.

[0150] Figure 6 is a schematic diagram of example components of one or more of the Figure 1 devices described herein. In some implementations, the semiconductor processing tools 102-116 and / or the wafer / die transfer tool 118 may include one or more devices 600 and / or one or more components of the device 600. As Figure 6 shown, the device 600 may include a bus 610, a processor 620, a memory 630, an input component 640, an output component 650, and / or a communication component 660.

[0151] The bus 610 may include one or more components that enable wired and / or wireless communication between the components of the device 600. The bus 610 may couple Figure 6 two or more of the

[0152] Memory 630 may include volatile and / or non-volatile memory. For example, memory 630 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 630 may include internal memory (e.g., RAM, ROM, or a hard disk drive) and / or removable memory (e.g., removable via a Universal Serial Bus connection). Memory 630 may be a non-transitory computer-readable medium. Memory 630 may store information related to the operation of device 600, one or more instructions, and / or software (e.g., one or more software applications). In some implementations, memory 630 may include one or more memories such as coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 620) via bus 610. The communicative coupling between processor 620 and memory 630 may enable processor 620 to read and / or process information stored in memory 630 and / or store information in memory 630.

[0153] Input component 640 may enable device 600 to receive input, such as user input and / or sensed input. For example, input component 640 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, switches, sensors, a Global Positioning System sensor, a Global Navigation Satellite System sensor, an accelerometer, a gyroscope, and / or an actuator. Output component 650 may enable device 600 to provide output, such as via a display, a speaker, and / or a light-emitting diode. Communication component 660 may enable device 600 to communicate with other devices via a wired connection and / or a wireless connection. For example, communication component 660 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0154] Device 600 may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 630) may store a set of instructions (e.g., one or more instructions or code) for execution by processor 620. Processor 620 may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions by one or more processors 620 causes one or more processors 620 and / or device 600 to perform one or more operations or processes described herein. In some implementations, hardwired circuitry may be used in place of or in combination with the instructions to perform one or more operations or processes described herein. Additionally or alternatively, processor 620 may be used to perform one or more operations or processes described herein. Accordingly, the implementations described herein are not limited to any particular combination of hardware circuitry and software.

[0155] Figure 6 The number and configuration of the components shown are provided as examples. Device 600 may include additional components, fewer components, different components, or components with a different configuration compared to the components shown in Figure 6 In addition or alternatively, a set of components (e.g., one or more components) of device 600 may perform one or more functions described as being performed by another set of components of device 600.

[0156] Figure 7 FIG. is a flowchart of an example process 700 associated with forming the multi-layer photodiode structure described herein. In some implementations, one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102-116) are used to perform Figure 7 one or more of the process blocks in Figure 7 In addition or alternatively, one or more components in device 600, such as processor 620, memory 630, input component 640, output component 650, and / or communication component 660, may be used to perform

[0157] As Figure 7 shown in

[0158] As Figure 7 further shown in

[0159] As Figure 7 further shown in

[0160] As Figure 7As further shown in, process 700 may include forming a dielectric material (dielectric structure) over the first sensing structure (block 740). For example, one or more of semiconductor processing tools 102-116 may be used to form a dielectric material (dielectric structure) (e.g., dielectric structure 406a) over the first sensing structure, as described herein.

[0161] As Figure 7 As further shown in, process 700 may include forming a recessed region within the dielectric material (dielectric structure) (block 750). For example, one or more of semiconductor processing tools 102-116 may be used to form a recessed region (e.g., region 504) within the dielectric material (dielectric structure), as described herein.

[0162] As Figure 7 As further shown in, process 700 may include forming a second cavity that passes through the dielectric material (dielectric structure) within the recessed region and through the oxide material to the substrate (block 760). For example, one or more of semiconductor processing tools 102-116 may be used to form a second cavity (e.g., cavity 508) that passes through the dielectric structure within the recessed region and through the oxide structure to the substrate, as described herein.

[0163] As Figure 7 As further shown in, process 700 may include forming a second sensing structure that is over the recessed region and includes a bottom protrusion that fills the second cavity to connect to the substrate (block 770). For example, one or more of semiconductor processing tools 102-116 may be used to form a second sensing structure (e.g., sensing structure 316b) that is over the recessed region and includes a bottom protrusion (e.g., bottom protrusion 408a) that fills the second cavity to connect to the substrate, as described herein. In some implementations, forming the second sensing structure includes forming the second sensing structure over the first sensing structure.

[0164] Process 700 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described herein and / or combined elsewhere herein.

[0165] In a first implementation, forming the first sensing structure includes epitaxially growing a type III structure or a type V structure in the first cavity, and planarizing the type III structure and the type V structure after epitaxially growing the type III structure or the type V structure in the first cavity.

[0166] In a second implementation, alone or in combination with the first implementation, forming the recessed region includes forming the recessed region to include a portion that extends across a boundary (e.g., boundary 506) corresponding to an outer edge of the first sensing structure such that the recessed region overlaps the first sensing structure.

[0167] In a third implementation, alone or in combination with one or more of the first and second implementations, forming a recessed area includes forming the entirety of the recessed area to be adjacent to a boundary corresponding to an outer edge of the first sensing structure (e.g., boundary 506) such that no part of the recessed area overlaps with the first sensing structure.

[0168] In a fourth implementation, alone or in combination with one or more of the first through third implementations, forming a second cavity includes forming the second cavity to have a width in the range of about 0.1 micrometer to about 1.0 micrometer (e.g., width D4), or forming the second cavity to have a depth included in the range of about 0.1 micrometer to about 1.0 micrometer (e.g., depth D5).

[0169] In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, forming a second sensing structure includes epitaxially growing a type-III structure or a type-V structure in the second cavity and above the dielectric structure, where epitaxial growth of the type-III structure or the type-V structure begins within the second cavity and the type-III structure or the type-V structure is planarized after epitaxial growth within the second cavity and above the dielectric structure.

[0170] Although Figure 7 example blocks of process 700 are shown, in some implementations, process 700 includes additional blocks, fewer blocks, different blocks, or differently configured blocks compared to the blocks depicted in Figure 7 In addition or alternatively, two or more blocks in process 700 may be executed in parallel.

[0171] Some implementations described herein provide an optoelectronic device that includes a multi-layer photodiode structure having a plurality of sensing structures formed by one or more quantum effect structures (e.g., formed by multiple layers of quantum effect structures). The plurality of sensing structures including sidewalls in contact with a substrate of the optoelectronic device may be stacked and include overlapping portions. By using the multi-layer photodiode structure including the plurality of sensing structures, the quantum length is increased relative to another photodiode structure including a single planar sensing structure formed by a single layer of quantum effect structures.

[0172] In this way, the performance of the optoelectronic device including the multi-layer photodiode structure is improved relative to another optoelectronic device including a single planar sensing structure. By improving the performance of the optoelectronic device, the quality and reliability of the optoelectronic device for target applications and / or environments can be increased, thereby increasing the manufacturing yield and reducing the in-field failure rate. Increasing the manufacturing yield and reducing the in-field failure rate can reduce the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) required to support the market for consumer optoelectronic devices.

[0173] As described in more detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes a substrate. The optoelectronic device includes a multi-layer photodiode structure that includes a first sensing structure extending into the substrate. The first sensing structure includes a first quantum effect structure and has sidewalls that are in direct contact with the substrate. The multi-layer photodiode structure includes a second sensing structure that is above the first sensing structure and includes a second quantum effect structure. The multi-layer photodiode structure includes an oxide structure that is below the second sensing structure and above the first sensing structure. The multi-layer photodiode structure includes a dielectric structure that is above the oxide structure and below the second sensing structure.

[0174] In some embodiments, the second sensing structure includes: a bottom protrusion that extends downward through the dielectric structure, through the oxide structure, and to the substrate.

[0175] In some embodiments, the first quantum effect structure or the second quantum effect structure includes: a germanium structure, or a silicon-germanium structure.

[0176] In some embodiments, the optoelectronic device corresponds to: a front-side illumination sensor, or a back-side illumination sensor.

[0177] In some embodiments, the ratio of the thickness of the second sensing structure to the thickness of the first sensing structure is greater than about 1:2.

[0178] In some embodiments, the multi-layer photodiode structure further includes: an electromagnetic wave transmission region that is vertically disposed, includes the first sensing structure, and has a width that is substantially the same as that of the first sensing structure.

[0179] In some embodiments, the second sensing structure laterally extends into the electromagnetic wave transmission region.

[0180] In some embodiments, the second sensing structure is included outside the electromagnetic wave transmission region.

[0181] As described in more detail above, some embodiments described herein provide a semiconductor device. The device includes a first semiconductor die. The first semiconductor die includes a first substrate and a pixel sensor. The pixel sensor includes a multi-layer photodiode structure that includes a first sensing structure extending into the first substrate, wherein the first sensing structure includes a first quantum effect structure and has sidewalls that are in direct contact with the first substrate. The multi-layer photodiode structure includes a second sensing structure that is above the first sensing structure and includes a second quantum effect structure. The device includes a second semiconductor die that is bonded to the first semiconductor die below the first semiconductor die. The second semiconductor die includes a second substrate and a logic integrated circuit system on or within the second substrate.

[0182] In some embodiments, the first substrate comprises: an oxide structure, a silicon structure, or a gallium arsenide structure.

[0183] In some embodiments, the logic integrated circuit system is electrically connected to the multi-layer photodiode structure.

[0184] In some embodiments, the multi-layer photodiode structure further comprises: a third sensing structure, comprising a third quantum effect structure and above the second sensing structure.

[0185] In some embodiments, the multi-layer photodiode structure further comprises: an epitaxial structure, between the third sensing structure and the second sensing structure.

[0186] In some embodiments, each of the first quantum effect structure, the second quantum effect structure, and the third quantum effect structure comprises: a type-III structure, or a type-V structure.

[0187] As described in more detail above, some embodiments herein provide a method of manufacturing a semiconductor device. The method includes forming an oxide structure over a substrate. The method includes forming a first cavity through the oxide structure and into the substrate. The method includes forming a first sensing structure in the first cavity, wherein forming the first sensing structure includes forming sidewalls in direct contact with the surface of the first cavity. The method includes forming a dielectric structure over the first sensing structure. The method includes forming a recessed region within the dielectric structure. The method includes forming a second cavity through the dielectric structure within the recessed region and through the oxide structure to the substrate. The method includes forming a second sensing structure, the second sensing structure above the recessed region and including a bottom protrusion that fills the second cavity to connect with the substrate, wherein forming the second sensing structure includes forming the second sensing structure over the first sensing structure.

[0188] In some embodiments, forming the first sensing structure includes: epitaxially growing a type-III structure or a type-V structure in the first cavity, and planarizing the type-III structure or the type-V structure after epitaxially growing the type-III structure or the type-V structure in the first cavity.

[0189] In some embodiments, forming the recessed region includes: forming the recessed region to include a portion that extends across a boundary corresponding to the outer edge of the first sensing structure such that the recessed region overlaps with the first sensing structure.

[0190] In some embodiments, forming the recessed region includes: forming an entirety of the recessed region to remain adjacent to a boundary corresponding to the outer edge of the first sensing structure such that no portion of the recessed region overlaps with the first sensing structure.

[0191] In some embodiments, forming the second cavity includes: forming the second cavity to have a width in the range of about 0.1 micrometer to about 1.0 micrometer, or forming the second cavity to have a depth in the range of about 0.1 micrometer to about 1.0 micrometer.

[0192] In some embodiments, the step of forming the second sensing structure includes: epitaxially growing a type-III structure or a type-V structure in the second cavity and above the dielectric structure, wherein the epitaxial growth of the type-III structure or the type-V structure starts within the second cavity, and after epitaxially growing the type-III structure or the type-V structure in the second cavity and above the dielectric structure, planarizing the type-III structure or the type-V structure.

[0193] As described in more detail above, some embodiments described herein provide an optoelectronic device. The optoelectronic device includes a substrate, a multi-layer photodiode structure, and an electromagnetic wave transmission region. The multi-layer photodiode structure includes a first sensing structure, a second sensing structure, and an oxide structure. The first sensing structure extends into the substrate, includes a first quantum effect structure, and has a plurality of sidewalls in direct contact with the substrate. The second sensing structure is above the first sensing structure and includes a second quantum effect structure. The oxide structure is below the second sensing structure and above the first sensing structure. The electromagnetic wave transmission region is vertically disposed, includes the first sensing structure, and has the same width as the first sensing structure.

[0194] As used herein, when used in conjunction with a plurality of items, the term “and / or” is intended to individually cover each of the plurality of items as well as any and all combinations of the plurality of items. For example, “A and / or B” covers “A and B”, “A but not B”, and “B but not A”.

[0195] As used herein, depending on the context, “meeting a threshold value” may refer to a value greater than the threshold value, greater than or equal to the threshold value, less than the threshold value, less than or equal to the threshold value, equal to the threshold value, not equal to the threshold value, or the like.

[0196] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use some embodiments of the present disclosure as a basis for designing or modifying other processes and structures for the same purpose and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and such equivalent structures can be variously changed, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. An optoelectronic device, characterized in that, Comprising: a substrate; and a multi-layer photodiode structure, comprising: a first sensing structure extending into the substrate, including a first quantum effect structure and having a plurality of sidewalls in direct contact with the substrate; a second sensing structure above the first sensing structure and including a second quantum effect structure; an oxide structure below the second sensing structure and above the first sensing structure; and a dielectric structure above the oxide structure and below the second sensing structure.

2. The optoelectronic device according to claim 1, characterized in that, Wherein the second sensing structure comprises: a bottom protrusion extending downward through the dielectric structure, through the oxide structure, and reaching the substrate.

3. The optoelectronic device according to claim 1, characterized in that, Wherein the optoelectronic device corresponds to: a front-illuminated sensor, or a back-illuminated sensor.

4. The optoelectronic device according to claim 1, wherein Wherein a ratio of a thickness of the second sensing structure to a thickness of the first sensing structure is greater than 1:

2.

5. A semiconductor device, characterized in that, Comprising: a first semiconductor die, comprising: a first substrate; and a pixel sensor, comprising: a multi-layer photodiode structure, comprising: a first sensing structure extending into the first substrate, including a first quantum effect structure and having a plurality of sidewalls in direct contact with the first substrate; and a second sensing structure above the first sensing structure and including a second quantum effect structure; and a second semiconductor die bonded to and below the first semiconductor die, and comprising: a second substrate; and a logic integrated circuit system on or within the second substrate.

6. The semiconductor device according to claim 5, wherein, Wherein the logic integrated circuit system is electrically connected to the multi-layer photodiode structure.

7. The semiconductor device according to claim 5, wherein, Wherein the multi-layer photodiode structure further comprises: a third sensing structure including a third quantum effect structure and above the second sensing structure.

8. The semiconductor device according to claim 7, wherein, Wherein the multi-layer photodiode structure further comprises: an epitaxial structure between the third sensing structure and the second sensing structure.

9. The semiconductor device according to claim 8, wherein, Wherein each of the first quantum effect structure, the second quantum effect structure, and the third quantum effect structure comprises: a type-III structure, or a type-V structure.

10. An optoelectronic device, characterized in that, Comprising: a substrate; a multi-layer photodiode structure, comprising: a first sensing structure extending into the substrate, including a first quantum effect structure and having a plurality of sidewalls in direct contact with the substrate; a second sensing structure above the first sensing structure and including a second quantum effect structure; and a layer of an oxide structure below the second sensing structure and above the first sensing structure; and an electromagnetic wave transmission region vertically disposed, including the first sensing structure and having the same width as the first sensing structure.

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