Gallium nitride power device saturation characteristic test circuit

Abstract

The utility model discloses a saturation characteristic test circuit for a gallium nitride power device, which is particularly used for optimizing test screening in a middle test stage and comprises a gallium nitride power device, the voltage control circuit is connected to the drain electrode and the source electrode of the gallium nitride power device and is used for controlling the voltage difference output to the two electrodes; the current detection circuit is connected to the grid electrode of the gallium nitride power device to control the grid electrode voltage and detect the grid electrode current; and the current source circuit is connected to the source electrode of the gallium nitride power device so as to control the current flowing through the drain electrode. In conclusion, compared with the prior art, the test circuit has the obvious advantages of being short in test time, high in accuracy, good in stability, low in cost, free of large current in the test process and the like, the test efficiency and the test precision are improved, the loss and the maintenance cost of test equipment are reduced, the high-efficiency, accurate and energy-saving test requirements of the modern electronic industry can be met, and the test cost is reduced. And the quality control efficiency and accuracy of batch production of GaN devices are improved.

Description

Technical Field

[0001] The utility model relates to a test circuit, in particular to a test circuit for the saturation characteristics of gallium nitride power devices. Background Art

[0002] Gallium nitride power devices (GaN devices) show significant advantages in extreme application scenarios such as high voltage, high temperature, and high frequency due to their wide bandgap, high electron mobility, high conductivity, and high thermal conductivity. GaN devices are widely used in military electronics, communication base stations, fast charging, etc., especially in the fast charging field with rapid growth.

[0003] In practical applications, GaN devices work in a high-temperature environment for a long time, and the working current of some unqualified devices will significantly decrease, easily causing current saturation problems and resulting in device damage.

[0004] Problems existing in the existing test technologies include excessive test current causing device heating, long test time, high equipment maintenance cost, low test accuracy, etc. These problems limit the quality control of GaN devices in the mass production process. At the same time, in actual tests, due to the different temperatures of the test environment and the actual application environment, the accuracy of the test results is affected. Especially in the middle test at the wafer stage and the final test after packaging, the test at room temperature is difficult to accurately reflect the performance at high-temperature operation. Content of the Utility Model

[0005] In order to solve the above-mentioned deficiencies of the technology, the utility model provides a test circuit for the saturation characteristics of gallium nitride power devices.

[0006] In order to solve the above technical problems, the technical solution adopted by the utility model is a test circuit for the saturation characteristics of gallium nitride power devices, including:

[0007] Gallium nitride power device;

[0008] A voltage control circuit connected between the drain and source of the gallium nitride power device to control the voltage difference output between the two poles;

[0009] A current detection circuit connected to the gate of the gallium nitride power device to control the gate voltage and detect the gate current;

[0010] A current source circuit connected to the source of the gallium nitride power device to control the current flowing through the drain.

[0011] Further, the voltage control circuit includes operational amplifier U1, operational amplifier U2, and operational amplifier U4;

[0012] The positive input terminal of the operational amplifier U1 is grounded. The negative input terminal of the operational amplifier U1 is connected to the output terminal of the operational amplifier U4 through the resistor R3. The output terminal of the operational amplifier U1 is connected to the D drain of the gallium nitride power device through the NPN transistor Q3. The emitter of the NPN transistor Q3 is connected to the negative input terminal of the operational amplifier U1 through the resistor R1. The negative input terminal of the operational amplifier U1 is connected to the reference voltage signal V3 through the resistor R2. The positive input terminal of the operational amplifier U2 is connected to the source of the gallium nitride power device. The negative input terminal of the operational amplifier U2 is connected to the output terminal of the operational amplifier U2. The output terminal of the operational amplifier U2 is connected to the negative input terminal of the operational amplifier U4 through the resistor R4. The negative input terminal of the operational amplifier U4 is connected to the output terminal of the operational amplifier U2 through the resistor R4. The positive input terminal of the operational amplifier U4 is grounded.

[0013] Further, the base of the NPN transistor Q3 is connected to the output terminal of the operational amplifier U1, the collector of the NPN transistor Q3 is connected to VCC, and the emitter of the NPN transistor Q3 is connected to the D drain of the gallium nitride power device.

[0014] Further, the current source circuit includes an operational amplifier Ua, an operational amplifier Ub, and a transistor Q1;

[0015] The positive input terminal of the operational amplifier Ua is connected to the reference voltage V1 through the resistor Rf2. The negative input terminal of the operational amplifier Ua is grounded through the resistor Rf1. The output terminal of the operational amplifier Ua is connected to the base of the PNP transistor Q1 through the resistor Rb. The emitter of Q1 is connected to one end Vp of the current detection resistor Rcs. The other end Vn of the current detection resistor Rcs is connected to the source of the gallium nitride power device. At the same time, Vn is connected to the positive input terminal of the operational amplifier Ub. The negative input terminal of the operational amplifier Ub is connected to the output terminal of the operational amplifier Ub. The output terminal of the operational amplifier Ub is connected to the positive input terminal of the operational amplifier Ua through the resistor Rf4.

[0016] Further, the positive input terminal of the operational amplifier U3 in the current detection circuit is grounded. The negative input terminal of the operational amplifier U3 is connected to the gate of the gallium nitride power device. The negative input terminal of the operational amplifier U3 is connected to the current detection node Uo3 through the resistor R6. A capacitor C1 is connected in parallel across both ends of the resistor R6.

[0017] The utility model discloses a gallium nitride power device saturation characteristic test circuit, which has obvious advantages such as short test time, high accuracy, good stability, and low cost. By improving the test efficiency and test accuracy, reducing the loss and maintenance cost of test equipment, it can meet the test requirements of high efficiency, precision, and energy saving in modern electronic industry, and improve the quality control efficiency and accuracy of GaN device mass production. Description of the Drawings

[0018] Figure 1 It is the circuit diagram of the existing test scheme.

[0019] Figure 2 It is the corresponding relationship diagram of different GT voltages and saturated Id currents.

[0020] Figure 3 It is the circuit diagram of the present utility model.

[0021] Figure 4 It is the current source circuit.

[0022] Figure 5 It is the data test diagram before improvement.

[0023] Figure 6 It is the data test diagram after improvement. Specific embodiments

[0024] The present utility model will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0025] Before introducing this patent, first understand the reasons for the large test current and long test time in the prior art. Figure 1 It is the circuit diagram of the existing test scheme. Taking a gallium nitride power device with a rated working current of 5A as an example, the principle is described as follows. First, the tester provides a VCC power supply, a 10A constant current source, and a GT drive pulse voltage. The tester contacts the gallium nitride power device through three gold fingers. Among them, both the D pole (drain) and the S pole (source) need to pass through a 10A current (this parameter is generally selected as twice the rated current). The working reliability of these two points should be ensured. Two wires are led out from the D pole and S pole of the gallium nitride power device and connected to the analog test channel of the tester. These two wires do not pass through a strong current and only transmit analog weak voltage signals (attention should be paid to adding a shielding layer to avoid external interference). Place the gallium nitride power device on the test bench. After firmly contacting the test channel of the tester, the tester first gives the VCC voltage and the constant current source. At this time, GT is still at a low level. After a delay by the tester, a high GT pulse is given (with an amplitude of 6V and a duration of 10ms, which can be adjusted according to the actual test situation for different devices). The gallium nitride power device will turn on. Since the current flowing into the D pole far exceeds the rated current, there will be a large voltage drop in Vds (when Id = 2 times the rated current, if Vds exceeds Vds_Limit = 6.5V, it is generally considered that saturation occurs). The tester tests the Vds voltage through a channel that transmits analog signals alone. If it exceeds the limit value Vds_Limit, it is considered that the currently tested GaN device is unqualified.

[0026] Two physical quantities during the test process are noted: one is the current (10 A) flowing into the D pole of the gallium nitride power device under test; the other is the voltage drop of Vds of the gallium nitride power device under test. The product of the current and the voltage is the consumed power. Taking the Vds at critical saturation as an example, its power value can reach 65 W during the high level Ton of GT, which is a relatively large value. While it causes the gallium nitride power device to heat up and affects the test accuracy, it also has an impact on the finished product test equipment and the stress on the contact gold fingers. The probe during the intermediate test bears such a large current, which will further reduce the service life and affect the test reliability.

[0027] This patent discloses a test circuit for the saturation characteristics of a gallium nitride power device. Utilizing the characteristics of the gallium nitride power device, it should be noted that when the gallium nitride power device is actually applied, the high level of the driving pulse of GT is generally controlled to maintain a fixed value (generally 6 V). At room temperature, when the voltage value of GT gradually rises from 0 V to Vth, it starts to conduct. When the voltage value of GT is not very high, Id is controlled by the voltage of GT (the value of Id is weakly related to the voltage of Vds). As Figure 2 shown in the multi-cluster curve simulation, which shows the corresponding relationship diagram between different GT voltages and the saturated Id current. It can be seen that there is a curve corresponding to every 20 mV for the GT voltage from 2.55 V to 2.65 V. The horizontal axis is the Vds voltage, and the vertical axis is Id. At the point Vds = 3 V and Id = 1.1 A in the figure, the corresponding GT voltage is 2.63 V. Taking this point as an example for observation. In other words, when the GT voltage is controlled to be 2.63 V and Vds = 3 V, the generated Id current is 1.1 A. When actually testing a certain number of gallium nitride power devices, when Vds = 3 V is given, the GT voltage value is controlled so that the current Id flowing through the drain of this chip is 1.1 A, and the GT voltage value is recorded. The GT voltage value of this batch of sample devices should be within 2.63 V ± δ. If the GT voltage value of a certain chip exceeds 2.63 V + δ, it means that the over-current capacity of this chip is weak and saturation will occur during normal operation, and it should be screened out; the value of δ is determined based on the actual measurement of a large number of samples. The test scheme proposed in this article is based on this principle.

[0028] As Figure 3 shown, the test circuit for the saturation characteristics of the gallium nitride power device includes:

[0029] Gallium nitride power device GaN;

[0030] A voltage control circuit is connected between the drain and source of a gallium nitride power device to control the voltage difference output between the two poles. The voltage control circuit includes operational amplifier U1, operational amplifier U2, and operational amplifier U4. The positive input terminal of operational amplifier U1 is grounded. The negative input terminal of operational amplifier U1 is connected to the output terminal of operational amplifier U4 through resistor R3. The output terminal of operational amplifier U1 is connected to the D drain of the gallium nitride power device through NPN transistor Q3. The emitter of NPN transistor Q3 is connected to the negative input terminal of operational amplifier U1 through resistor R1. Specifically, the base of NPN transistor Q3 is connected to the output terminal of operational amplifier U1, the collector of NPN transistor Q3 is connected to VCC, and the emitter of NPN transistor Q3 is connected to the D drain of the gallium nitride power device. The negative input terminal of operational amplifier U1 is connected to the reference voltage signal V3 through resistor R2. The positive input terminal of operational amplifier U2 is connected to the source of the gallium nitride power device. The negative input terminal of operational amplifier U2 is connected to the output terminal of operational amplifier U2. The output terminal of operational amplifier U2 is connected to the negative input terminal of operational amplifier U4 through resistor R4. The negative input terminal of operational amplifier U4 is connected to the output terminal of operational amplifier U2 through resistor R4. The positive input terminal of operational amplifier U4 is grounded. It can be seen that the voltage control circuit includes operational amplifier U2, resistor R4, resistor R5, operational amplifier U4, resistor R1, resistor R2, resistor R3, the externally given reference voltage signal V3, operational amplifier U1, and NPN transistor Q3. The function of this circuit is to control the voltage difference Vds applied between the drain and source poles to be V3. Operational amplifier U2 is connected in a follower configuration, and its output voltage Uo2 = Us. Operational amplifier U4, resistor R4, and resistor R5 are connected in an inverter configuration. The resistance value of resistor R4 is equal to the resistance value of resistor R5, and its output voltage Uo4 = -Us. Operational amplifier U1, transistor Q3, and resistors R1 to R3 are connected in a reverse adder configuration. The resistance values of the three resistors R1 to R3 are equal, and its output voltage Ud = -V3 - Uo4 = Vlimit + Us. Therefore, Vds of the gallium nitride power device = Ud - Us = Vlimit.

[0031] The current detection circuit is connected to the gate of the gallium nitride power device to control the gate voltage and detect the gate current. The positive input terminal of the operational amplifier U3 in the current detection circuit is grounded, the negative input terminal of the operational amplifier U3 is connected to the gate of the gallium nitride power device, the negative input terminal of the operational amplifier U3 is connected to the current detection node Uo3 through the resistor R6, and a capacitor C1 is connected in parallel at both ends of the resistor R6. For the gate voltage control and gate current Ig detection circuit of the gallium nitride power device, due to the "virtual short" characteristics of the positive and negative inputs of the operational amplifier U3, the potential of the gate Ug of GaN is GND. In addition, the node Uo3 / R6 = the current Ig flowing into the gate of GaN (which can be understood as the gate leakage current of the GaN device - this parameter is also an important electrical parameter of gallium nitride). This circuit can synchronously test the chips with large gate leakage current of GaN. It should be noted that after the circuit is stable, the source voltage is negative to ensure that GaN is in the on state.

[0032] Such as Figure 4 The current source circuit shown, the current source circuit is connected to the source of the gallium nitride power device to control the current flowing through the drain. The current source circuit includes an operational amplifier Ua, an operational amplifier Ub, and a triode Q1; the positive input terminal of the operational amplifier Ua is connected to the reference voltage V1 through the resistor Rf2, the negative input terminal of the operational amplifier Ua is grounded through the resistor Rf1, the output terminal of the operational amplifier Ua is connected to the base of the PNP triode Q1 through the resistor Rb, the emitter of Q1 is connected to one end Vp of the current detection resistor Rcs, and the other end Vn of the current detection resistor Rcs is connected to the source of the gallium nitride power device; at the same time, Vn is connected to the positive input terminal of the operational amplifier Ub, the negative input terminal of the operational amplifier Ub is connected to the output terminal of the operational amplifier Ub, and the output terminal of the operational amplifier Ub is connected to the positive input terminal of the operational amplifier Ua through the resistor Rf4.

[0033] When the current source extracts 1A current from the S pole (source) of the gallium nitride power device, the potential of the Us node will decrease. When Us < Ug of the gallium nitride power device and their difference reaches the turn-on voltage, the current Id flows from VCC through Q3 into the GaN device. If the turn-on force of the gallium nitride power device is insufficient and Id < I2, the potential of Us will continue to decrease, and the value of Ug - Us will increase, thereby ensuring an increase in the turn-on force of the gallium nitride power device until Id = I2. When external interference or fluctuations in the power supply VCC cause Id to be greater than I2, the potential of Us will be raised by Id, reducing the value of Ug - Us, and the turn-on force of GaN will weaken until Id = I2. This part of the circuit is automatically balanced.

[0034] By controlling the voltage value of the reference voltage V1, the value of the inflowing Id current can be controlled.

[0035] The N-terminal input voltage of the operational amplifier Ua:

[0036] UN = Vp * Rf1 / (Rf1 + Rf3);

[0037] Since Ubo = Vn, according to the circuit superposition theorem, the input voltage at the P terminal of the operational amplifier Ua:

[0038] UP = Vn * Rf2 / (Rf2 + Rf4) + V1 * Rf4 / (Rf2 + Rf4);

[0039] The resistance values of the four resistors Rf1 to Rf4 in the circuit are equal. When the circuit is balanced, UN = UP, and we can get:

[0040] Vp = Vn + V1;

[0041] The current Id flows from the right end to the left end of Rcs, so we can get: -V1 = Vn - Vp;

[0042] Therefore, Id = -V1 / Rcs. By giving the reference voltage V1, the current value flowing into the Id node can be determined.

[0043] The operational amplifiers Ua and Ub are of the type with low input offset voltage and low input offset current to ensure the constant current accuracy of Id.

[0044] In summary, the specific differences between the proposed solution in this article and the existing solutions are as follows: The test current Id of the tester is 1A, which is 1 / 10 times the original current value; the tester gives Vds = Vds_Limit (3V is taken in this embodiment); the tester controls the given value of the gate-source voltage difference VGS of GaN according to the constant Id value (due to the inconsistent saturation characteristics of different chips, the stable voltage value of VGS is different). When the test system is in a steady state, when the current Id flowing into the D pole of GaN is 1A and Vds = Vds_Limit, the higher the GT voltage value, the more saturated the device will be during actual application.

[0045] The test steps are as follows:

[0046] According to Figure 1 the connection relationship, connect the GaN device to the tester reliably. The current flowing through the drain and source of GaN is relatively large, and relatively thick wires are required for the relevant connection points. Referring to Figure 3 the control method of Vds in, the tester gives the amplitude of V3 = Vds_Limit (3V is taken). Since U1 is connected as an inverting adder, the phase of V3 should be 180 degrees, that is, V3 = Vds_Limit * sin(180°) = -3V. Thus, Vds can be controlled to 3V to ensure that the GaN to be tested is in the saturation mode. Control the Vds voltage of the GaN device to 3V, condition a.

[0047] Control the gate-source voltage difference of the GaN device to be tested to be greater than the turn-on voltage Vth of the device:Figure 3 The current source I2 in Figure 3 extracts current from the source of the GaN, forcing the source potential to be lower than the gate. The direction of I2 is from top to bottom, that is Figure 4 In Figure 4 , the current flows from the right end to the left end of Rcs. Therefore, the control machine should give V1 a negative voltage. When V1 = -1V and Rcs is 1 ohm, the value of I2 is 1A. Since the gate current of the GaN device is extremely small (a few μA), most of this 1A current flows through the drain of the GaN. It can be known that this current comes from the emitter of Q3. Therefore, the power supply VCC connected to the collector of Q3 requires a driving ability of more than 1A. Control the current flowing through the drain of the GaN = 1A, condition b.

[0048] Hardware principle Figure 4 After U3 in Figure 4 stabilizes, the positive and negative input pins have the characteristic of virtual short. Therefore, the potential of Ug is also GND. The current Ig flowing into the gate of the GaN is calculated through Uo3. At this time, the GaN is already turned on, and the source voltage is negative. Control the gate-source voltage of the GaN to make it in the saturation conduction state, condition c.

[0049] The above three steps have satisfied the three elements of the improved test method proposed in this article. Test and record the Vgs voltage in step c. When this value is greater than the specified threshold, it is judged that the current test chip is a failed chip.

[0050] The advantages of this patent are reflected by comparing experimental data below. (Taking the GaN with a rated current of 5A as an example, conduct experimental tests and verifications according to the method mentioned above and compare with the test results of the existing method.)

[0051] Table 1 below is a comparison table of data tests based on the existing GaN saturation current test method and data tests based on the improved test method proposed in this article. The second column in Table 1 is the data test based on the existing GaN saturation current test method. The test machine controls the gate voltage = 6V, injects a drain current = 10A, and tests the Vds voltage at balance. If it exceeds 6.5V, it is judged as saturated, and the 7# chip is a non-conforming product. The third column in Table 1 is the data test based on the improved test method proposed in this article. Extract 1A current from the source of the GaN, control the drain-source voltage difference Vds, and test the GT voltage value at stability. An additional advantage of this method is that it can test the gate leakage current.

[0052] Table 1

[0053]

[0054] Test the same 10 GaN chips with two test methods. The data is as follows in the table and two histograms, as Figure 5 and Figure 6As shown, it can be seen from the histogram distribution that No. 7 is an abnormal chip, and both methods can detect it. The saturation trends of other chips are also basically the same. However, it should be noted that the method proposed in this paper is more indirect, time-saving, and environmentally friendly. Since the current used in the test is smaller, the test is more stable and causes less stress on the test equipment; compared with the existing method, it is more suitable for the in-line testing stage of wafers.

[0055] In summary, the saturation current test scheme of the GaN device in this patent has obvious advantages compared with the existing technology. First of all, the test time of the present invention is short and there is no device heating. Therefore, it can quickly and accurately test the saturation characteristics of the GaN device, and the saturation characteristics at high-temperature operation can be deduced from the test results at room temperature, improving the test accuracy.

[0056] Secondly, since basically no heat is generated during the whole test process, the test accuracy and stability are guaranteed. Compared with the existing technology, the test process of this scheme will not cause device heating, so the probability of problems occurring at the gold finger contact points can be reduced, and the maintenance cost of the test equipment is reduced. In addition, the test method proposed in this paper is also applicable to the test after product packaging, improving the flexibility and applicability of the test.

[0057] In addition, the second part of this test circuit can simultaneously test the gate leakage current of the GaN device, screening out the chips with relatively large gate leakage current, effectively improving the ex-factory quality of the product.

[0058] The above embodiments are not limitations to the present utility model, and the present utility model is not limited to the above examples either. Changes, modifications, additions or substitutions made by those skilled in the art within the technical solution scope of the present utility model also fall within the protection scope of the present utility model.

Claims

1. A test circuit for the saturation characteristics of a gallium nitride power device, characterized in that, Comprising: A gallium nitride power device; A voltage control circuit connected between the drain and source of the gallium nitride power device to control the voltage difference output between the two poles; A current detection circuit connected to the gate of the gallium nitride power device to control the gate voltage and detect the gate current; A current source circuit connected to the source of the gallium nitride power device to control the current flowing through the drain.

2. The gallium nitride power device saturation characteristic test circuit according to claim 1, wherein: The voltage control circuit includes operational amplifiers U1, U2, and U4; The positive input terminal of operational amplifier U1 is grounded. The negative input terminal of operational amplifier U1 is connected to the output terminal of operational amplifier U4 through resistor R3. The output terminal of operational amplifier U1 is connected to the D drain of the gallium nitride power device through NPN transistor Q3. The emitter of NPN transistor Q3 is connected to the negative input terminal of operational amplifier U1 through resistor R1. The negative input terminal of operational amplifier U1 is connected to the reference voltage signal V3 through resistor R2. The positive input terminal of operational amplifier U2 is connected to the source of the gallium nitride power device. The negative input terminal of operational amplifier U2 is connected to the output terminal of operational amplifier U2. The output terminal of operational amplifier U2 is connected to the negative input terminal of operational amplifier U4 through resistor R4. The negative input terminal of operational amplifier U4 is connected to the output terminal of operational amplifier U2 through resistor R4. The positive input terminal of operational amplifier U4 is grounded.

3. The gallium nitride power device saturation characteristic test circuit according to claim 2, wherein: The base of the NPN transistor Q3 is connected to the output terminal of the operational amplifier U1, and the collector of the NPN transistor Q3 is connected to VCC , and the emitter of the NPN transistor Q3 is connected to the D drain of the gallium nitride power device.

4. The gallium nitride power device saturation characteristic test circuit according to claim 3, wherein: The current source circuit includes operational amplifiers Ua, Ub, and transistor Q1; The positive input terminal of operational amplifier Ua is connected to reference voltage V1 through resistor Rf2. The negative input terminal of operational amplifier Ua is grounded through resistor Rf1. The output terminal of operational amplifier Ua is connected to the base of PNP transistor Q1 after passing through resistor Rb. The emitter of Q1 is connected to one end Vp of the current detection resistor Rcs. The other end Vn of the current detection resistor Rcs is connected to the source of the gallium nitride power device. At the same time, Vn is connected to the positive input terminal of operational amplifier Ub. The negative input terminal of operational amplifier Ub is connected to the output terminal of operational amplifier Ub. The output terminal of operational amplifier Ub is connected to the positive input terminal of operational amplifier Ua through resistor Rf4.

5. The gallium nitride power device saturation characteristic test circuit according to claim 4, wherein: The positive input terminal of operational amplifier U3 of the current detection circuit is grounded. The negative input terminal of operational amplifier U3 is connected to the gate of the gallium nitride power device. The negative input terminal of operational amplifier U3 is connected to the current detection node Uo3 through resistor R6. A capacitor C1 is connected in parallel across both ends of resistor R6.

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