Layout frame structure
By dividing the cutting path area into peripheral cutting path and inner peripheral cutting path, the cutting path layout is optimized, and the problem of large occupancy area and low utilization rate of the cutting path is solved, and higher chip output and cutting path utilization rate are achieved.
Patent Information
- Application Number
- CN202422038439.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-08-21
AI Technical Summary
In the prior art, the cutting path with a width of 30 μm cannot meet the marking pattern size requirements, and the cutting path occupies a large area and has low utilization rate.
The cutting path area is divided into peripheral cutting paths and inner peripheral cutting paths. The peripheral cutting path is used as the overlapping exposure area of adjacent exposure units, the inner peripheral cutting path is used as the non-repeat exposure area, and the test patterns are placed in the inner peripheral cutting path, and the overlapping patterns and blocks are placed in the peripheral cutting path to optimize the layout of the cutting path.
The overlapping exposure areas of the cutting path are reduced, the utilization rate of the cutting path is improved, the number of effective chips in each exposure unit is increased, and the occupied area of the cutting path is reduced.
Smart Images
Figure CN223092289U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a layout frame structure. Background Art
[0002] To meet customer requirements, it is necessary to reduce the width of the scribe lane in the frame (layout frame) (for example, reduce it to 30 μm) to increase the chip output. However, a scribe lane with a width of 30 μm cannot meet the size requirements of each marking pattern. To solve this problem, usually, the outermost chips in the chip area 1 of the exposure unit (shot) are used as the scribe lane 2 and are used to place each marking pattern 22. For example, the scribe lane 2 extends to 330 μm above, below, left, and right of the chip area 1 (as Figure 1 shown). And the scribe lane 2, as the overlap area of adjacent exposure units, will be exposed twice during exposure. Therefore, it is necessary to set a marking pattern in one side of the scribe lane 2 in the chip area 1 (for example, above the chip area 1 of the scribe lane 2), and design a blocking block 21 at the corresponding position on the other side of the chip area 1 (for example, below the chip area 1 of the scribe lane 2) to ensure that the marking pattern 22 is correct at the same position of the exposure unit during exposure (that is, there will be no errors such as staggered marking patterns), as specifically shown in Figure 2 shown. However, this scribe lane occupies a large area and has a low actual utilization rate. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a layout frame structure, which can reduce the area occupied by the scribe lane and improve the utilization rate of the scribe lane.
[0004] To solve the above problems, the utility model provides a layout frame structure, which has a scribe lane area and a chip area. The scribe lane area is arranged outside the chip area. The scribe lane area includes an outer scribe lane and an inner scribe lane. The outer scribe lane and the inner scribe lane are sequentially arranged outside the chip area. Among them, the outer scribe lane serves as the overlapping exposure area of adjacent exposure units during exposure.
[0005] Optionally, the inner scribe lane is arranged in a ring outside the chip area.
[0006] Furthermore, the widths of the inner scribe lane and the outer scribe lane outside the chip area are respectively:
[0007] a = [(1pitch + 1A) - b] / 2;
[0008] a = c;
[0009] b = d;
[0010] Among them, a is the width of the inner peripheral cutting channel in the transverse direction; b is the width of the outer peripheral cutting channel in the transverse direction; A is the design requirement value of the dicing slot; pitch is the distance between the center lines of the line widths of each chip pattern and the center lines of the line widths of adjacent chip patterns; c is the width of the inner peripheral cutting channel in the longitudinal direction; d is the width of the outer peripheral cutting channel in the longitudinal direction.
[0011] Optionally, the outside of the chip area has an upper side and a lower side that are oppositely arranged and a left side and a right side that are oppositely arranged. The inner peripheral cutting channel is located on the upper side and the lower side of the chip area, or on the left side and the right side of the chip area.
[0012] Furthermore, when the inner peripheral cutting channel is located on the upper side and the lower side of the chip area, the widths of the inner peripheral cutting channel and the outer peripheral cutting channel on the outside of the chip area are respectively:
[0013] a = [(1pitch + 1A) - b] / 2;
[0014] Among them, a is the width of the inner peripheral cutting channel in the transverse direction; b is the width of the outer peripheral cutting channel in the transverse direction; A is the design requirement value of the dicing slot; pitch is the distance between the center lines of the line widths of each chip pattern and the center lines of the line widths of adjacent chip patterns.
[0015] Furthermore, the width of the outer peripheral cutting channel in the transverse direction is less than the width of the outer peripheral cutting channel in the longitudinal direction.
[0016] Furthermore, when the inner peripheral cutting channel is located on the left side and the right side of the chip area, the widths of the inner peripheral cutting channel and the outer peripheral cutting channel on the outside of the chip area are respectively:
[0017] c = [(1pitch + 1A) - d] / 2;
[0018] Among them, c is the width of the inner peripheral cutting channel in the longitudinal direction; d is the width of the outer peripheral cutting channel in the longitudinal direction; A is the design requirement value of the dicing slot, and pitch is the distance between the center lines of the line widths of each chip pattern and the center lines of the line widths of adjacent chip patterns.
[0019] Furthermore, the width of the outer peripheral cutting channel in the longitudinal direction is less than the width of the outer peripheral cutting channel in the transverse direction.
[0020] Furthermore, a cutting channel pattern is placed in the cutting channel area. The cutting channel pattern includes an overlapping pattern and a test pattern. The overlapping pattern is placed in the outer peripheral cutting channel, and the test pattern is placed in the inner peripheral cutting channel.
[0021] Further, a shielding block is also placed in the peripheral cutting channel, and all the shielding blocks are respectively placed on the upper side, lower side, left side and right side of the chip area, and the shielding blocks on each side are correspondingly arranged with the overlapping patterns on the corresponding side.
[0022] Compared with the prior art, the utility model has the following beneficial effects:
[0023] The utility model provides a layout frame structure, which has a cutting channel area and a chip area. The cutting channel area is arranged outside the chip area. The cutting channel area includes a peripheral cutting channel and an inner cutting channel. The peripheral cutting channel and the inner cutting channel are sequentially arranged outside the chip area. Among them, the peripheral cutting channel serves as an overlapping exposure area of adjacent exposure units during exposure. By dividing the cutting channel area into a peripheral cutting channel for repeated exposure of adjacent exposure units during exposure and an inner cutting channel for placing test patterns in a non-repeated exposure area during exposure, the repeated exposure area of adjacent exposure units is reduced, so that the effective area of the chip area can be increased, thereby increasing the number of effective chips in each exposure unit, reducing the occupied area of the cutting channel, and improving the utilization rate of the cutting channel. Description of the Drawings
[0024] Figure 1 - Figure 2 It is a schematic structural diagram of a layout frame structure in the prior art.
[0025] Figure 3 - Figure 4 It is a schematic structural diagram of a layout frame structure provided in Embodiment 1 of the utility model.
[0026] Figure 5 - Figure 6 It is a schematic structural diagram of a layout frame structure provided in Embodiment 2 of the utility model.
[0027] Description of the Reference Numerals:
[0028] 1 - Chip area; 2 - Cutting channel; 21 - Shielding block; 22 - Marking pattern;
[0029] 100 - Chip area; 210 - Inner cutting channel; 211 - Test pattern; 220 - Peripheral cutting channel; 221 - Overlapping pattern; 222 - Shielding block. Detailed Embodiments
[0030] The following will further describe in detail a layout frame structure of the utility model. The utility model will be described in more detail with reference to the drawings, in which the preferred embodiments of the utility model are shown. It should be understood that those skilled in the art can modify the utility model described herein and still achieve the beneficial effects of the utility model. Therefore, the following description should be understood as a broad guidance for those skilled in the art and not as a limitation to the utility model.
[0031] For clarity, not all features of the actual embodiments will be described. In the following description, well-known functions and structures will not be described in detail, because they would obscure the present utility model with unnecessary details. It should be recognized that in the development of any actual embodiment, numerous implementation details must be made to achieve the specific goals of the developer, such as changing from one embodiment to another in accordance with system-related or business-related constraints. Additionally, it should be recognized that such development work may be complex and time-consuming, but is only routine work for those skilled in the art.
[0032] To make the objectives and features of the present utility model more obvious and understandable, the following further describes the specific implementation manners of the present utility model with reference to the accompanying drawings. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, only for the convenience of clearly assisting in explaining the objectives of the embodiments of the present utility model.
[0033] This embodiment provides a layout frame structure, which has a dicing street area and a chip area. The dicing street area is arranged outside the chip area. The outside of the chip area has an upper side and a lower side arranged oppositely and a left side and a right side arranged oppositely. The dicing street area includes an outer dicing street 220 and an inner dicing street 210. The outer dicing street 220 and the inner dicing street 210 are sequentially arranged outside the chip area, such that the inner dicing street 210 is located between the outer dicing street 220 and the chip area, and the inner dicing street 210 is located on the upper side and the lower side of the chip area, and / or on the left side and the right side of the chip area. Among them, the outer dicing street 220 serves as an overlapping exposure area of adjacent exposure units during exposure.
[0034] In this embodiment, by dividing the dicing street area into the outer dicing street 220 for repeated exposure of adjacent exposure units during exposure and the inner dicing street 210 for non-repeated exposure areas during exposure and placing test patterns, the repeated exposure area of adjacent exposure units is reduced. In this way, the effective area of the chip area can be increased, thereby increasing the number of effective chips in each exposure unit, reducing the occupied area of the dicing street, and improving the utilization rate of the dicing street.
[0035] Embodiment 1
[0036] As Figure 3 - Figure 4As shown, the layout frame structure has a chip area 100 where chips are placed in an array distribution, and the spacing between adjacent chips is fixed, for example, 30 μm. The chip area 100 is, for example, rectangular in shape, so the chip area 100 includes an upper side, a lower side, a left side, and a right side on the outer sides of the four sides. Among them, the upper side and the lower side are oppositely arranged, and the direction extending from the upper side to the lower side is the longitudinal direction. The left side and the right side are oppositely arranged, and the direction extending along the left side and the right side is the transverse direction. Chip patterns (each chip pattern is all the patterns forming a chip) are arranged in the chip area 100, and the spacing between the line width centerlines of adjacent chip patterns is fixed.
[0037] The layout frame structure has a scribe lane area for placing scribe lane patterns. The scribe lane patterns include overlay patterns and test patterns 211, and the test patterns 211 include patterns such as TSK (test key), CD bar, and AIM (advanced imaging metrology).
[0038] The scribe lane area includes an outer scribe lane 220 and an inner scribe lane 210. The shape of the outer scribe lane 220 is a rectangular ring, and the shapes of the inner scribe lanes 210 are all rectangular rings or two parallel rectangles.
[0039] To achieve two-way (i.e., transverse and longitudinal) scribe lane reduction, the inner scribe lane 210 is arranged in a ring outside the chip area 100, and the outer scribe lane 220 is arranged in a ring outside the inner scribe lane 210, and the shapes of the outer scribe lane 220 and the inner scribe lane 210 are both rectangular rings.
[0040] The width a of the inner scribe lane 210 in the transverse direction is equal to the width c of the inner scribe lane 210 in the longitudinal direction, that is, the inner scribe lane 210 is arranged with equal width around the chip area; the width b of the outer scribe lane 220 in the transverse direction is equal to the width d of the outer scribe lane 220 in the longitudinal direction, that is, the outer scribe lane 220 is arranged with equal width around the inner scribe lane 210.
[0041] At this time, the following formula is satisfied:
[0042] a = [(1pitch + 1A) - b] / 2;
[0043] a = c;
[0044] b = d;
[0045] Wherein, a is the width of the inner peripheral dicing channel 210 in the transverse direction; b is the width of the outer peripheral dicing channel 220 in the transverse direction; A is the design requirement value of the scribe line; pitch is the distance between the center lines of the line widths of each chip pattern and the adjacent chip pattern.
[0046] Taking 1 pitch as 300 μm and 1 A as 30 μm as an example, currently, the entire dicing channel outside the chip area 100 needs to be exposed with overlapping exposure during exposure. At this time, the width of the dicing channel area on each side of the chip area 100 needs to be 330 μm. In this embodiment, when it is defined that b≥50 μm and the specific value is, for example, 60 μm, the value of a can be calculated as 135 μm using the above formula. In this way, the width of the dicing channel on each side of the chip area 100 is 195 μm (i.e., 60 μm + 135 μm). Compared with the width of the dicing channel area in the prior art, which is 330 μm, it reduces the size of the overlapping exposure area, thereby greatly reducing the area occupied by the dicing channel area, improving the utilization rate of the exposure unit, and for example, 180 chips can be added in each exposure unit. It is also more suitable for the operation logic of the existing mask soft, reducing the program modification time, reducing the product outfeed cycle time, reducing the number and frequency of manually moving marks during the exposure process, reducing the MO (missoperate) probability, and meeting the detection standard to ensure that no abnormality occurs when the inspection machine inspects the wafer. It also enables the layout frame structure provided in this embodiment to be applicable not only to MCU chip products but also to driver chip products.
[0047] A plurality of overlay patterns and a plurality of block blocks are arranged in the outer peripheral dicing channel 220. All the block blocks 222 are respectively arranged on the upper side, lower side, left side, and right side of the chip area 100, and the block blocks 222 on each side are correspondingly arranged with the overlay patterns 221 on the corresponding side. For example, all the overlay patterns 221 in the outer peripheral dicing channel 220 on the upper side of the chip area 100 are correspondingly arranged with the block blocks 222 in the outer peripheral dicing channel 220 on the lower side of the chip area 100; all the overlay patterns 221 in the outer peripheral dicing channel 220 on the lower side of the chip area 100 are correspondingly arranged with the block blocks 222 in the outer peripheral dicing channel 220 on the upper side of the chip area 100; all the overlay patterns 221 in the outer peripheral dicing channel 220 on the left side of the chip area 100 are correspondingly arranged with the block blocks 222 in the outer peripheral dicing channel 220 on the right side of the chip area 100; all the overlay patterns 221 in the outer peripheral dicing channel 220 on the right side of the chip area 100 are correspondingly arranged with the block blocks 222 in the outer peripheral dicing channel 220 on the left side of the chip area 100.
[0048] A test pattern 211, such as a TSK (test key), CD bar, AIM, etc., is provided in the inner peripheral saw street 210. In this embodiment, by providing an overlapping pattern 221 in the outer peripheral saw street 220 and a test pattern 211 on the inner peripheral saw street 210, the exposed overlapping saw street area (i.e., the outer peripheral saw street 220) is greatly reduced. For example, the saw street area is reduced by 41%.
[0049] Embodiment 2
[0050] As Figure 5 - Figure 6 shown, compared with Embodiment 1, in order to achieve unidirectional (i.e., horizontal or vertical) saw street reduction, this embodiment provides a layout frame structure. The inner peripheral saw streets 210 are located on both sides of the chip area 100. For example, the inner peripheral saw streets 210 are located on the left and right sides of the chip area 100, or the inner peripheral saw streets 210 are located on the upper and lower sides of the chip area 100.
[0051] At this time, when achieving horizontal saw street reduction, the width c of the inner peripheral saw street 210 in the longitudinal direction takes a value of 0. The width b of the outer peripheral saw street 220 in the horizontal direction is less than the width of the outer peripheral saw street 220 in the longitudinal direction, and the width of the outer peripheral saw street 220 in the longitudinal direction remains the same as the width of the saw street in the prior art. For example, it is 330 μm, which is the width of the saw street on either side of the chip area in the prior art.
[0052] At this time, the following relationship is satisfied between the width a of the inner peripheral saw street 210 in the horizontal direction and the width b of the outer peripheral saw street 220 in the horizontal direction:
[0053] a = [(1pitch + 1A) - b] / 2;
[0054] where A is the design requirement value of the scribe line; pitch is the distance between the center lines of the line widths of each chip pattern and the adjacent chip pattern.
[0055] When achieving vertical saw street reduction, the width a of the inner peripheral saw street 210 in the horizontal direction takes a value of 0. The width d of the outer peripheral saw street 220 in the longitudinal direction is less than the width of the outer peripheral saw street 220 in the horizontal direction, and the width of the outer peripheral saw street 220 in the horizontal direction remains the same as the width of the saw street in the prior art. For example, it is 330 μm, which is the width of the saw street on either side of the chip area in the prior art.
[0056] At this time, the following relationship is satisfied between the width c of the inner peripheral saw street 210 in the longitudinal direction and the width d of the outer peripheral saw street 220 in the longitudinal direction:
[0057] c = [(1pitch + 1A) - d] / 2;
[0058] Wherein, A is the design requirement value of the scribe line, and pitch is the distance between the center lines of the line widths of each chip pattern and the adjacent chip pattern.
[0059] The reduction of the dicing lane in one direction in this embodiment can reduce the occupied area of the dicing lane and improve the utilization rate of the exposure unit.
[0060] A plurality of overlapping patterns 221 and a plurality of shielding blocks 222 are provided in the peripheral dicing lane 220. All the shielding blocks 222 are respectively placed on the upper side, lower side, left side and right side of the chip area 100, and the shielding blocks 222 on each side are correspondingly arranged with the overlapping patterns 221 on the corresponding side.
[0061] When realizing the horizontal reduction, test patterns 211 are provided in the inner peripheral dicing lanes 210 on the left side and the right side of the chip area 100; when realizing the vertical reduction, test patterns 211 are provided in the inner peripheral dicing lanes 210 on the upper side and the lower side of the chip area 100.
[0062] In summary, the present utility model provides a layout frame structure, which has a dicing lane area and a chip area. The dicing lane area is arranged outside the chip area. The dicing lane area includes a peripheral dicing lane and an inner peripheral dicing lane. The peripheral dicing lane and the inner peripheral dicing lane are sequentially arranged outside the chip area. Wherein, the peripheral dicing lane serves as an overlapping exposure area of adjacent exposure units during exposure; by dividing the dicing lane area into a peripheral dicing lane for repeated exposure of adjacent exposure units during exposure and an inner peripheral dicing lane for placing test patterns in a non-repeated exposure area during exposure, the repeated exposure area of adjacent exposure units is reduced, so that the effective area of the chip area can be increased, thereby increasing the number of effective chips in each exposure unit, reducing the occupied area of the dicing lane, and improving the utilization rate of the dicing lane.
[0063] In addition, it should be noted that unless otherwise specifically stated or indicated, the descriptions of the terms "first" and "second" in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.
[0064] It can be understood that although the present utility model has been disclosed above with the preferred embodiments, the above embodiments are not intended to limit the present utility model. For any person skilled in the art, without departing from the scope of the technical solution of the present utility model, many possible changes and modifications can be made to the technical solution of the present utility model by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present utility model without departing from the content of the technical solution of the present utility model still fall within the scope of protection of the technical solution of the present utility model.
Claims
1. A layout framework structure, characterized in that, It has a scribe lane region and a chip region. The scribe lane region is arranged outside the chip region. The scribe lane region includes an outer scribe lane and an inner scribe lane. The outer scribe lane and the inner scribe lane are sequentially arranged outside the chip region. Among them, the outer scribe lane serves as an overlapping exposure region of adjacent exposure units during exposure.
2. The layout frame structure according to claim 1, wherein The inner scribe lane is arranged in a ring outside the chip region.
3. The layout frame structure according to claim 2, characterized in that, The widths of the inner scribe lane and the outer scribe lane outside the chip region are respectively: a = [(1pitch + 1A) - b] / 2; a = c; b = d; Among them, a is the width of the inner scribe lane in the transverse direction; b is the width of the outer scribe lane in the transverse direction; A is the design requirement value of the dicing saw slot; pitch is the distance between the line width center lines of each chip pattern and the adjacent chip pattern; c is the width of the inner scribe lane in the longitudinal direction; d is the width of the outer scribe lane in the longitudinal direction.
4. The layout frame structure according to claim 1, wherein The outside of the chip region has an upper side and a lower side arranged opposite to each other and a left side and a right side arranged opposite to each other. The inner scribe lane is located on the upper side and the lower side of the chip region, or is located on the left side and the right side of the chip region.
5. The layout frame structure according to claim 4, characterized in that, When the inner scribe lane is located on the upper side and the lower side of the chip region, the widths of the inner scribe lane and the outer scribe lane outside the chip region are respectively: a = [(1pitch + 1A) - b] / 2; Among them, a is the width of the inner scribe lane in the transverse direction; b is the width of the outer scribe lane in the transverse direction; A is the design requirement value of the dicing saw slot; pitch is the distance between the line width center lines of each chip pattern and the adjacent chip pattern.
6. The layout frame structure according to claim 5, wherein, The width of the outer scribe lane in the transverse direction is less than the width of the outer scribe lane in the longitudinal direction.
7. The layout frame structure according to claim 4, wherein When the inner scribe lane is located on the left side and the right side of the chip region, the widths of the inner scribe lane and the outer scribe lane outside the chip region are respectively: c = [(1pitch + 1A) - d] / 2; Among them, c is the width of the inner scribe lane in the longitudinal direction; d is the width of the outer scribe lane in the longitudinal direction; A is the design requirement value of the dicing saw slot, and pitch is the distance between the line width center lines of each chip pattern and the adjacent chip pattern.
8. The layout frame structure according to claim 7, characterized in that, The width of the outer scribe lane in the longitudinal direction is less than the width of the outer scribe lane in the transverse direction.
9. The layout frame structure according to claim 4, characterized in that, A scribe lane pattern is placed in the scribe lane region. The scribe lane pattern includes an overlapping pattern and a test pattern. The overlapping pattern is placed in the outer scribe lane, and the test pattern is placed in the inner scribe lane.
10. The layout frame structure according to claim 9, characterized in that, Blocking blocks are also placed in the outer scribe lane. All the blocking blocks are respectively placed on the upper side, the lower side, the left side and the right side of the chip region, and the blocking blocks on each side are correspondingly arranged with the overlapping patterns on the corresponding side.