Signal processing device

Abstract

The utility model belongs to the technical field of signal processing, and provides a signal processing device, which comprises an FPGA (field programmable gate array) logic processing unit, a DSP (digital signal processor) signal processing unit, a DAC (digital to analog converter) module, an ADC (analog to digital converter) module and a clock unit. The DSP signal processing unit is electrically connected with the FPGA logic processing unit and is used for receiving and processing data of the FPGA logic processing unit; the DAC module is used for performing digital-to-analog conversion on the transmitted signal; the ADC module is used for performing analog-to-digital conversion on the received intermediate frequency signal; the clock unit is used for providing clock signals for the FPGA logic processing unit, the DAC module and the ADC module. The FPGA logic processing unit is matched with the DSP signal processing unit, and a signal processing part and a data processing part are integrated, so that the functions of the two parts can be realized on the basis of one board card, the requirement of equipment integration is met, and the management complexity is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of signal processing, and particularly relates to a signal processing device. Background Art

[0002] The new navigation system consists of four parts: communication (C), navigation (N), surveillance (S), and air traffic management (ATM). Among them, the surveillance system mainly includes secondary surveillance radar (SSR) in A / C mode or S mode, and automatic dependent surveillance - broadcast (ADS - B). With the development of China's social economy, the number and scale of domestic civil aviation airports have been continuously expanding, and the number of aircraft has also been growing rapidly. The demand for airport surface surveillance and en - route surveillance has increased significantly, and the requirements for secondary surveillance radar and automatic dependent surveillance - broadcast equipment and their reliability have become higher and higher. Secondary surveillance radar and automatic dependent surveillance - broadcast equipment are not only used in civil aviation but also installed on military primary radars. The military primary radars include fixed radar stations, vehicle - mounted radars, and portable radars. These primary radars have strict requirements for the volume and weight of secondary surveillance radar and automatic dependent surveillance - broadcast equipment, and there is a need for an integrated design of secondary surveillance radar and automatic dependent surveillance - broadcast equipment to reduce volume and weight, and at the same time, the supply needs to be stable and reliable.

[0003] The current signal processing device processes data processing and signal processing on two separate circuit boards respectively, which cannot meet the requirements of equipment integrated design, and at the same time causes problems such as high cost and complex management. Summary of the Utility Model

[0004] Aiming at the defects in the prior art, the signal processing device provided by the utility model divides data processing and signal processing into two circuit boards for separate processing, resulting in problems of high cost and complex management.

[0005] The signal processing device provided by the utility model includes:

[0006] An FPGA logic processing unit, configured to process the received signal;

[0007] A DSP signal processing unit, electrically connected to the FPGA logic processing unit, configured to receive the data from the FPGA logic processing unit and process it;

[0008] A DAC module, electrically connected to the FPGA logic processing unit, configured to perform digital - to - analog conversion on the transmitted signal;

[0009] An ADC module, electrically connected to the FPGA logic processing unit, configured to perform analog - to - digital conversion on the received intermediate - frequency signal;

[0010] A clock unit, configured to provide clock signals for the FPGA logic processing unit, the DAC module, and the ADC module.

[0011] As can be seen from the above technical solutions, the signal processing device provided by the present utility model integrates signal processing and data processing by cooperating with the FPGA logic processing unit and the DSP signal processing unit, so that these two functions can be realized based on one board, meeting the requirements of device integration and reducing the management complexity.

[0012] Optionally, an EMIF bus interface, an SRIO x4 high-speed serial interface, and an SPI&UART low-speed interface are connected between the FPGA logic processing unit and the DSP signal processing unit.

[0013] Optionally, it further includes a connector. The connector is provided with an intermediate frequency signal receiving port, an intermediate frequency transmitting port, and a clock input port. The intermediate frequency signal receiving port is connected to the ADC module, the intermediate frequency transmitting port is connected to the DAC module, and the clock input port is connected to the FPGA logic processing unit.

[0014] Optionally, the clock unit includes a clock management chip. The clock management chip is connected to a 100M externally supplied clock through the clock input port, and the clock management chip provides clocks for the FPGA logic processing unit, the ADC module, and the DAC module respectively.

[0015] Optionally, the connector is further provided with an external data interaction interface and a TTL control interface.

[0016] The external data interaction interface is connected to an interface chip, and is connected to the FPGA logic processing unit through the interface chip. The interface chip includes an RS422 interface chip, an RS485 interface chip, and an RS232 interface chip.

[0017] The TTL control interface is connected to a level conversion chip, and is connected to the FPGA logic processing unit through the level conversion chip.

[0018] Optionally, the connector is further provided with a power interface. The power interface is connected to a controller chip, and the controller chip is used to implement power-on management and reset.

[0019] Adopting the above technical solutions, the present application has the following technical effects:

[0020] The signal processing device provided by the present utility model integrates signal processing and data processing by cooperating with the FPGA logic processing unit and the DSP signal processing unit, so that these two functions can be realized based on one board, meeting the requirements of device integration and reducing the management complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0022] Figure 1 Schematic diagram of the signal processing device provided by the embodiment of the present invention. Specific embodiments

[0023] The following will describe in detail the embodiments of the technical solutions of the present invention with reference to the drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, so they are only examples and cannot be used to limit the protection scope of the present invention.

[0024] It should be noted that unless otherwise specified, the technical terms or scientific terms used in this application should have the ordinary meanings understood by those skilled in the art to which the present invention belongs.

[0025] As Figure 1 shown, this embodiment provides a signal processing device, including an FPGA logic processing unit, a DSP signal processing unit, a DAC module, an ADC module, and a clock unit. The FPGA logic processing unit is used to process the received signal; the DSP signal processing unit is electrically connected to the FPGA logic processing unit and is used to receive and process the data of the FPGA logic processing unit; the DAC module is electrically connected to the FPGA logic processing unit and is used to perform digital-to-analog conversion on the transmitted signal; the ADC module is electrically connected to the FPGA logic processing unit and is used to perform analog-to-digital conversion on the received intermediate-frequency signal; the clock unit is used to provide clock signals for the FPGA logic processing unit, the DAC module, and the ADC module.

[0026] In this embodiment, through the cooperation of the FPGA logic processing unit and the DSP signal processing unit, the signal processing and data processing parts are integrated and set, so that these two functions can be realized based on one board, meeting the requirements of equipment integration and reducing the management complexity.

[0027] Optionally, an FPGA logic processing unit selects a JFM7VX690T20 to implement the digital processing of the intermediate-frequency input signals of 4 ADC channels. The implementation method is to digitally process the 4-channel data collected by two ADCs through the JFM7VX690T20 and connect it to the DSP signal processing unit through the SRIO / EMIF interface. The DSP signal processing unit performs calculations on the received data and outputs the calculation results through the network port. The DSP signal processing unit selects an 8-core processor FT-M6678N as the calculation unit. The DSP signal processing unit receives the collected data sent by the FPGA logic processing unit and performs demodulation and calculation according to the application. A path of EMIF bus interface is connected between the DSP signal processing unit and the FPGA logic processing unit as the main data transmission interface. At the same time, a SRIO x4 high-speed serial interface and a SPI&UART low-speed interface are reserved between the DSP signal processing unit and the FPGA logic processing unit, and a 100M network interface is provided for transmitting the demodulated and calculated data.

[0028] As Figure 1 shown, an EMIF bus interface, a SRIO x4 high-speed serial interface and a SPI&UART low-speed interface are connected between the FPGA logic processing unit and the DSP signal processing unit. As Figure 1 shown, the communication interfaces between the DSP signal processing unit and the FPGA logic processing unit mainly include a 16-bit EMIF bus parallel data exchange bus, a 1-path SRIO x4 high-speed serial bus, a 1-path SPI and a 1-path UART serial port.

[0029] Optionally, 4 DDR3 SDRAMs are externally connected to the DSP signal processing unit, and the memory capacity of each DDR3 SDRAM is 2GB; specifically, the DDR3 SDRAM chip of model SM41J256M16M is selected. A 256Mb NOR Flash is also externally connected to the DSP signal processing unit for program solidification and parameter storage; specifically, the NOR Flash chip of model JFM29GL256-ES is selected.

[0030] In a specific embodiment, two JAD9268 chips are selected for the ADC module to implement four-channel analog-to-digital conversion. Selecting this model for the ADC module allows for in-situ replacement with the AD9268 from Analog Devices, Inc. The JAD9268 is a dual-channel, 16-bit ADC conversion chip with a maximum sampling rate of 125 MSPS. It has high performance, extremely low jitter that allows undersampling to achieve very good noise performance, and is very suitable for applications in the communication field. The chip is powered by a single 1.8V power supply, with a maximum power consumption of 750 mW. It has selectable input ranges of 1 Vp-p or 2 Vp-p, a full-power bandwidth of 650 MHz, and a 64-pin LFCSP package. Four-channel analog signals are input, and after front-end processing, they are sent to the analog input of the ADC module for sampling. The output digital signals are connected to the FPGA logic processing unit through a multi-channel LVDS interface. The FPGA logic processing unit completes data reception at the back end of the ADC module and performs preprocessing or transmission. The SPI of the ADC module is mainly used to configure the working mode of the ADC. The clock of the ADC supports internal and external clock modes.

[0031] Two SDA9739K chips are selected for the DAC module to implement four-channel digital-to-analog conversion. Selecting this model enables in-situ replacement with the AD9739 from Analog Devices, Inc. The SDA9739K is powered by 1.8V and 3.3V power supplies, and has a power consumption of only 1.16W when operating at 2.5 GSPS. The input clocks of the two SDA9739K chips are provided by a clock distribution chip and sent to the SDA9739K through the differential signal CLK± pins. This clock drives the DAC in an 8x mode inside the DAC to minimize clock jitter.

[0032] Optionally, it further includes a connector. The connector is provided with an intermediate-frequency signal receiving port, an intermediate-frequency transmitting port, and a clock input port. The intermediate-frequency signal receiving port is connected to the ADC module, the intermediate-frequency transmitting port is connected to the DAC module, and the clock input port is connected to the FPGA logic processing unit.

[0033] Optionally, the clock unit includes a clock management chip. The clock management chip is connected to a 100M externally supplied clock through the clock input port, and the clock management chip provides clocks for the FPGA logic processing unit, the ADC module, and the DAC module respectively.

[0034] Specifically, the clock unit mainly consists of three parts. The first part is that the 100M externally supplied clock passes through the clock management chip Ⅰ to provide clocks for the FPGA logic processing unit, the ADC module, and the DAC module respectively. The second part is the 125M crystal oscillator clock, which provides a high-speed interface clock through the clock management chip Ⅱ. The third part is the 25M crystal oscillator clock, which mainly provides the DSP working clock and the network port clock.

[0035] In a specific embodiment, the model of the clock management chip in the first part is selected as GM4526C, and the model of the usage management chip in the second part is selected as GMD946C.

[0036] Optionally, the connector is further provided with an external data interaction interface and a TTL control interface. The external data interaction interface is connected to an interface chip, and is connected to the FPGA logic processing unit through the interface chip; the interface chip includes an RS422 interface chip, an RS485 interface chip, and an RS232 interface chip; the TTL control interface is connected to a level conversion chip, and is connected to the FPGA logic processing unit through the level conversion chip.

[0037] Specifically, the network interface is implemented using the B88E1111 chip; the RS422 interface chip is implemented using B26LV31TF and B26LV32TF; the RS485 interface chip is implemented using the SM3485 chip; the RS232 interface is implemented using MAX3232EUE+.

[0038] Optionally, the connector is further provided with a power interface, and the power interface is connected to a controller chip, which is used to implement power-on management and reset. The controller chip is selected as CS32F103CB.

[0039] To implement the functions of power-on management and reset, a single-chip microcomputer is selected for unified management, which is used to provide the power-on sequence and delay for the DSP signal processing unit, the FPGA logic processing unit, etc., and is also used to reset or control the state of the DSP signal processing unit and its peripherals. The model of the power-on management and reset module is CS32F103CB.

[0040] Based on the signal processing device provided in this embodiment, it can generate an interrogation signal in a corresponding format according to a user control instruction, perform encoding and modulation on the interrogation signal, and output an intermediate-frequency transmission excitation signal; receive the intermediate-frequency response signal processed by the receiver returned by the aircraft and complete processing such as demodulation, decoding, and data parsing, and at the same time complete the functions of ranging and angle measurement, and output aircraft target data.

[0041] In the description of the present invention, a large number of specific details are set forth. However, it can be understood that the embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered within the scope of the claims and the description of the present invention.

Claims

1. A signal processing device, characterized in that, Including: An FPGA logic processing unit for processing the received signals; A DSP signal processing unit electrically connected to the FPGA logic processing unit for receiving and processing the data of the FPGA logic processing unit; A DAC module electrically connected to the FPGA logic processing unit for performing digital-to-analog conversion on the transmitted signals; An ADC module electrically connected to the FPGA logic processing unit for performing analog-to-digital conversion on the received intermediate-frequency signals; A clock unit for providing clock signals to the FPGA logic processing unit, the DAC module, and the ADC module.

2. The signal processing device according to claim 1, wherein An EMIF bus interface, an SRIO x4 high-speed serial interface, and an SPI&UART low-speed interface are connected between the FPGA logic processing unit and the DSP signal processing unit.

3. The signal processing device according to claim 1, wherein It further includes a connector. The connector is provided with an intermediate-frequency signal receiving port, an intermediate-frequency transmitting port, and a clock input port. The intermediate-frequency signal receiving port is connected to the ADC module, the intermediate-frequency transmitting port is connected to the DAC module, and the clock input port is connected to the FPGA logic processing unit.

4. The signal processing device according to claim 3, wherein The clock unit includes a clock management chip. The clock management chip is connected to an external 100M clock through the clock input port, and the clock management chip provides clocks for the FPGA logic processing unit, the ADC module, and the DAC module respectively.

5. The signal processing device according to claim 3, characterized in that, The connector is further provided with an external data interaction interface and a TTL control interface. The external data interaction interface is connected to an interface chip and is connected to the FPGA logic processing unit through the interface chip. The interface chip includes an RS422 interface chip, an RS485 interface chip, and an RS232 interface chip. The TTL control interface is connected to a level conversion chip and is connected to the FPGA logic processing unit through the level conversion chip.

6. The signal processing device according to claim 5, characterized in that, The connector is further provided with a power interface. The power interface is connected to a controller chip, and the controller chip is used to implement power-on management and reset.

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