Internal insulation packaging structure

Abstract

The utility model provides an internal insulation packaging structure, the packaging structure comprises a heat conduction plate, a chip, a lead, a pin and a packaging layer, the heat conduction plate comprises a first metal layer, an insulation heat conduction layer and a second metal layer which are laminated, the first metal layer comprises at least one welding area, a first lead area and at least one second lead area, the welding area is communicated with the first lead area; the at least one chip is welded on the welding area; the plurality of leads are electrically connected with the chips needing to be interconnected and the second lead areas corresponding to the electrodes in the chips; the plurality of pins are electrically connected with the welding area and the second lead areas respectively; the packaging layer covers the chip, the lead, the first metal layer and the pin which are welded on the exposed surface of one end of the second lead area. According to the utility model, the packaging structure is improved, and the heat-conducting plate is used as the substrate for welding the chip, so that the heat dissipation performance and reliability of the packaging structure are improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of power device packaging, and relates to an internal insulation packaging structure. Background Art

[0002] In recent years, power devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs for short) and Insulated Gate Bipolar Transistors (IGBTs for short) have developed rapidly towards high power density. Their current-carrying capacity and voltage-carrying capacity have also been greatly improved. At the same time, as discrete devices composed of power devices, the requirements for voltage and current of a single transistor are also getting higher and higher. At the same time, the application environment has higher and higher requirements for packaging.

[0003] At present, when discrete devices are in use, it is usually necessary to add a metal heat sink on the back to improve the heat dissipation capacity of the discrete device. The metal heat sink is generally not insulated from the inside of the discrete device. Therefore, a ceramic sheet for improving heat dissipation needs to be added at the application end for insulation. At the same time, when adding the ceramic sheet, a thermal grease layer needs to be set on the surface of the ceramic sheet, which increases the thermal resistance of the system and the cost of the system, and its heat dissipation is limited. As Figure 1 shown, it includes a package body 01, pins 02, a thermal grease layer 03, a ceramic sheet 04, a heat sink 05, a PCB board 06 and a spacer 07. In addition, discrete devices are usually welded on a lead frame with uneven upper surfaces. When welding discrete devices containing multiple chips, multiple welds are required, which reduces the welding efficiency and assembly accuracy and affects the reliability of the packaging structure. At the same time, since the chips in the discrete device and between the chips and the lead frame are usually interconnected by bonding wires, and the area of the bonding leads in the lead frame is fixed and limited, the number of bonding leads in the bonding lead area is limited, which in turn limits the current-carrying capacity of the discrete device. And in order to ensure the electrical performance of the discrete device, green oil that blocks the solder from overflowing onto the leads during the process of welding the pins is usually provided between the leads and the pins in the discrete device, introducing secondary pollution and increasing the packaging cost.

[0004] Therefore, there is an urgent need to find an internal insulation packaging structure that reduces the packaging cost, improves the heat dissipation capacity, and ensures the reliability of the packaging structure. Summary of the Utility Model

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide an internal insulation packaging structure for solving the problems of high packaging cost, poor heat dissipation capacity and poor reliability of discrete devices in the prior art.

[0006] To achieve the above and other related objectives, the present utility model provides an internal insulation encapsulation structure, including:

[0007] A heat conduction plate, including a stacked first metal layer, an insulating heat conduction layer, and a second metal layer. The first metal layer includes at least one welding area, a first lead area, and at least one second lead area spaced apart from the welding area. The welding area is in communication with the first lead area;

[0008] At least one chip, welded to the side of the welding area facing away from the insulating heat conduction layer;

[0009] A plurality of leads, electrically connecting the chips to be interconnected and the respective second lead areas corresponding to the electrodes in the chips;

[0010] A plurality of pins, respectively electrically connected to the welding area and each of the second lead areas;

[0011] An encapsulation layer, covering the chips, the leads, the first metal layer, and the exposed surfaces of the pins welded to one end of the second lead areas.

[0012] Optionally, the chips include MOSFET chips, IGBT chips, FRD chips, JBS chips, SBD chips; the heat conduction plate includes DBC substrates, AMB substrates.

[0013] Optionally, the distance between the part of the pin protruding from the encapsulation layer and the surface of the heat conduction plate exposed by the encapsulation layer ranges from 2.0 mm to 3.5 mm.

[0014] Optionally, at least one groove is further provided between the area electrically connected to the lead and the area electrically connected to the pin in the same second lead area.

[0015] Optionally, the depth range of the groove is 20% to 50% of the thickness of the first metal layer.

[0016] Optionally, the first metal layer includes a plurality of welding areas. The leads also electrically connect the chips to be electrically connected and the first lead area, and the first lead area is spaced apart from the welding area where the chips are welded.

[0017] Optionally, at least one groove is further provided between the area where the lead is bonded in the first lead area and the welding area.

[0018] Optionally, a plurality of the pins are led out from the same side wall of the encapsulation layer, and at least one notch is provided in the side wall of the encapsulation layer where the plurality of pins are led out. The notch is located between adjacent two pins and opens on the surface of the side wall of the encapsulation layer where the pins are led out.

[0019] Optionally, a heat dissipation structure fixedly connected to the heat conduction plate is further provided on the surface of the heat conduction plate exposed by the encapsulation layer.

[0020] Optionally, a circuit board electrically connected to the end of the pin away from the encapsulation layer is further provided in the inner insulation encapsulation structure.

[0021] As described above, the inner insulation encapsulation structure of the present invention improves the encapsulation structure, uses a heat conduction plate as the substrate for soldering the chips in discrete devices, and the first lead area and the second lead area for bonding leads and soldering pins in the first metal layer of the heat conduction plate can be divided into larger sizes according to the needs of the functional circuit, so that the number of leads bonded in the first lead area and the second lead area is increased, and the current carrying capacity of the encapsulation structure is improved; by providing grooves in the second lead area between the lead and the pin and in the first lead area between the soldering area and the lead, the solder overflowing during the soldering process can be blocked from overflowing onto the lead, reducing the encapsulation cost, avoiding the secondary pollution introduced by setting up a solder mask layer, and at the same time ensuring the electrical performance of the encapsulation structure; the heat conduction plate is combined with the encapsulation layer and the distance between the part of the pin protruding from the encapsulation layer and the second metal layer is adjusted according to the application scenario requirements, so that when the heat dissipation structure is soldered to the back of the second metal layer, the creepage distance of the encapsulation structure in a high-voltage environment can also be ensured, improving the reliability of the encapsulation structure. In addition, by using the combination of the second metal layer and the insulating heat-conducting layer, the heat dissipation structure can be directly soldered to the second metal layer through a solder with a high thermal conductivity, reducing the thermal resistance of the system composed of the encapsulation structure and the heat dissipation structure, improving the heat dissipation capacity of the system, and reducing the encapsulation cost, having high industrial utilization value. Description of the Drawings

[0022] Figure 1 It shows a schematic structural diagram of a discrete device encapsulation structure.

[0023] Figure 2 It shows a top view of the inner insulation encapsulation structure of the present invention.

[0024] Figure 3 It shows a bottom view of the inner insulation encapsulation structure of the present invention.

[0025] Figure 4 It shows a schematic side structural diagram of the inner insulation encapsulation structure of the present invention.

[0026] Figures 5 to 17 It respectively shows schematic structural diagrams of different inner insulation encapsulation structures of the present invention.

[0027] Explanation of the Reference Numerals in the Drawings

[0028] 01 Encapsulation body

[0029] 02 Pin

[0030] 03 Thermal grease layer

[0031] 04 Ceramic sheet

[0032] 05 Radiator

[0033] 06 PCB board

[0034] 07 Spacer

[0035] 1 Heat conducting plate

[0036] 11 First metal layer

[0037] 12 Insulating and heat conducting layer

[0038] 13 Second metal layer

[0039] 14 Welding area

[0040] 15 First lead area

[0041] 16 Second lead area

[0042] 17 Groove

[0043] 2 Chip

[0044] 3 Lead

[0045] 4 Pin

[0046] 5 Encapsulation layer

[0047] 51 Notch

[0048] 6 Heat dissipation structure

[0049] 7 Circuit board

[0050] 71 Support layer Detailed implementation manners

[0051] The following uses specific specific examples to illustrate the implementation manners of the present utility model. Those skilled in the art can easily understand other advantages and effects of the present utility model from the content disclosed in this specification. The present utility model can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present utility model.

[0052] Please refer to Figures 2 to 17 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present utility model in a schematic manner. Therefore, only the components related to the present utility model are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0053] This embodiment provides an internal insulation encapsulation structure, as Figure 2 , Figure 3 , Figure 4 and Figures 5 to 17 shown, which are respectively the top view of the internal insulation encapsulation structure, the bottom view of the internal insulation encapsulation structure, the side structure schematic diagram of the internal insulation encapsulation structure, and the structure schematic diagrams of different internal insulation encapsulation structures, including a heat conduction plate 1, a chip 2, leads 3, pins 4, and an encapsulation layer 5. Among them, the heat conduction plate 1 includes a stacked first metal layer 11, an insulating heat conduction layer 12, and a second metal layer 13. The first metal layer 11 includes at least one welding area 14, a first lead area 15, and at least one second lead area 16 spaced from the welding area 14. The welding area 14 is connected to the first lead area 15; at least one chip 2 is welded to the side of the welding area facing away from the insulating heat conduction layer; a plurality of leads 3 are electrically connected to the chips 2 to be interconnected and the respective second lead areas 16 corresponding to the electrodes in the chips 2; a plurality of pins 4 are respectively electrically connected to the respective second lead areas 16 of the welding area 14; the encapsulation layer 5 covers the chips 2, the leads 3, the exposed surfaces of the first metal layer 11, and the ends of the pins 4 welded to the second lead areas 16.

[0054] Specifically, the heat conduction plate 1 is a process platform for manufacturing the internal insulation encapsulation structure, and bears the chips 2, the leads 3, and the pins 4, and realizes the interconnection between the chips 2 in the encapsulation structure and between the chips 2 and the pins 4 through the first metal layer 11 and the leads 3.

[0055] As an example, the heat conduction plate 1 includes a DBC substrate, an AMB substrate, or other suitable high - thermal - conductivity substrates.

[0056] Specifically, the material of the insulating heat conduction layer 12 includes alumina, aluminum nitride, silicon nitride, or other suitable high - thermal - conductivity insulating materials.

[0057] Specifically, when ensuring the performance of the encapsulation structure, the size, thickness, and shape of the heat conduction plate 1 are selected according to the actual situation; the thickness of the first metal layer 11 can be selected according to the actual situation; the thickness and shape of the insulating heat conduction layer 12 can be selected according to the actual situation; the thickness and shape of the second metal layer 13 can be selected according to the actual situation. In this embodiment, the shape of the heat conduction plate 1 is a regular quadrilateral, and the sides of the respective regions of the first metal layer 11 facing away from the insulating heat conduction layer 12 are flush.

[0058] Specifically, the insulating heat conduction layer 12 has good thermal conductivity, so that the heat inside the encapsulation structure is quickly conducted to the second metal layer 13 through the insulating heat conduction layer 12, improving the heat dissipation efficiency of the encapsulation layer.

[0059] Specifically, the material of the first metal layer 11 includes copper, gold, silver or other suitable conductive materials. Preferably, a copper layer with high thermal conductivity and low resistivity is used as the first metal layer 12.

[0060] Specifically, the insulating and heat-conducting layer 12 is stacked on the upper surface of the second metal layer 13, and the first metal layer 11 is stacked on the upper surface of the insulating and heat-conducting layer 12. The material of the second metal layer 13 includes copper, gold, silver, aluminum or other suitable materials with high thermal conductivity. When ensuring the heat-conducting performance of the heat-conducting plate 1, the material of the second metal layer 13 can be the same as or different from that of the first metal layer 11. Preferably, a copper layer with high thermal conductivity is used as the second metal layer 13.

[0061] Specifically, the welding area 14 is used to weld the chip 2 in the packaging structure. At the same time, since the welding area 14 is a conductive metal layer, it is convenient to lead out the electrodes in the chip 2 that are welded to the welding area 14.

[0062] Specifically, the number, size and shape of the welding area 14 are related to the relevant circuits of the functions to be realized by the packaging structure, and can be selected according to the actual circuit conditions.

[0063] Specifically, the first lead area 15 is used for welding the leads 3 and pins 4, so as to lead out the electrodes in the chip 2 that are electrically connected to the welding area 14. At the same time, since the first lead area 15 is connected to the welding area 14, the electrodes in the chip 2 that are welded to the welding area 14 can also be led out through the leads 3 and pins 4 welded to the first lead area 15.

[0064] Specifically, the number of the first lead areas 15 corresponds to the number of the welding areas 14 one by one. When ensuring the performance of the packaging structure, the size, shape and distribution of the first lead areas 15 can be selected according to the requirements of the internal functional circuits and application scenarios in the packaging structure, and will not be limited here.

[0065] Specifically, the second lead areas 16 are usually distributed in the edge area of the insulating and heat-conducting layer 12, so as to lead out the electrodes of the functional circuits in the packaging structure through the leads 3 and pins 4 welded thereto.

[0066] Specifically, when ensuring the performance of the packaging structure, the number, size and shape of the second lead areas 16 can be selected according to the internal functional circuits and application scenarios of the packaging structure, and will not be limited here.

[0067] For example, chip 2 includes MOSFET chips, IGBT chips, FRD chips, JBS chips, SBD chips or other suitable power device chips. Here, the MOSFET chip is a metal oxide semiconductor field effect transistor chip, the IGBT chip is an insulated gate bipolar transistor chip, the FRD chip is a fast recovery diode chip, the JBS chip is a junction barrier Schottky diode chip, and the SBD chip is a Schottky barrier diode chip.

[0068] Specifically, the type, number and arrangement of chips 2 in the packaging structure are related to the functional circuit for realizing the packaging structure, which will not be elaborated here; the size of chip 2 is related to the device structure and manufacturing process, which will not be elaborated here.

[0069] Specifically, based on the functional circuit of the packaging structure, the corresponding electrodes on the back of chip 2 are led to the second lead area 16 or the first lead area 15 by leads 3. When the back electrodes of multiple chips 2 in the packaging structure need to be interconnected, leads 3 also interconnect the back electrodes of different chips 2 based on the functional circuit.

[0070] Specifically, under the condition of ensuring the performance of the packaging structure, the number and length of leads 3 can be selected according to the actual situation, which will not be restricted here.

[0071] Specifically, lead 3 can be in the form of a sheet or a wire. When lead 3 is in the form of a sheet, the current-carrying capacity of the packaging structure can be enhanced, and when lead 3 is in the form of a wire, the current-carrying capacity of the packaging structure can be increased by increasing the number of leads 3 between two bonding points.

[0072] Specifically, under the condition of ensuring the performance of the packaging structure, when lead 3 is in the form of a sheet, its size and thickness can be selected according to the actual situation; when lead 3 is in the form of a wire, its wire diameter can be selected according to the actual situation.

[0073] Specifically, the material of lead 3 includes gold, silver, copper, aluminum or other suitable conductive leads.

[0074] Specifically, pin 4 is used to lead out each electrode of the functional circuit in the packaging structure. The number of pins 4 is related to the function of the functional circuit in the packaging structure, which will not be restricted here; under the condition of ensuring the performance of the packaging structure, the width, length and shape of pin 4 can be selected according to the actual situation. Here, the width refers to the dimension in the long edge direction parallel to the side wall of the insulating and heat-conducting layer 12.

[0075] Specifically, the width of the part of pin 4 welded to the first lead area 15 and the second lead area 16 is greater than the width of the part protruding from the packaging layer, so as to facilitate the welding of pin 4.

[0076] As an example, the widths of the portions of different pins 4 protruding from the encapsulation layer 5 are different, that is, the widths of the portions of the pins 4 exposed outside the encapsulation layer 5 are different, as Figures 6 to 8 , Figures 12 to 14 and Figure 16 shown.

[0077] Specifically, under the condition of ensuring the performance of the encapsulation structure, the widths of the portions of the pins 4 exposed outside the encapsulation layer 5 can also be the same; the lengths of the portions of the pins 4 exposed outside the encapsulation layer 5 can be the same or different; the shapes of the portions of the pins 4 exposed outside the encapsulation layer 5 can be selected according to the actual situation.

[0078] Specifically, the material of the pin 4 includes gold, silver, copper, aluminum, nickel, titanium or other suitable conductive materials.

[0079] Specifically, the encapsulation layer 5 also covers the side wall of the heat conducting plate 1 and there is a preset distance between its side wall and the side wall of the heat conducting plate 1 to protect the heat conducting plate 1, and at the same time, the insulation performance between the pin 4 and the second metal layer 13 can be enhanced, and the reliability of the encapsulation structure can be improved.

[0080] Specifically, under the condition of ensuring the performance of the encapsulation structure, the thickness, size and shape of the encapsulation layer 5 can be selected according to the actual situation and are not limited here.

[0081] Specifically, the material of the encapsulation layer 5 includes epoxy resin, polyimide, poly maleimide triazine resin, polyphenylene ether or polytetrafluoroethylene or other suitable dielectric materials. Preferably, an epoxy resin layer is used as the encapsulation layer 5.

[0082] As an example, the distance range between the portion of the pin 4 protruding from the encapsulation layer 5 and the surface of the heat conducting plate 1 exposed by the encapsulation layer 5 is 2.0 mm to 3.5 mm, that is, the distance range between the plane where the side of the second metal layer 13 away from the insulating heat conducting layer 12 is located and the portion of the pin 4 protruding from the encapsulation layer 5 is 2.0 mm to 3.5 mm.

[0083] Specifically, by controlling the distance between the portion of the pin 4 protruding from the encapsulation layer 5 and the plane of the surface of the heat conducting plate 1 exposed by the encapsulation layer 5 within the range of 2.0 mm to 3.5 mm, when the side of the second metal layer 13 away from the insulating heat conducting layer 11 is welded to the heat dissipation structure, the creepage distance in the high voltage scenario is also satisfied.

[0084] As an example, there is at least one groove 17 between the area electrically connected to the lead 3 and the area electrically connected to the pin 4 in the same second lead area 16, as Figures 5 to 16 shown.

[0085] Specifically, since the pin 4 is usually soldered to the second lead region 16, during the soldering process, the solder is likely to overflow into the region where the lead 3 is bonded in the second lead region 16, affecting the electrical performance of the package structure. A groove 17 is provided between the region where the pin 4 is soldered in the second lead region 16 and the region where the lead 3 is bonded. When soldering the pin 4, the groove 17 can prevent the solder from overflowing onto the lead 3 during the soldering process, ensuring the electrical performance of the package structure. There is no need to set up solder mask between the region where the lead 3 is bonded and the region where the pin 4 is soldered in the second lead region 16 to prevent the solder for soldering the pin 4 from overflowing onto the lead 3, reducing the cost and avoiding the secondary pollution introduced by the solder mask.

[0086] As an example, the depth range of the groove 17 is 20% - 50% of the thickness of the first metal layer 11.

[0087] Specifically, since the groove 17 in the second lead region 16 opens from the side of the second lead region 16 facing away from the insulating and heat-conducting layer 12 and does not penetrate the first metal layer 11, the depth of the groove 17 is only 20% - 50% of the thickness of the first metal layer 11, thus having no impact on the current-carrying capacity of the package structure due to the introduction of the groove 17.

[0088] Specifically, under the condition of ensuring the performance of the package structure, the opening size, opening shape, and number of the groove 17 can be selected according to the actual situation. In this embodiment, a plurality of grooves 17 are provided at intervals between the region where the pin 4 is soldered in the second lead region 16 and the region where the lead 3 is bonded.

[0089] Specifically, the method for forming the groove 17 includes dry etching, wet etching, laser etching, or other suitable methods.

[0090] As an example, the first metal layer 11 includes a plurality of welding regions 14, and the lead 3 also electrically connects the chip 2 to be electrically connected and the first lead region 15, and the welding regions 14 where the first lead region 15 is soldered to the chip 2 are arranged at intervals.

[0091] Specifically, a plurality of welding regions 14 are provided in the first metal layer 11, and the connection between the chip 2 and the first lead region 15 is interconnected based on the functional circuit in the package structure to achieve the function of the functional circuit. For example, based on the connection of the electrodes of each device in the functional circuit, the chip 2 can be electrically connected to a plurality of different first lead regions 15 (i.e., the first lead regions 15 not electrically connected to the chip 2) through the lead 3 at the same time, or can be electrically connected to only one first lead region 15 arranged at intervals with the first lead region 15 where the chip 2 is soldered.

[0092] As an example, at least one groove 17 is further provided between the region where the lead 3 is bonded in the first lead region 15 and the welding region 14.

[0093] Specifically, since the first lead region 15 is connected to the welding region 14, and the chip 2 is usually welded to the welding region 14 through solder. During the welding process, the solder is likely to overflow from the welding region 14 into the region where the lead 3 is bonded in the first lead region 15, affecting the electrical performance of the packaging structure. A groove 17 is provided between the region where the lead 3 is bonded in the first lead region 15 and the welding region 14. When welding the chip 2, the groove 17 can prevent the solder on the surface of the welding region 14 from overflowing onto the lead 3 during the welding process. There is no need to provide solder mask between the region where the lead 3 is bonded in the first lead region 15 and the welding region 14 to prevent the solder for welding the chip 2 from overflowing onto the lead 3 bonded in the first lead region 15, reducing the cost and avoiding the secondary pollution introduced by the solder mask.

[0094] Specifically, a plurality of welding regions 14 are provided in the first metal layer 11. Based on the electrode connection conditions of the devices in the functional circuit, different welding regions 14 can also be interconnected through the lead 3.

[0095] Specifically, the lead 3 is electrically connected to different welding regions 14 and is usually interconnected through the first lead region 15 connected to the welding region 14, that is, the lead 3 is bonded to the first lead region 15 connected to different welding regions 14 to achieve the interconnection between different welding regions 14.

[0096] As an example, a plurality of pins 4 are led out from the same side wall of the encapsulation layer 5. At least one notch 51 is provided in the side wall of the encapsulation layer 5 from which the plurality of pins 4 are led out. The notch 51 is located between two adjacent pins 4 and opens on the surface of the side wall of the encapsulation layer 5 from which the pins 4 are led out, as Figures 5 to 14 shown.

[0097] Specifically, the notch 51 penetrates the encapsulation layer 5 in the stacking direction of the chip 2 and the heat conducting plate 1, and the bottom surface of the notch 51 is spaced from the side wall of the heat conducting plate 1 by a preset distance. Under the condition of ensuring the performance of the packaging structure, the opening size and shape of the notch 51 can be selected according to the actual situation; the distance between the bottom surface of the notch 51 and the side wall of the heat conducting plate 1 can be selected according to the actual situation. Here, the opening size and shape of the notch 51 refer to the opening on the side wall of the encapsulation layer 5, and the bottom surface of the notch 51 refers to the surface parallel to the side wall of the encapsulation layer 5 from which the plurality of pins 4 are led out.

[0098] Specifically, a plurality of pins 4 are led out from the same side wall of the encapsulation layer 5. By providing a notch 51 between two adjacent pins 4 on this side wall, the creepage distance between the pins 4 in the packaging structure can be enhanced, improving the performance of the packaging structure.

[0099] Specifically, a heat dissipation structure 6 fixedly connected to the heat conducting plate 1 is further provided on the surface of the heat conducting plate 1 exposed by the encapsulation layer 5.

[0100] Specifically, the heat dissipation structure 6 is usually used to accelerate the release of heat in the packaging structure and improve the heat dissipation capacity of the packaging structure. Under the condition of ensuring the performance of the packaging structure, the structure, shape and size of the heat dissipation structure 6 can be selected according to the actual situation. Preferably, a finned radiator is used as the heat dissipation structure 6.

[0101] Specifically, a welding layer for fixedly connecting the heat dissipation structure 6 and the second metal layer 13 is also provided between the heat dissipation structure 6 and the second metal layer 13. The welding layer is formed by a common welding material through a welding process, which will not be elaborated here.

[0102] Specifically, under the condition of ensuring the heat dissipation performance of the packaging structure, the heat dissipation structure 6 can also be fixed on the side of the encapsulation layer 5 where the heat conducting plate 1 is exposed by clamping or screwing, and a thermal grease layer is provided between the second metal layer 13 exposed on the encapsulation layer 5 and the heat dissipation structure 6 to improve the heat transfer effect between the second metal layer 13 and the heat dissipation structure 6.

[0103] As an example, a circuit board 7 electrically connected to the end of the pin 4 away from the encapsulation layer 5 is also provided in the discrete device packaging structure, as Figure 17 shown.

[0104] Specifically, the electrical connection between the packaging structure and the circuit board 7 is realized by welding the packaging structure to the circuit board 7. By welding the packaging structure to the circuit board 7, it is convenient to apply the packaging structure and other circuits to a complex functional circuit. The size and shape of the circuit board 7 and the circuit distribution in the circuit board 7 can be selected according to the actual situation.

[0105] Specifically, when the packaging structure is welded to the circuit board 7, a support layer 71 for supporting the packaging structure can be provided between the packaging structure and the circuit board 7 if necessary. The support layer 71 is fixed together with the packaging structure and the circuit board 7, and its material, thickness, size and shape can be selected according to the actual situation.

[0106] Specifically, by using the heat conducting plate 1 as the substrate of the packaged chip 2, the heat conducting plate 1 includes a second metal layer 13, an insulating heat conducting layer 12 and a first metal layer 11 stacked in sequence. Among them, a welding area 14 for welding the chip 2, a first lead area 15 and a second lead area 16 communicating with the welding area 14 are provided in the first metal layer 11. Through the isolation of the insulating heat conducting layer 12, the chip 2 welded on the welding area 14 is insulated from the second metal layer 13, and the sizes of the first lead area 15 and the second lead area 16 in the first metal layer 11 can divide the area where the lead 3 is bonded according to the requirements of the functional circuit in the packaging structure to be larger, so that the number of leads 3 that can be bonded in the first lead area 15 and the second lead area 16 increases, improving the product current capacity and avoiding the influence of the fixed bonding area of the lead 3 in the lead frame on the current capacity of the packaging structure.

[0107] Specifically, since the upper surfaces of the welding area 14, the first lead area 15 and the second lead area 16 are flush, it is possible to synchronously form the welding layer of the welding pins 4 and the chip 2, and synchronously weld the chip 2 and the pins 4, reducing the number of welding operations, improving the welding precision and efficiency, and enhancing the reliability of the packaging structure.

[0108] Specifically, by forming grooves 17 between the area where the welding area 14 in the first lead area 15 is bonded to the lead 3 and the area where the pin 4 in the second lead area is bonded to the lead 3, it blocks the solder overflowing onto the lead 3 during the process of welding the chip 2 and the pins. There is no need to set up solder mask to prevent the solder from overflowing onto the lead 3, reducing the packaging cost and avoiding the secondary pollution caused by the solder mask. Moreover, since the depth of the groove 17 is 20% - 50% of the thickness of the first metal layer 11, it ensures the current-carrying capacity of the packaging structure while ensuring the performance of the packaging structure.

[0109] Specifically, by adjusting the distance between the part of the pin 4 protruding from the packaging layer 5 and the surface of the second metal layer 13 exposed on the packaging layer 5, when the heat dissipation structure 6 is soldered to the back of the second metal layer 13, it can also ensure the creepage distance of the packaging structure under high-voltage environments.

[0110] Specifically, since the heat conducting plate 1 includes an insulating heat conducting layer 12 and a second metal layer 13 covering the insulating heat conducting layer 12 away from the first metal layer 11, directly soldering the heat dissipation structure 6 to the side of the second metal layer 13 away from the insulating heat conducting layer 12 with high thermal conductivity solder can significantly reduce the thermal resistance of the system composed of the packaging structure and the heat dissipation structure 6, enhance the heat dissipation capacity of the system, and reduce the packaging cost.

[0111] In summary, the internal insulation encapsulation structure of the present utility model improves the encapsulation structure. The heat conduction plate including the stacked first metal layer, insulation heat conduction layer and second metal layer is used as the substrate for soldering the chips in the discrete devices. Moreover, the first lead areas and the second lead areas for bonding leads and soldering pins in the first metal layer can be divided into larger sizes according to the needs of the functional circuit, increasing the number of leads bonded to the first lead areas and the second lead areas and enhancing the current capacity of the encapsulation structure. Grooves are provided in the second lead areas between the leads and the pins and in the first lead areas between the soldering areas and the leads, blocking the solder overflowing during the soldering process from reaching the leads, ensuring the electrical performance of the encapsulation structure, reducing the encapsulation cost, and avoiding the secondary pollution introduced by setting the solder mask layer. By combining the heat conduction plate with the encapsulation layer and adjusting the distance between the pins protruding from the encapsulation layer and the second metal layer, when the heat dissipation structure is soldered to the back of the second metal layer, the creepage distance of the encapsulation structure in a high-voltage environment can also be ensured, enhancing the reliability of the encapsulation structure. In addition, by utilizing the combination of the second metal layer and the insulation heat conduction layer, the heat dissipation structure can be directly soldered to the second metal layer through the solder with high thermal conductivity, reducing the thermal resistance of the system composed of the encapsulation structure and the heat dissipation structure, enhancing the heat dissipation capacity of the system, and reducing the encapsulation cost. Therefore, the present utility model effectively overcomes various drawbacks in the prior art and has high industrial utilization value.

[0112] The above embodiments are only illustrative of the principles and effects of the present utility model and are not intended to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present utility model should still be covered by the claims of the present utility model.

Claims

1. An internal insulation encapsulation structure, characterized in that, Comprising: A heat conducting plate, including a stacked first metal layer, an insulating and heat conducting layer, and a second metal layer. The first metal layer includes at least one welding area, a first lead area, and at least one second lead area spaced apart from the welding area. The welding area communicates with the first lead area; At least one chip, welded to the side of the welding area facing away from the insulating and heat conducting layer; A plurality of leads, electrically connecting the chips to be interconnected and the respective second lead areas corresponding to the electrodes in the chips; A plurality of pins, electrically connected to the welding area and each of the second lead areas respectively; A packaging layer, covering the chip, the lead, the first metal layer, and the exposed surface of the pin welded to one end of the second lead area.

2. The internal insulation encapsulation structure according to claim 1, characterized in that: The chip includes a MOSFET chip, an IGBT chip, an FRD chip, a JBS chip, an SBD chip; the heat conducting plate includes a DBC substrate, an AMB substrate.

3. The internal insulation encapsulation structure according to claim 1, characterized in that: The distance between the part of the pin protruding from the packaging layer and the surface of the heat conducting plate exposed by the packaging layer ranges from 2.0 mm to 3.5 mm.

4. The internal insulation encapsulation structure according to claim 1, characterized in that: In the same second lead area, at least one groove is further provided between the area electrically connected to the lead and the area electrically connected to the pin.

5. The internal insulation encapsulation structure according to claim 4, characterized in that: The depth range of the groove is 20% to 50% of the thickness of the first metal layer.

6. The internal insulation encapsulation structure according to claim 1, characterized in that: The first metal layer includes a plurality of welding areas. The lead also electrically connects the chips to be electrically connected and the first lead area, and the first lead area is spaced apart from the welding area where the chip is welded.

7. The inner insulation encapsulation structure according to claim 6, characterized in that: At least one groove is further provided between the area where the lead is bonded in the first lead area and the welding area.

8. The internal insulation encapsulation structure according to claim 1, wherein: A plurality of the pins are led out from the same side wall of the packaging layer, and at least one notch is provided in the side wall of the packaging layer from which the plurality of pins are led out. The notch is located between two adjacent pins and opens on the surface of the side wall of the packaging layer from which the pins are led out.

9. The internal insulation encapsulation structure according to claim 1, wherein: A heat dissipation structure fixedly connected to the heat conducting plate is further provided on the surface of the heat conducting plate exposed by the packaging layer.

10. The internal insulation encapsulation structure according to claim 1, wherein: A circuit board electrically connected to the end of the pin away from the packaging layer is further provided in the inner insulation packaging structure.

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