DBC ceramic substrate and power semiconductor module
By setting bubble point, chamfer and stress relief holes on the DBC ceramic substrate, the problem of ceramic layer cracking caused by insufficient stress relief during welding is solved, the reliability and production yield of the device are improved, and the cost is reduced.
Patent Information
- Application Number
- CN202422302525.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-09-20
AI Technical Summary
The existing DBC-Al2O3 ceramic substrates are not fully released during welding, resulting in cracking of the ceramic layer and cost loss.
Bubble point, chamfer and stress relief hole are installed on the DBC ceramic substrate. These structural designs reduce the influence of thermal stress during welding and ultrasonic bonding and avoid cracking of the ceramic layer.
It improves the reliability and production yield of the device, reduces costs, avoids the use of DBC-ZTA ceramic substrates, and realizes cost controllability.
Smart Images
Figure CN223092888U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of power semiconductors, and particularly relates to a DBC ceramic substrate and a power semiconductor module. Background Art
[0002] The DBC process is a packaging technology commonly used in electronic power devices. DBC (Direct Bonded Copper) refers to directly bonding a copper foil to a ceramic substrate to form a tightly combined composite material. According to different classifications, DBC ceramic substrates can be divided into DBC-Al2O3 (aluminum oxide ceramic substrate) and DBC-ZTA (zirconium-doped aluminum oxide ceramic substrate).
[0003] The DBC-ZTA ceramic substrate is a product formed based on zirconium-doped Al2O3 ceramic. The zirconium-doped Al2O3 ceramic improves the performance of DBC and its bending degree. During the module packaging welding furnace passing and the terminal ultrasonic bonding process, there will be no problem of cracking of the DBC ceramic layer. Compared with the DBC-Al2O3 ceramic substrate, the DBC-ZTA ceramic substrate has a longer service life and higher reliability, but its cost is higher.
[0004] Therefore, in order to reduce costs and according to different application requirements, in some industrial environments with low requirements, attempts have been made to use DBC-Al2O3 ceramic substrates. The DBC-Al2O3 ceramic substrate has a higher cost performance compared to the DBC-ZTA ceramic substrate, but its flexibility is reduced. Therefore, during the actual welding and terminal ultrasonic bonding processes, the DBC ceramic layer will crack due to the stress not being well released, resulting in relatively large cost losses. For example: in a DPIM packaging module with a small area and complex structure, the stress is not fully released during welding and terminal bonding, making the cracking problem most serious.
[0005] In the process of implementing the present utility model, the inventor found that there are at least the following problems in the prior art:
[0006] During the actual welding process of the existing DBC-Al2O3 ceramic substrate, the stress is not fully released, resulting in cracking of the DBC ceramic layer and causing relatively large cost losses. Summary of the Utility Model
[0007] The purpose of the present utility model is to provide a DBC ceramic substrate and a power semiconductor module to solve the technical problem in the prior art that during the actual welding process of the DBC-Al2O3 ceramic substrate, the stress is not fully released, resulting in cracking of the DBC ceramic layer and causing relatively large cost losses. The many technical effects that can be produced by the preferred technical solutions provided by the present utility model are described in detail below.
[0008] To achieve the above object, the present utility model provides the following technical solutions:
[0009] In a first aspect, the present utility model provides a DBC ceramic substrate, comprising: a first metal layer, a second metal layer, and a ceramic layer, wherein the ceramic layer is located between the first metal layer and the second metal layer;
[0010] Bubble fixing points are provided inside the edges of the first metal layer;
[0011] The second metal layer includes a power area, a power pin area, and a temperature sampling area. Chamfers are provided at the edges of the power area, the power pin area, and the temperature sampling area; Bubble fixing points are provided inside the edges of the power area, the power pin area, and the temperature sampling area.
[0012] Optionally, the power area includes a power input area, a first power output area, and a second power output area. Stress relief holes are provided in the power input area, the first power output area, and the second power output area; The stress relief holes are used to eliminate the stress generated when the power chip is welded on the power input area, the first power output area, and the second power output area.
[0013] Optionally, the stress relief holes are one or more of strip-shaped, circular, oval, and rectangular.
[0014] Optionally, the bubble fixing points are circular or spherical.
[0015] Optionally, the diameter of the bubble fixing points is 0.2 - 0.8 mm.
[0016] Optionally, the radius of the chamfers is 1 - 6 mm.
[0017] Optionally, a thermistor accommodation area is provided in the temperature sampling area.
[0018] In a second aspect, based on the same inventive concept, the present utility model further provides a power semiconductor module, which is characterized in that it includes the DBC ceramic substrate according to any one of the claims, and further includes a thermistor, a power chip, power pins, and temperature sampling pins. The power chip is correspondingly arranged in the power area, the power pins are arranged in the corresponding power pin area, the temperature sampling pins are correspondingly arranged in the temperature sampling area, and the thermistor is correspondingly arranged in the thermistor accommodation area.
[0019] Optionally, the power chip is a MOSFET, an IGBT, or an FRD;
[0020] Adjacent two power chips arranged on the power area are separated by stress relief holes.
[0021] Optionally, the power pins are arranged in the corresponding power pin areas through bonding metal wires or bonded metal copper sheets;
[0022] The power pins are in a Z shape, an S shape or a straight pin shape.
[0023] Implementing one of the above technical solutions of the present utility model has the following advantages or beneficial effects:
[0024] A DBC ceramic substrate provided by the present utility model can reduce the influence of thermal stress during the vacuum welding process of the power chip on the DBC ceramic substrate, and avoid cracking of the ceramic layer of the DBC ceramic substrate during ultrasonic bonding of the power pins, eliminate stress, improve the reliability and production yield of the device, and achieve corresponding technical effects without using DBC-ZTA (zirconium-doped alumina ceramic substrate), making the cost controllable. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In the drawings:
[0026] Figure 1 is the overall structural schematic diagram of Embodiment 1 of the present utility model;
[0027] Figure 2 is the structural schematic diagram of the first metal layer in Embodiment 1 of the present utility model;
[0028] Figure 3 is the structural schematic diagram of the second metal layer in Embodiment 1 of the present utility model;
[0029] Figure 4 is the installation structural schematic diagram of the power semiconductor module in Embodiment 2 of the present utility model.
[0030] In the figures: 1, the first metal layer; 11, the bubble point; 2, the ceramic layer; 3, the second metal layer; 31, the power area; 311, the power input area; 312, the first power output area; 313, the second power output area; 314, the fourth power area; 32, the power pin area; 33, the temperature sampling area; 34, the thermistor accommodation area; 35, the chamfer; 36, the stress relief hole; 4, the power chip; 41, the IGBT; 42, the FRD; 5, the thermistor; 6, the power pin; 7, the temperature sampling pin; 8, the electrical clearance. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0031] To make the objectives, technical solutions and advantages of the present utility model more clear and understandable, various exemplary embodiments to be described below will refer to the corresponding drawings, which form a part of the exemplary embodiments and describe various exemplary embodiments that may be adopted to implement the present utility model. Unless otherwise indicated, the same numerals in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. It should be understood that they are merely examples of processes, methods, devices, etc. that are consistent with some aspects of the present utility model disclosed in detail in the appended claims. Other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present utility model.
[0032] In the description of the present utility model, it should be understood that terms such as "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings shown, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. Terms such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. The meaning of the term "plurality" is two or more. The terms "connected" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.
[0033] To illustrate the technical solutions described in the present utility model, the following will be described by specific examples, and only the parts related to the embodiments of the present utility model are shown.
[0034] Embodiment 1:
[0035] The first embodiment of the present utility model provides a DBC ceramic substrate, as Figures 1-3 shown, including: a first metal layer 1, a second metal layer 3, and a ceramic layer 2, with the ceramic layer 2 located between the first metal layer 1 and the second metal layer 3; fixing bubble points 11 are provided inside the edges of the first metal layer 1; the second metal layer 3 includes a power area 31, a power pin area 32, and a temperature sampling area 33, and chamfers 35 are provided at the edges of the power area 31, the power pin area 32, and the temperature sampling area 33; fixing bubble points 11 are provided inside the edges of the power area 31, the power pin area 32, and the temperature sampling area 33.
[0036] Specifically, the first metal layer 1 is a heat dissipation layer, which is used for heat dissipation when the power module is working. The second metal layer 3 is a power layer, which is used to carry the power chip 4, power pins 6, etc., for power input or power output. As Figure 1 shown, the ceramic layer 2 is located between the first metal layer 1 and the second metal layer 3, and is used for electrical insulation. It should be noted that the first metal layer 1, the ceramic layer 2 and the second metal layer 3 are manufactured and connected by the DBC process.
[0037] As Figure 2 and Figure 3 shown, dimple points 11 (Dimple points) are uniformly arranged inside the edge of the first metal layer 1, and dimple points 11 are also arranged inside the edges of the power area 31, power pin area 32 and temperature sampling area 33 on the second metal layer 3. The setting of the dimple points 11 can increase the adhesion and adhesiveness between the metal layer and the ceramic layer 2, improve the adhesion force, and can solve or reduce the influence of thermal stress during the vacuum high-temperature welding process of the power chip 4 on the DBC ceramic substrate, and when the power pins 6 are ultrasonically bonded, avoid the ceramic layer 2 of the DBC ceramic substrate from cracking.
[0038] As an optional implementation manner, the dimple points 11 are circular or spherical, that is, blind holes. Preferably, the diameter of the dimple points 11 is 0.2 - 0.8 mm. After verification, when the DBC ceramic substrate with dimple points 11 in this diameter range is ultrasonically bonded at 240 °C under vacuum, with a 25 KHz ultrasonic frequency and a 200 μm deformation amount, the DBC stress is small and no fracture occurs. The test data of dimple points 11 with different diameters and the state of the DBC ceramic substrate are shown in Table 1:
[0039] Table 1
[0040]
[0041]
[0042] As can be seen from Table 1, when the diameter of the dimple points 11 is in the range of 0.2 - 0.8 mm, the DBC ceramic substrate will not fracture due to ultrasonic bonding or welding. It should be noted that the dimple points 11 described in this embodiment are only dimpled at the edges of the first metal layer 1 and the second metal layer 3 of the DBC ceramic substrate through the dimple process, and do not completely penetrate the metal layer. In addition, in this embodiment, the dimple points 11 are preferably dot-shaped or spherical, but selecting other shapes (such as rectangular, hexagonal, elliptical, etc.) can also achieve the same technical effect in principle, and will not be elaborated here.
[0043] As Figure 3As shown, the second metal layer 3 of the DBC board includes a power area 31, a power pin area 32, and a temperature sampling area 33. There is an electrical gap 8 between the power area 31, the power pin area 32, and the temperature sampling area 33 for electrical layout according to the corresponding electrical circuit.
[0044] As Figure 3 shown, chamfers 35 are provided at the edges of the power area 31, the power pin area 32, and the temperature sampling area 33. The chamfers 35 are preferably rounded corners, and the radius of the chamfers 35 is 1 to 6 mm. Setting the edges of the power area 31, the power pin area 32, and the temperature sampling area 33 as chamfers 35, and the radius of the chamfer 35 of the power area 31 is larger, further expanding the chamfer 35 of the internal copper-clad structure, enabling the stress to be fully released, and being able to thoroughly improve the cracking problem of the DBC ceramic substrate during the welding and terminal bonding processes, and being able to further improve the reliability of the device manufacturing process.
[0045] It should be noted that multiple power pin areas 32 are provided to facilitate the connection of power terminals.
[0046] As an optional implementation manner, as Figure 3 shown, the power area 31 includes a power input area 311, a first power output area 312, and a second power output area 313. Stress relief holes 36 are provided in the power input area 311, the first power output area 312, and the second power output area 313; the stress relief holes 36 are used to eliminate the stress generated when the power chip 4 is welded on the power input area 311, the first power output area 312, and the second power output area 313.
[0047] Specifically, the power input area 311, the first power output area 312, and the second power output area 313 of the power area 31 are all used to carry the power chip 4. Stress relief holes 36 are provided on the power input area 311, the second power output area 313, and the second power output area 313. The stress relief holes 36 are located between adjacent power chips 4 and are used to relieve or eliminate the stress generated when the power chip 4 is welded on the power input area 311, the second power output area 313, and the second power output area 313, preventing the DBC ceramic substrate from cracking.
[0048] It should be noted that the stress relief holes 36 are different from the bubble points 11. The stress relief holes 36 penetrate through the power area 31 where they are located, further alleviating the problem of the DBC ceramic substrate cracking caused by the stress generated during the welding process of the power chip 4. In addition, the stress relief holes 36 are one or more of strip-shaped, circular, oval, and rectangular.
[0049] In addition to including a power input area 311, a first power output area 312, and a second power output area 313, the power area 31 further includes a fourth power area 314. A rivet bubble point 11 is also provided on the fourth power area 314. The fourth power area 314 is used to mount the power terminals required for the power semiconductor module and is used to connect to the negative pole or ground.
[0050] As an optional implementation manner, as Figure 3 shown, the temperature sampling area 33 is located between two power pin areas 32. A thermistor accommodation area 34 is provided in the temperature sampling area 33. There are two temperature sampling areas 33, and the thermistor accommodation area 34 is provided between the two temperature sampling areas 33. The setting of the thermistor accommodation area 34 enables the thermistor 5 to be welded to the temperature sampling area 33 more stably, improving the reliability of the device.
[0051] A DBC ceramic substrate provided by the present utility model can solve or reduce the influence of thermal stress during the vacuum welding process of the power chip 4 on the DBC ceramic substrate, and avoid the ceramic layer 2 of the DBC ceramic substrate from cracking during the ultrasonic bonding of the power pins 6, eliminate stress, improve the reliability and production yield of the device, and achieve the corresponding technical effects without using DBC-ZTA (zirconium-doped alumina ceramic substrate), making the cost controllable by setting rivet holes, chamfers 35, and stress relief holes 36.
[0052] The embodiment is only a special case and does not indicate that the present utility model has only such an implementation manner.
[0053] Embodiment Two:
[0054] The second embodiment of the present utility model further provides a power semiconductor module, as Figure 4 shown, including the DBC ceramic substrate described in Embodiment One, further including a thermistor 5, a power chip 4, power pins 6, and temperature sampling pins 7. The power chip 4 is correspondingly arranged in the power area 31, the power pins 6 are arranged in the corresponding power pin areas 32, the temperature sampling pins 7 are correspondingly arranged in the temperature sampling areas 33, and the thermistor 5 is correspondingly arranged in the thermistor accommodation area 34. The power chip 4 is a MOSFET, IGBT41, or FRD42. Adjacent two power chips 4 arranged on the power area 31 are separated by stress relief holes 36.
[0055] As Figure 4As shown, this embodiment uses IGBT41 and FRD42 power chips 4 to perform electrical layout according to the H-bridge circuit layout. Specifically, the second metal layer 3 on the DBC ceramic substrate is a power layer, which is used to carry the power chip 4 and the power pin 6, etc. The chip and the bonding pin are welded on the second metal layer 3, and then packaged to form a power semiconductor module. In addition to the DBC ceramic substrate described in the first embodiment, the power semiconductor module also includes Figure 4 As shown, it also includes a power chip 4 correspondingly arranged on the power area 31, a power pin 6 correspondingly arranged on the power pin area 32, a temperature sampling pin 7 correspondingly arranged on the temperature sampling area 33, and a thermistor 5 correspondingly arranged on the thermistor accommodation area 34. In this embodiment, the thermistor 5 can be selected as a cylindrical thermistor or a rectangular thermistor. If a cylindrical thermistor is selected, it is adapted to the thermistor accommodation area 34 to avoid displacement of the cylindrical thermistor during the welding process. If a rectangular thermistor is selected, it can be set in the thermistor accommodation area 34, or it can be set at other positions between the two temperature sampling areas 33, but no matter how the rectangular thermistor is set, it will not affect its subsequent use; the thermistor accommodation area 34 is set mainly to meet the requirements of different performances of the power module and adopt a similar cylindrical thermistor in the welding process. The limit fixation prevents the resistor from shifting during the welding process, which makes the power module performance unreliable.
[0056] It should be noted that two adjacent power chips 4 arranged in the power input area 311, the first power output area 312 and the second power output area 313 are separated by a stress release hole 36. The setting of the stress release hole 36 further alleviates the problem of the DBC ceramic substrate being cracked due to the stress generated by the IGBT41 and FRD42 power chips 4 during the welding process.
[0057] The power semiconductor module shown in this embodiment is arranged in the form of an H-bridge circuit on the DBC ceramic substrate recorded in Example 1. In addition, the module structure in this embodiment can also be arranged according to other electrical principles, such as a three-phase full-bridge circuit, a half-bridge circuit or other customized circuits, etc. At the same time, the power chip 4 uses IGBT41 and FRD42 only as an example for a better understanding of this embodiment, and does not mean that it is limited to IGBT41 and FRD42 power chips 4. If other power chips 4 are used as substitutes, such as MOSFET, etc., stress release holes 36 are set between any two adjacent chips to achieve the same technical effect.
[0058] As an alternative embodiment, the power pin 6 is disposed in the corresponding power pin area 32 through bonding metal wires or bonding metal copper sheets. Exemplarily, for the power pin 6 and the temperature sampling pin 7 of the present utility model, Z-shaped, S-shaped, vertical pin-shaped, etc. are all acceptable. The power pin 6 and the temperature sampling pin 7 are both connected to the corresponding power pin area 32 and temperature sampling area 33 by ultrasonic bonding or solder / solder welding. The power chip 4 is connected to the power pin 6 or the copper layer where the power pin 6 is located through bonding metal wires (preferably aluminum wires, copper wires) or bonding metal sheets (preferably copper sheets). The power areas 31 are connected through bonding metal wires (preferably aluminum wires, copper wires) or bonding metal sheets (preferably copper sheets).
[0059] The power semiconductor module obtained by subsequent processing using the DBC board described in Embodiment 1 reduces the process damage rate, improves the production yield of the product, and at the same time ensures the reliability of the power semiconductor module.
[0060] The above are only the preferred embodiments of the present utility model. Those skilled in the art know that without departing from the spirit and scope of the present utility model, various changes or equivalent substitutions can be made to these features and embodiments. Additionally, under the teaching of the present utility model, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present utility model. Therefore, the present utility model is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present utility model.
Claims
1. A DBC ceramic substrate, characterized in that, Comprising: A first metal layer (1), a second metal layer (3) and a ceramic layer (2), wherein the ceramic layer (2) is located between the first metal layer (1) and the second metal layer (3); Bumping points (11) are provided inside the edges of the first metal layer (1); The second metal layer (3) includes a power area (31), a power pin area (32) and a temperature sampling area (33), and chamfers (35) are provided at the edges of the power area (31), the power pin area (32) and the temperature sampling area (33); Bumping points (11) are provided inside the edges of the power area (31), the power pin area (32) and the temperature sampling area (33).
2. The DBC ceramic substrate according to claim 1, characterized in that, The power area (31) includes a power input area (311), a first power output area (312) and a second power output area (313), and stress relief holes (36) are provided inside the power input area (311), the first power output area (312) and the second power output area (313); The stress relief holes (36) are used to eliminate the stress generated when the power chip (4) is soldered on the power input area (311), the first power output area (312) and the second power output area (313).
3. The DBC ceramic substrate according to claim 2, wherein, The stress relief holes (36) are one or more of strip-shaped, circular, oval and rectangular.
4. The DBC ceramic substrate according to claim 1, wherein The bumping points (11) are circular or spherical.
5. The DBC ceramic substrate according to claim 4, wherein The diameter of the bumping points (11) is 0.2 - 0.8 mm.
6. The DBC ceramic substrate according to claim 1, wherein The radius of the chamfers (35) is 1 - 6 mm.
7. The DBC ceramic substrate according to claim 1, wherein, A thermistor accommodating area (34) is provided inside the temperature sampling area (33).
8. A power semiconductor module, characterized in that, Comprising the DBC ceramic substrate according to any one of claims 1 - 7, further comprising a thermistor (5), a power chip (4), power pins (6) and temperature sampling pins (7), wherein the power chip (4) is correspondingly arranged in the power area (31), the power pins (6) are arranged in the corresponding power pin area (32), the temperature sampling pins (7) are correspondingly arranged in the temperature sampling area (33), and the thermistor (5) is correspondingly arranged in the thermistor accommodating area (34).
9. The power semiconductor module according to claim 8, characterized in that, The power chip (4) is a MOSFET, an IGBT or an FRD; Adjacent two power chips (4) arranged on the power area (31) are separated by stress relief holes (36).
10. The power semiconductor module according to claim 8, characterized in that, The power pins (6) are arranged inside the corresponding power pin area (32) through bonding metal wires or bonding metal copper sheets; The power pins (6) are Z-shaped, S-shaped or straight pin-shaped.