Rail transit platform door control system
A redundant station door control system with a main and backup control unit addresses the high failure rates of existing PEDC systems, ensuring reliable door operation and train operation continuity.
Patent Information
- Application Number
- CN202421739001.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-22
- Publication Date
- 2025-07-15
- Estimated Expiration
- 2034-07-22
AI Technical Summary
The internal relay failure rate of the existing logic control unit PEDC is high, resulting in the failure of the single-side platform door to open and close the door normally, affecting driving order.
A rail transit station gate control system is designed, using logic control unit LCU, terminal control disk PSL, integrated backup disk IBP, signal system SIG, gate controller DCU and integrated monitoring module to realize power redundancy, controller redundancy, IO redundancy and network redundancy, and enhance the reliability of the system.
It effectively solves the problem that the single-sided platform door cannot be opened and closed due to the failure of the internal relay of PEDC, reduces the equipment failure rate and ensures normal driving order.
Smart Images
Figure CN223104395U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of rail transit control, and particularly relates to a rail transit platform screen door control system. Background Technique
[0002] The platform screen door system includes a logic control unit PEDC (platform electrical docontroller), an integrated backup panel IBP (integrated backup panel), a platform screen doors local control panel PSL (platform screen doors local control panel), a door control unit DCU (door control unit), and a signaling system SIG (signaling system). Among them, the logic control unit PEDC is arranged in the main control cabinet in the platform screen door equipment room and is a device for monitoring the operation of the platform screen door; the integrated backup panel IBP is arranged in the train control room and is a device for controlling a single-sided platform screen door in case of emergency; the platform screen doors local control panel PSL is arranged at both ends or in the middle of the platform area and is a device for locally controlling a single-sided platform screen door; the door control unit DCU is a device for locally controlling a single door; and the signaling system SIG is a system for monitoring the operation of the train and the opening and closing of the platform screen door.
[0003] The existing logic control unit PEDC and internal relays do not have redundancy functions, and the failure rate is relatively high. Content of the Utility Model
[0004] The purpose of the utility model is to provide a rail transit platform screen door control system, which effectively solves the problem that the single-sided platform screen door cannot be opened or closed due to the failure of the internal relay of the PEDC, and achieves the purpose of reducing the equipment failure rate and ensuring the normal train operation order.
[0005] To solve the above technical problems, the utility model adopts the following technical solutions:
[0006] A platform screen door control system for rail transit, comprising a logic control unit LCU, a platform side control panel PSL, an integrated backup panel IBP, a signal system SIG, a door control unit DCU, and an integrated monitoring module. The power input terminal of the logic control unit LCU is connected to a first input power supply; the power input terminal of the platform side control panel PSL is connected to a second input power supply, and the platform side control panel PSL is connected to the logic control unit LCU; the power input terminal of the integrated backup panel IBP is connected to the second input power supply, and the integrated backup panel IBP is connected to both the logic control unit LCU and the platform side control panel PSL; the power input terminal of the signal system SIG is connected to a third input power supply, and the signal system SIG is connected to the logic control unit LCU, the platform side control panel PSL, and the integrated backup panel IBP; the door control unit DCU is connected to the logic control unit LCU, the platform side control panel PSL, and the integrated backup panel IBP; the power input terminal of the integrated monitoring module is connected to a fourth input power supply, and the integrated monitoring module is connected to the logic control unit LCU.
[0007] A further technical solution is that: the logic control unit LCU includes a main chassis circuit; the main chassis circuit includes a main chassis control chip, relays K38, K40, K41, and K42; the PL5_d32 of the main chassis control chip is connected to the 12th pin of relay K42, and the 11th pin of relay K42 is connected to the first input power supply; the PL5_d30 of the main chassis control chip is connected to the 12th pin of relay K41, and the 11th pin of relay K41 is connected to the control power supply; the PL5_d28 of the main chassis control chip is connected to the 1st pin of relay K38; the PL9_z2 and z10 of the main chassis control chip are both connected to L1 of the door head enable power supply; the PL9_z6 and PL9_z14 of the main chassis control chip are both connected to L2 of the door head enable power supply; the PL3_d2 of the main chassis control chip is connected to both the 5th pin of relay K38 and the 12th pin of relay K40, the 8th pin of relay K38 is connected to the 14th pin of relay K40, the 9th pin and the 12th pin of relay K38 are connected to the drive power supply, and the 11th pin of relay K40 is respectively connected to the first input power supply and the control power supply; the PL4_z2, PL4_z4, PL4_z22, and PL4_z24 of the main chassis control chip are all connected to L1 of the PEDC power supply; the PL4_z8, PL4_z10, PL4_z28, and PL4_z30 of the main chassis control chip are all connected to N1 of the PEDC power supply; the PL1_z2, PL1_z4, PL1_z22, and PL1_z24 of the main chassis control chip are all connected to L1 of the indicator light power supply; the PL1_z8, PL1_z10, PL1_z28, and PL1_z30 of the main chassis control chip are all connected to N1 of the indicator light power supply.
[0008] A further technical solution is as follows: The main chassis circuit further includes CAN units, relays K30, K31, K32, K33, K34, K35, K36, K37, K43, K44, K45 and K46; The SK9_9 pin of the main chassis control chip is connected to the 14th pin of relay K37, and the 11th pin of relay K37 is connected to CAN2_COM of the door controller DCU; The SK9_8 pin of the main chassis control chip is connected to the 14th pin of relay K36, and the 11th pin of relay K36 is connected to CAN2_L of the door controller DCU; The SK9_4 pin of the main chassis control chip is connected to the 14th pin of relay K35, and the 11th pin of relay K35 is connected to CAN2_H of the door controller DCU; The SK9_7 pin of the main chassis control chip is connected to the 14th pin of relay K34, and the 11th pin of relay K34 is connected to CAN1_COM of the door controller DCU; The SK9_6 pin of the main chassis control chip is connected to the 14th pin of relay K33, and the 11th pin of relay K33 is connected to CAN1_L of the door controller DCU; The SK9_2 pin of the main chassis control chip is connected to the 14th pin of relay K32, and the 11th pin of relay K32 is connected to CAN1_H of the door controller DCU; PL10_z18 of the main chassis control chip is connected to the 1st pin of relay K30; PL10_z22 of the main chassis control chip is connected to the 4th pin of relay K30, the 9th pin of relay K30 is connected to ENABLE_L1 of the door controller DCU, and the 12th pin of relay K30 is connected to ENABLE_L2 of the door controller DCU; PL10_z26 of the main chassis control chip is connected to the 1st pin of relay K31, and the 9th pin of relay K31 is connected to OPEN_L1 of the door controller DCU; PL3_z20 of the main chassis control chip is connected to the 12th pin of relay K43, and the 11th pin of relay K43 is connected to SUPLLY of the door controller DCU; PL3_z32 of the main chassis control chip is connected to the 12th pin of relay K46, and the 11th pin of relay K46 is connected to RETURN of the door controller DCU; PL6_d2 and PL6_d4 of the main chassis control chip are both connected to the 12th pin of relay K44, and the 11th pin of relay K44 is connected to SW+ of the door controller DCU; PL6_z2 and PL6_z4 of the main chassis control chip are both connected to the 12th pin of relay K45, and the 11th pin of relay K45 is connected to SW- of the door controller DCU; A of the CAN unit is connected to the 12th pin of relay K32; B of the CAN unit is connected to the 12th pin of relay K33; C of the CAN unit is connected to the 12th pin of relay K34; D of the CAN unit is connected to the 12th pin of relay K35; E of the CAN unit is connected to the 12th pin of relay K36; F of the CAN unit is connected to the 12th pin of relay K37.
[0009] A further technical solution is that the main chassis circuit further includes relays K28, K29, K47, K48, K49, and K50; both PL6_d6 and PL6_d8 of the main chassis control chip are connected to the 4th pin of relay K47, and the 9th pin of relay K47 is connected to OPEN_SUPLLY of signal system SIG; both PL6_z6 and PL6_z8 of the main chassis control chip are connected to the 1st pin of relay K48, and the 9th pin of relay K48 is connected to OPEN_SW- of signal system SIG; both PL6_d10 and PL6_d12 of the main chassis control chip are connected to the 4th pin of relay K49, and the 9th pin of relay K49 is connected to CLOSE_SUPLLY of signal system SIG; both PL6_z10 and PL6_z12 of the main chassis control chip are connected to the 1st pin of relay K50, and the 9th pin of relay K50 is connected to CLOSE_SW- of signal system SIG; the 1st pin of relay K47 and the 1st pin of relay K49 are both connected to the 12th pin of relay K43; the 5th pin of relay K48 and the 5th pin of relay K50 are both connected to the 12th pin of relay K46; the 12th pin of relay K47 is connected to OPEN_SW+ of signal system SIG; the 12th pin of relay K48 is connected to OPEN_RTN of signal system SIG; the 12th pin of relay K49 is connected to CLOSE_SW+ of signal system SIG; the 12th pin of relay K50 is connected to CLOSE_RTN of signal system SIG; PL8_z2 of the main chassis control chip is connected to the 1st pin of relay K28; both PL8_z18 and PL8_z30 of the main chassis control chip are connected to the 4th pin of relay K28, the 9th pin of relay K28 is connected to CLOSED_60VDC of signal system SIG, and the 12th pin of relay K28 is connected to CLOSE_SW+ of signal system SIG; PL8_z22 of the main chassis control chip is connected to the 1st pin of relay K29; PL8_z6 of the main chassis control chip is connected to the 4th pin of relay K29; the 9th pin of relay K28 is connected to CLOSE_SW- of signal system SIG, and the 12th pin of relay K29 is connected to CLOSED_0VDC of signal system SIG.
[0010] A further technical solution is as follows: The comprehensive monitoring module includes an ISCS comprehensive monitoring unit, a MODBUS communication unit, a PSA monitoring unit, and relays K22, K23, K24, K25, K26, and K27. The GND of the ISCS comprehensive monitoring unit is connected to the 11th pin of relay K24 and the 11th pin of relay K27. The 14th pin of relay K24 is connected to SK3_1 of the logic control unit PEDC, and the 12th pin of relay K24 is connected to the 5th pin of the MODBUS communication unit. The 14th pin of relay K27 is connected to SK3_5 of the main chassis control chip. The B- of the ISCS comprehensive monitoring unit is connected to the 11th pin of relay K23 and the 11th pin of relay K26. The 14th pin of relay K23 is connected to SK3_3 of the logic control unit PEDC, and the 12th pin of relay K23 is connected to the 3rd pin of the MODBUS communication unit. The 14th pin of relay K26 is connected to SK3_3 of the main chassis control chip. The A+ of the ISCS comprehensive monitoring unit is connected to the 11th pin of relay K22 and the 11th pin of relay K25. The 14th pin of relay K22 is connected to SK3_7 of the logic control unit PEDC, and the 12th pin of relay K22 is connected to the 1st pin of the MODBUS communication unit. The 14th pin of relay K25 is connected to SK3_2 of the main chassis control chip. The L of the PSA monitoring unit is connected to the L of the fourth input power supply. The N of the PSA monitoring unit is connected to the N of the fourth input power supply. The CH1 of the PSA monitoring unit is connected to SK5 of the main chassis control chip.
[0011] A further technical solution is as follows: SK8_1 of the main chassis control chip is connected to SK4_8 of the logic control unit PEDC; SK8_5 of the main chassis control chip is connected to SK4_3 of the logic control unit PEDC; SK8_4 of the main chassis control chip is connected to SK4_5 of the logic control unit PEDC; SK8_2 of the main chassis control chip is connected to SK4_2 of the logic control unit PEDC; SK8_3 of the main chassis control chip is connected to SK4_7 of the logic control unit PEDC; SK8_8 of the main chassis control chip is connected to SK4_1 of the logic control unit PEDC; SK8_3 of the main chassis control chip is connected to SK4_5 of the logic control unit PEDC; SK8_5 of the main chassis control chip is connected to SK4_4 of the logic control unit PEDC; SK8_2 of the main chassis control chip is connected to SK4_2 of the logic control unit PEDC; SK8_7 of the main chassis control chip is connected to SK4_3 of the logic control unit PEDC.
[0012] A further technical solution is as follows: The main chassis circuit further includes relays K17, K18, K19, K20, and K21; TB1_5 of the integrated backup panel IBP is connected to the 11th pin of relay K17, and the 12th pin of relay K17 is connected to both PL3_z4 and PL5_d4 of the main chassis control chip; TB1_4 of the integrated backup panel IBP is connected to the 11th pin of relay K18, and the 12th pin of relay K18 is connected to PL5_d6 of the main chassis control chip; TB1_3 of the integrated backup panel IBP is connected to the 11th pin of relay K19, and the 12th pin of relay K19 is connected to PL5_d18 of the main chassis control chip; TB1_8 of the integrated backup panel IBP is connected to PL5_z18 of the main chassis control chip; TB1_7 of the integrated backup panel IBP is connected to the 11th pin of relay K20, and the 12th pin of relay K20 is connected to PL5_d8 of the main chassis control chip; TB1_9 of the integrated backup panel IBP is connected to the 11th pin of relay K21, and the 12th pin of relay K21 is connected to PL7_d8 of the main chassis control chip.
[0013] A further technical solution is as follows: The main chassis circuit further includes relays K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11, and K16; TB2_6 of the end control panel PSL is connected to both PL3_z12 and PL5_z2 of the main chassis control chip; TB2_12 of the end control panel PSL is connected to the 11th pin of relay K4, and the 12th pin of relay K4 is connected to the 12th pin of relay K20; TB2_10 of the end control panel PSL is connected to the 11th pin of relay K5, and the 12th pin of relay K5 is connected to PL7_z4 of the main chassis control chip; TB2_9 of the end control panel PSL is connected to the 11th pin of relay K6, and the 12th pin of relay K6 is connected to PL7_b4 of the main chassis control chip; TB1_2 of the end control panel PSL is connected to the 11th pin of relay K1, and the 12th pin of relay K1 is connected to PL5_d2 of the main chassis control chip; TB2_7 of the end control panel PSL is connected to the 11th pin of relay K9, and the 12th pin of relay K9 is connected to PL7_d4 of the main chassis control chip; TB2_8 of the end control panel PSL is connected to the 11th pin of relay K10, and the 12th pin of relay K10 is connected to PL7_z8 of the main chassis control chip; TB2_11 of the end control panel PSL is connected to the 11th pin of relay K11, and the 12th pin of relay K11 is connected to PL7_b8 of the main chassis control chip; TB2_5 of the end control panel PSL is connected to the 11th pin of relay K16, and the 12th pin of relay K16 is connected to PL5_d10 of the main chassis control chip; TB1_1 of the end control panel PSL is connected to the 11th pin of relay K3, and the 12th pin of relay K3 is connected to PL3_z4 of the main chassis control chip; TB1_4 of the end control panel PSL is connected to the 11th pin of relay K2, and the 12th pin of relay K2 is connected to PL3_z4 of the main chassis control chip; TB1_10 of the end control panel PSL is connected to the 11th pin of relay K7, and the 12th pin of relay K7 is connected to PL5_d12 of the main chassis control chip; TB1_11 of the end control panel PSL is connected to the 11th pin of relay K8, and the 12th pin of relay K8 is connected to PL5_d14 of the main chassis control chip.
[0014] A further technical solution is as follows: The logic control unit LCU further includes a sub-chassis circuit; the sub-chassis circuit includes a sub-chassis control chip; PL1_z2, PL1_z4, PL1_z22, and PL1_z24 of the sub-chassis control chip are all connected to L1 of the IBP power supply; PL1_z8, PL1_z10, PL1_z28, and PL1_z30 of the sub-chassis control chip are all connected to N1 of the IBP power supply; PL3_d14 of the sub-chassis control chip is connected to PL7_z12 of the sub-chassis control chip; PL3_d18 of the sub-chassis control chip is connected to PL7_b12 of the sub-chassis control chip; PL3_d20 of the sub-chassis control chip is connected to PL7_d12 of the sub-chassis control chip; PL3_d22 of the sub-chassis control chip is connected to PL7_z18 of the sub-chassis control chip; PL4_z12 of the sub-chassis control chip is connected to PL6_d14 of the sub-chassis control chip; PL4_b12 of the sub-chassis control chip is connected to PL6_d18 of the sub-chassis control chip; PL4_d12 of the sub-chassis control chip is connected to PL6_d20 of the sub-chassis control chip; PL4_z18 of the sub-chassis control chip is connected to PL6_d22 of the sub-chassis control chip; PL3_z32 of the sub-chassis control chip is connected to PL3_d14 of the sub-chassis control chip; PL4_z32 of the sub-chassis control chip is connected to PL3_z14 of the sub-chassis control chip; PL4_z26 of the sub-chassis control chip is connected to PL3_z6 of the sub-chassis control chip; PL3_d6 and PL3_d8 of the sub-chassis control chip are both connected to the 4th pin of the relay K47; PL3_z6 and PL3_z8 of the sub-chassis control chip are both connected to the 1st pin of the relay K47; PL3_d10 and PL3_d12 of the sub-chassis control chip are both connected to the 4th pin of the relay K49; PL3_z10 and PL3_z12 of the sub-chassis control chip are both connected to the 1st pin of the relay K50; PL3_d2 and PL3_d4 of the sub-chassis control chip are both connected to the 12th pin of the relay K44; PL3_z2 and PL3_z4 of the sub-chassis control chip are both connected to the 12th pin of the relay K45; PL2_d28 of the sub-chassis control chip is connected to the 1st pin of the relay K38; PL2_d30 of the sub-chassis control chip is connected to the 12th pin of the relay K41; PL2_d32 of the sub-chassis control chip is connected to the 12th pin of the relay K42; PL5_z2 of the sub-chassis control chip is connected to the 1st pin of the relay K28; PL5_z18 and PL5_z26 of the sub-chassis control chip are both connected to the 4th pin of the relay K28; PL5_z6 of the sub-chassis control chip is connected to the 4th pin of the relay K29; PL5_z22 of the sub-chassis control chip is connected to the 1st pin of the relay K29; PL5_z6 of the sub-chassis control chip is connected to the 4th pin of the relay K29;The PL7_z18 of the secondary chassis control chip is connected to the 1st pin of the relay K30; the PL7_z22 of the secondary chassis control chip is connected to the 4th pin of the relay K30; the PL7_z26 of the secondary chassis control chip is connected to the 1st pin of the relay K31.
[0015] A further technical solution is that: both PL6_z2 and PL6_z10 of the secondary chassis control chip are connected to L1 of the door head enable power supply; both PL6_z6 and PL6_z14 of the secondary chassis control chip are connected to L2 of the door head enable power supply; PL2_z2 of the secondary chassis control chip is connected to TB2_6 of the end control panel PSL; PL2_d2 of the secondary chassis control chip is connected to the 12th pin of the relay K1; PL2_d4 of the secondary chassis control chip is connected to the 12th pin of the relay K3; PL2_d6 of the secondary chassis control chip is connected to the 12th pin of the relay K18; PL2_d8 of the secondary chassis control chip is connected to the 12th pin of the relay K20; PL2_d10 of the secondary chassis control chip is connected to the 12th pin of the relay K16; PL2_z12 of the secondary chassis control chip is connected to TB1_8 of the end control panel PSL; PL2_d12 of the secondary chassis control chip is connected to the 12th pin of the relay K7; PL2_d14 of the secondary chassis control chip is connected to the 12th pin of the relay K8; PL2_d18 of the secondary chassis control chip is connected to the 12th pin of the relay K19; PL4_z4 of the secondary chassis control chip is connected to the 12th pin of the relay K5; PL4_b4 of the secondary chassis control chip is connected to the 12th pin of the relay K6; PL4_d4 of the secondary chassis control chip is connected to the 12th pin of the relay K9; PL4_z8 of the secondary chassis control chip is connected to the 12th pin of the relay K10; PL4_b8 of the secondary chassis control chip is connected to the 12th pin of the relay K11; PL4_d8 of the secondary chassis control chip is connected to the 12th pin of the relay K21.
[0016] Compared with the prior art, the beneficial effects of the present utility model are:
[0017] Effectively solve the problem that the single-side platform door cannot be opened or closed due to the failure of the internal relay of the PEDC, achieving the purpose of reducing the equipment failure rate and ensuring the normal train operation order. Description of the Drawings
[0018] Figure 1 It is a schematic diagram of the electrical block diagram of a rail transit platform door control system in this embodiment;
[0019] Figure 2 It is a circuit structure topology diagram of the door controller DCU for a rail transit platform door control system in this embodiment;
[0020] Figure 3It is the circuit structure topology diagram of a signal system SIG for a rail transit platform screen door control system in this embodiment;
[0021] Figure 4 It is the structure topology diagram of the main chassis circuit for a rail transit platform screen door control system in this embodiment;
[0022] Figure 5 It is the structure topology diagram of the auxiliary chassis circuit for a rail transit platform screen door control system in this embodiment;
[0023] Figure 6 It is the circuit structure topology diagram of the door head enabling power supply for a rail transit platform screen door control system in this embodiment;
[0024] Figure 7 It is the circuit structure topology diagram of the end control panel PSL for a rail transit platform screen door control system in this embodiment;
[0025] Figure 8 It is the circuit structure topology diagram of the integrated backup panel IBP for a rail transit platform screen door control system in this embodiment;
[0026] Figure 9 It is the circuit structure topology diagram of the integrated monitoring module for a rail transit platform screen door control system in this embodiment. Specific implementation mode
[0027] The present utility model will be further described below in conjunction with the accompanying drawings. Specific implementation mode:
[0029] Embodiment 1
[0030] This embodiment provides a rail transit platform screen door control system, as Figure 1As shown, it includes a Logic Control Unit (LCU), a Platform Screen Door Local Control Panel (PSL), an Integrated Backup Panel (IBP), a Signaling System (SIG), a Door Control Unit (DCU), and an Integrated Monitoring Module. The power input terminal of the Logic Control Unit (LCU) is connected to a first input power supply; the power input terminal of the Platform Screen Door Local Control Panel (PSL) is connected to a second input power supply, and the Platform Screen Door Local Control Panel (PSL) is connected to the Logic Control Unit (LCU); the power input terminal of the Integrated Backup Panel (IBP) is connected to the second input power supply, and the Integrated Backup Panel (IBP) is connected to both the Logic Control Unit (LCU) and the Platform Screen Door Local Control Panel (PSL); the power input terminal of the Signaling System (SIG) is connected to a third input power supply, and the Signaling System (SIG) is connected to the Logic Control Unit (LCU), the Platform Screen Door Local Control Panel (PSL), and the Integrated Backup Panel (IBP); the Door Control Unit (DCU) is connected to the Logic Control Unit (LCU), the Platform Screen Door Local Control Panel (PSL), and the Integrated Backup Panel (IBP); the power input terminal of the Integrated Monitoring Module is connected to a fourth input power supply, and the Integrated Monitoring Module is connected to the Logic Control Unit (LCU).
[0031] Exemplarily, during the implementation process, the first input power supply is AC110V, the second input power supply is DC24V, the third input power supply is DC60V, and the fourth input power supply is AC220V. Among them, both the second input power supply and the third input power supply can be obtained by converting the first input power supply using a DCDC power module in the prior art. The connection method of the DCDC power module is the prior art and will not be elaborated here. For example, a DCDC power module of model EDR-120-24 can be used to convert the first input power supply to obtain the second input power supply, and a DCDC power module of model EDR-120-60 can be used to convert the first input power supply to obtain the third input power supply.
[0032] The Platform Screen Door Local Control Panel (PSL), the Integrated Backup Panel (IBP), the Signaling System (SIG), the Door Control Unit (DCU), and the Integrated Monitoring Module all adopt existing products. Among them, the Door Control Unit (DCU) can adopt an existing product of model D85965 / 016.
[0033] Among them, the Logic Control Unit (LCU) serves as the core of the entire platform screen door control system, responsible for processing signals from various interface devices, performing logical judgments, and issuing control instructions to ensure that the platform screen doors open, close, and maintain their states according to predetermined rules.
[0034] The Platform Screen Door Local Control Panel (PSL) is located at the end of the platform, providing staff (such as platform attendants) with the ability to perform on-site operations when necessary, such as manually opening and closing doors, releasing interlocks to receive and send trains, etc. The Platform Screen Door Local Control Panel (PSL) is directly connected to the Logic Control Unit (LCU) to ensure that local control commands can be transmitted to the LCU in a timely manner.
[0035] The Integrated Backup Panel (IBP) serves as an emergency backup control device. When the main control system fails or in an emergency, the IBP allows operators to quickly activate preset emergency procedures, such as opening all platform screen doors with one key, to ensure passenger safety and the continuity of train operation. The IBP is dually connected to the Logic Control Unit (LCU) and the Platform Side Controller (PSL), enhancing the redundancy and emergency response capabilities of the system.
[0036] The Signaling System (SIG) is closely integrated with the Logic Control Unit (LCU) and is used to receive information such as train positioning, approach speed, and docking position, ensuring the precise synchronization of the opening and closing of platform screen doors and train doors, and achieving train-ground linkage.
[0037] Door Control Units (DCUs) are distributed at each platform screen door, responsible for receiving instructions sent by the Logic Control Unit (LCU) and driving the actual movement of the platform screen doors, while feeding back the door body status (such as open / closed position, fault alarm, etc.) to the Logic Control Unit (LCU).
[0038] The Integrated Monitoring Module interfaces with the Logic Control Unit (LCU), real-time collects the operation data and status information of the platform screen door system, conducts centralized display, recording, and remote monitoring, facilitating maintenance personnel to promptly discover and handle problems, and improving the maintenance efficiency and fault diagnosis capabilities of the system.
[0039] Embodiment 2
[0040] Such as Figure 4 Combined with Figure 6As shown, on the basis of the above-mentioned Embodiment 1, the logic control unit LCU in this embodiment includes a main chassis circuit; the main chassis circuit includes a main chassis control chip, relays K38, K40, K41, and K42; the PL5_d32 of the main chassis control chip is connected to the 12th pin of relay K42, and the 11th pin of relay K42 is connected to the first input power supply; the PL5_d30 of the main chassis control chip is connected to the 12th pin of relay K41, and the 11th pin of relay K41 is connected to the control power supply; the PL5_d28 of the main chassis control chip is connected to the 1st pin of relay K38; the PL9_z2 and z10 of the main chassis control chip are both connected to L1 of the door header enable power supply; the PL9_z6 and PL9_z14 of the main chassis control chip are both connected to L2 of the door header enable power supply; the PL3_d2 of the main chassis control chip is connected to both the 5th pin of relay K38 and the 12th pin of relay K40, the 8th pin of relay K38 is connected to the 14th pin of relay K40, the 9th and 12th pins of relay K38 are connected to the drive power supply, and the 11th pin of relay K40 is respectively connected to the first input power supply and the control power supply; the PL4_z2, PL4_z4, PL4_z22, and PL4_z24 of the main chassis control chip are all connected to L1 of the PEDC power supply; the PL4_z8, PL4_z10, PL4_z28, and PL4_z30 of the main chassis control chip are all connected to N1 of the PEDC power supply; the PL1_z2, PL1_z4, PL1_z22, and PL1_z24 of the main chassis control chip are all connected to L1 of the indicator light power supply; the PL1_z8, PL1_z10, PL1_z28, and PL1_z30 of the main chassis control chip are all connected to N1 of the indicator light power supply.
[0041] Exemplarily, during implementation, the control power supply, drive power supply, and first input power supply (main power supply) all adopt DC110V. The main chassis control chip can adopt an existing processor chip of model PGC2K.
[0042] Embodiment 3
[0043] As Figure 2As shown in the figure, on the basis of the above-mentioned Embodiment 2, the main chassis circuit in this embodiment further includes a CAN unit, relays K30, K31, K32, K33, K34, K35, K36, K37, K43, K44, K45 and K46; the SK9_9 pin of the main chassis control chip is connected to the 14th pin of relay K37, and the 11th pin of relay K37 is connected to CAN2_COM of the door controller DCU; the SK9_8 pin of the main chassis control chip is connected to the 14th pin of relay K36, and the 11th pin of relay K36 is connected to CAN2_L of the door controller DCU; the SK9_4 pin of the main chassis control chip is connected to the 14th pin of relay K35, and the 11th pin of relay K35 is connected to CAN2_H of the door controller DCU; the SK9_7 pin of the main chassis control chip is connected to the 14th pin of relay K34, and the 11th pin of relay K34 is connected to CAN1_COM of the door controller DCU; the SK9_6 pin of the main chassis control chip is connected to the 14th pin of relay K33, and the 11th pin of relay K33 is connected to CAN1_L of the door controller DCU; the SK9_2 pin of the main chassis control chip is connected to the 14th pin of relay K32, and the 11th pin of relay K32 is connected to CAN1_H of the door controller DCU; PL10_z18 of the main chassis control chip is connected to the 1st pin of relay K30; PL10_z22 of the main chassis control chip is connected to the 4th pin of relay K30, the 9th pin of relay K30 is connected to ENABLE_L1 of the door controller DCU, and the 12th pin of relay K30 is connected to ENABLE_L2 of the door controller DCU; PL10_z26 of the main chassis control chip is connected to the 1st pin of relay K31, and the 9th pin of relay K31 is connected to OPEN_L1 of the door controller DCU; PL3_z20 of the main chassis control chip is connected to the 12th pin of relay K43, and the 11th pin of relay K43 is connected to SUPLLY of the door controller DCU; PL3_z32 of the main chassis control chip is connected to the 12th pin of relay K46, and the 11th pin of relay K46 is connected to RETURN of the door controller DCU; PL6_d2 and PL6_d4 of the main chassis control chip are both connected to the 12th pin of relay K44, and the 11th pin of relay K44 is connected to SW+ of the door controller DCU; PL6_z2 and PL6_z4 of the main chassis control chip are both connected to the 12th pin of relay K45, and the 11th pin of relay K45 is connected to SW- of the door controller DCU; A of the CAN unit is connected to the 12th pin of relay K32; B of the CAN unit is connected to the 12th pin of relay K33; C of the CAN unit is connected to the 12th pin of relay K34; D of the CAN unit is connected to the 12th pin of relay K35; E of the CAN unit is connected to the 12th pin of relay K36; F of the CAN unit is connected to the 12th pin of relay K37.
[0044] Example 4
[0045] As Figure 3 shown, on the basis of the above-mentioned Embodiment 3, the main chassis circuit in this embodiment further includes relays K28, K29, K47, K48, K49, and K50; both PL6_d6 and PL6_d8 of the main chassis control chip are connected to the 4th pin of relay K47, and the 9th pin of relay K47 is connected to OPEN_SUPLLY of signal system SIG; both PL6_z6 and PL6_z8 of the main chassis control chip are connected to the 1st pin of relay K48, and the 9th pin of relay K48 is connected to OPEN_SW- of signal system SIG; both PL6_d10 and PL6_d12 of the main chassis control chip are connected to the 4th pin of relay K49, and the 9th pin of relay K49 is connected to CLOSE_SUPLLY of signal system SIG; both PL6_z10 and PL6_z12 of the main chassis control chip are connected to the 1st pin of relay K50, and the 9th pin of relay K50 is connected to CLOSE_SW- of signal system SIG; the 1st pin of relay K47 and the 1st pin of relay K49 are both connected to the 12th pin of relay K43; the 5th pin of relay K48 and the 5th pin of relay K50 are both connected to the 12th pin of relay K46; the 12th pin of relay K47 is connected to OPEN_SW+ of signal system SIG; the 12th pin of relay K48 is connected to OPEN_RTN of signal system SIG; the 12th pin of relay K49 is connected to CLOSE_SW+ of signal system SIG; the 12th pin of relay K50 is connected to CLOSE_RTN of signal system SIG; PL8_z2 of the main chassis control chip is connected to the 1st pin of relay K28; both PL8_z18 and PL8_z30 of the main chassis control chip are connected to the 4th pin of relay K28, the 9th pin of relay K28 is connected to CLOSED_60VDC of signal system SIG, and the 12th pin of relay K28 is connected to CLOSE_SW+ of signal system SIG; PL8_z22 of the main chassis control chip is connected to the 1st pin of relay K29; PL8_z6 of the main chassis control chip is connected to the 4th pin of relay K29; the 9th pin of relay K28 is connected to CLOSE_SW- of signal system SIG, and the 12th pin of relay K29 is connected to CLOSED_0VDC of signal system SIG.
[0046] Example 5
[0047] As Figure 9As shown, on the basis of the above-mentioned Embodiment 2, in this embodiment, the comprehensive monitoring module includes an ISCS comprehensive monitoring unit, a MODBUS communication unit, a PSA monitoring unit, and relays K22, K23, K24, K25, K26, and K27; the GND of the ISCS comprehensive monitoring unit is connected to the 11th pin of relay K24 and the 11th pin of relay K27. The 14th pin of relay K24 is connected to SK3_1 of the logic control unit PEDC, and the 12th pin of relay K24 is connected to the 5th pin of the MODBUS communication unit. The 14th pin of relay K27 is connected to SK3_5 of the main chassis control chip; the B- of the ISCS comprehensive monitoring unit is connected to the 11th pin of relay K23 and the 11th pin of relay K26. The 14th pin of relay K23 is connected to SK3_3 of the logic control unit PEDC, and the 12th pin of relay K23 is connected to the 3rd pin of the MODBUS communication unit. The 14th pin of relay K26 is connected to SK3_3 of the main chassis control chip; the A+ of the ISCS comprehensive monitoring unit is connected to the 11th pin of relay K22 and the 11th pin of relay K25. The 14th pin of relay K22 is connected to SK3_7 of the logic control unit PEDC, and the 12th pin of relay K22 is connected to the 1st pin of the MODBUS communication unit. The 14th pin of relay K25 is connected to SK3_2 of the main chassis control chip; the L of the PSA monitoring unit is connected to the L of the fourth input power supply; the N of the PSA monitoring unit is connected to the N of the fourth input power supply; the CH1 of the PSA monitoring unit is connected to SK5 of the main chassis control chip. Among them, the logic control unit PEDC can be an existing product with the model number D85993 / 001.
[0048] Embodiment 6
[0049] As Figure 9 shown, on the basis of the above-mentioned Embodiment 5, in this embodiment, SK8_1 of the main chassis control chip is connected to SK4_8 of the logic control unit PEDC; SK8_5 of the main chassis control chip is connected to SK4_3 of the logic control unit PEDC; SK8_4 of the main chassis control chip is connected to SK4_5 of the logic control unit PEDC; SK8_2 of the main chassis control chip is connected to SK4_2 of the logic control unit PEDC; SK8_3 of the main chassis control chip is connected to SK4_7 of the logic control unit PEDC; SK8_8 of the main chassis control chip is connected to SK4_1 of the logic control unit PEDC; SK8_3 of the main chassis control chip is connected to SK4_5 of the logic control unit PEDC; SK8_5 of the main chassis control chip is connected to SK4_4 of the logic control unit PEDC; SK8_2 of the main chassis control chip is connected to SK4_2 of the logic control unit PEDC; SK8_7 of the main chassis control chip is connected to SK4_3 of the logic control unit PEDC.
[0050] Example 7
[0051] As Figure 8 shown, on the basis of the above-mentioned Embodiment 4, the main chassis circuit in this embodiment further includes relays K17, K18, K19, K20 and K21; TB1_5 of the integrated backup panel IBP is connected to the 11th pin of relay K17, and the 12th pin of relay K17 is connected to both PL3_z4 and PL5_d4 of the main chassis control chip; TB1_4 of the integrated backup panel IBP is connected to the 11th pin of relay K18, and the 12th pin of relay K18 is connected to PL5_d6 of the main chassis control chip; TB1_3 of the integrated backup panel IBP is connected to the 11th pin of relay K19, and the 12th pin of relay K19 is connected to PL5_d18 of the main chassis control chip; TB1_8 of the integrated backup panel IBP is connected to PL5_z18 of the main chassis control chip; TB1_7 of the integrated backup panel IBP is connected to the 11th pin of relay K20, and the 12th pin of relay K20 is connected to PL5_d8 of the main chassis control chip; TB1_9 of the integrated backup panel IBP is connected to the 11th pin of relay K21, and the 12th pin of relay K21 is connected to PL7_d8 of the main chassis control chip.
[0052] Example 8
[0053] As Figure 7As shown, on the basis of the above-mentioned Embodiment 7, the main chassis circuit in this embodiment further includes relays K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11 and K16; TB2_6 of the end control panel PSL is connected to both PL3_z12 and PL5_z2 of the main chassis control chip; TB2_12 of the end control panel PSL is connected to the 11th pin of relay K4, and the 12th pin of relay K4 is connected to the 12th pin of relay K20; TB2_10 of the end control panel PSL is connected to the 11th pin of relay K5, and the 12th pin of relay K5 is connected to PL7_z4 of the main chassis control chip; TB2_9 of the end control panel PSL is connected to the 11th pin of relay K6, and the 12th pin of relay K6 is connected to PL7_b4 of the main chassis control chip; TB1_2 of the end control panel PSL is connected to the 11th pin of relay K1, and the 12th pin of relay K1 is connected to PL5_d2 of the main chassis control chip; TB2_7 of the end control panel PSL is connected to the 11th pin of relay K9, and the 12th pin of relay K9 is connected to PL7_d4 of the main chassis control chip; TB2_8 of the end control panel PSL is connected to the 11th pin of relay K10, and the 12th pin of relay K10 is connected to PL7_z8 of the main chassis control chip; TB2_11 of the end control panel PSL is connected to the 11th pin of relay K11, and the 12th pin of relay K11 is connected to PL7_b8 of the main chassis control chip; TB2_5 of the end control panel PSL is connected to the 11th pin of relay K16, and the 12th pin of relay K16 is connected to PL5_d10 of the main chassis control chip; TB1_1 of the end control panel PSL is connected to the 11th pin of relay K3, and the 12th pin of relay K3 is connected to PL3_z4 of the main chassis control chip; TB1_4 of the end control panel PSL is connected to the 11th pin of relay K2, and the 12th pin of relay K2 is connected to PL3_z4 of the main chassis control chip; TB1_10 of the end control panel PSL is connected to the 11th pin of relay K7, and the 12th pin of relay K7 is connected to PL5_d12 of the main chassis control chip; TB1_11 of the end control panel PSL is connected to the 11th pin of relay K8, and the 12th pin of relay K8 is connected to PL5_d14 of the main chassis control chip.
[0054] Embodiment 9
[0055] As Figure 5As shown, on the basis of the above-mentioned Embodiment 8, the logic control unit LCU in this embodiment further includes a sub-chassis circuit; the sub-chassis circuit includes a sub-chassis control chip; PL1_z2, PL1_z4, PL1_z22, and PL1_z24 of the sub-chassis control chip are all connected to L1 of the IBP power supply; PL1_z8, PL1_z10, PL1_z28, and PL1_z30 of the sub-chassis control chip are all connected to N1 of the IBP power supply; PL3_d14 of the sub-chassis control chip is connected to PL7_z12 of the sub-chassis control chip; PL3_d18 of the sub-chassis control chip is connected to PL7_b12 of the sub-chassis control chip; PL3_d20 of the sub-chassis control chip is connected to PL7_d12 of the sub-chassis control chip; PL3_d22 of the sub-chassis control chip is connected to PL7_z18 of the sub-chassis control chip; PL4_z12 of the sub-chassis control chip is connected to PL6_d14 of the sub-chassis control chip; PL4_b12 of the sub-chassis control chip is connected to PL6_d18 of the sub-chassis control chip; PL4_d12 of the sub-chassis control chip is connected to PL6_d20 of the sub-chassis control chip; PL4_z18 of the sub-chassis control chip is connected to PL6_d22 of the sub-chassis control chip; PL3_z32 of the sub-chassis control chip is connected to PL3_d14 of the sub-chassis control chip; PL4_z32 of the sub-chassis control chip is connected to PL3_z14 of the sub-chassis control chip; PL4_z26 of the sub-chassis control chip is connected to PL3_z6 of the sub-chassis control chip; PL3_d6 and PL3_d8 of the sub-chassis control chip are both connected to the 4th pin of relay K47; PL3_z6 and PL3_z8 of the sub-chassis control chip are both connected to the 1st pin of relay K47; PL3_d10 and PL3_d12 of the sub-chassis control chip are both connected to the 4th pin of relay K49; PL3_z10 and PL3_z12 of the sub-chassis control chip are both connected to the 1st pin of relay K50; PL3_d2 and PL3_d4 of the sub-chassis control chip are both connected to the 12th pin of relay K44; PL3_z2 and PL3_z4 of the sub-chassis control chip are both connected to the 12th pin of relay K45; PL2_d28 of the sub-chassis control chip is connected to the 1st pin of relay K38; PL2_d30 of the sub-chassis control chip is connected to the 12th pin of relay K41; PL2_d32 of the sub-chassis control chip is connected to the 12th pin of relay K42; PL5_z2 of the sub-chassis control chip is connected to the 1st pin of relay K28; PL5_z18 and PL5_z26 of the sub-chassis control chip are both connected to the 4th pin of relay K28; PL5_z6 of the sub-chassis control chip is connected to the 4th pin of relay K29; PL5_z22 of the sub-chassis control chip is connected to the 1st pin of relay K29; PL5_z6 of the sub-chassis control chip is connected to the 4th pin of relay K29;The PL7_z18 of the secondary chassis control chip is connected to the 1st pin of the relay K30; the PL7_z22 of the secondary chassis control chip is connected to the 4th pin of the relay K30; the PL7_z26 of the secondary chassis control chip is connected to the 1st pin of the relay K31.;
[0056] Exemplarily, during implementation, the secondary chassis control chip can also adopt an existing processor chip of model PGC2K.
[0057] Embodiment 10
[0058] As Figure 5 Combined with Figure 6 As shown, on the basis of the above Embodiment 9, in this embodiment, the PL6_z2 and PL6_z10 of the secondary chassis control chip are both connected to L1 of the door head enabling power supply; the PL6_z6 and PL6_z14 of the secondary chassis control chip are both connected to L2 of the door head enabling power supply; the PL2_z2 of the secondary chassis control chip is connected to TB2_6 of the end control panel PSL; the PL2_d2 of the secondary chassis control chip is connected to the 12th pin of the relay K1; the PL2_d4 of the secondary chassis control chip is connected to the 12th pin of the relay K3; the PL2_d6 of the secondary chassis control chip is connected to the 12th pin of the relay K18; the PL2_d8 of the secondary chassis control chip is connected to the 12th pin of the relay K20; the PL2_d10 of the secondary chassis control chip is connected to the 12th pin of the relay K16; the PL2_z12 of the secondary chassis control chip is connected to TB1_8 of the end control panel PSL; the PL2_d12 of the secondary chassis control chip is connected to the 12th pin of the relay K7; the PL2_d14 of the secondary chassis control chip is connected to the 12th pin of the relay K8; the PL2_d18 of the secondary chassis control chip is connected to the 12th pin of the relay K19; the PL4_z4 of the secondary chassis control chip is connected to the 12th pin of the relay K5; the PL4_b4 of the secondary chassis control chip is connected to the 12th pin of the relay K6; the PL4_d4 of the secondary chassis control chip is connected to the 12th pin of the relay K9; the PL4_z8 of the secondary chassis control chip is connected to the 12th pin of the relay K10; the PL4_b8 of the secondary chassis control chip is connected to the 12th pin of the relay K11; the PL4_d8 of the secondary chassis control chip is connected to the 12th pin of the relay K21.
[0059] The working principle of this rail transit platform door control system:
[0060] After the Logic Control Unit (LCU) receives the door opening or closing instruction sent by the Signal System (SIG), the LCU sends the door opening or closing instruction to the Door Control Units (DCUs) of all doors to perform the door opening or closing operation. At the same time, the DCUs feedback the door status to the LCU, and the LCU feeds back the operation data and status information of the platform door system to the Integrated Monitoring Module. When the main chassis of the LCU cannot work, the slave chassis takes over the work of the main chassis to achieve the master-slave redundancy function.
[0061] The Logic Control Unit (LCU) of this rail transit platform door control system includes a main chassis circuit and a slave chassis circuit, achieving power redundancy, controller redundancy, IO redundancy, and network redundancy, effectively solving the problem that the single-sided platform doors cannot be opened or closed due to the failure of the internal relay of the PEDC, and achieving the purpose of reducing the equipment failure rate and ensuring the normal train operation order.
[0062] In this specification, the so-called "one embodiment", "another embodiment", "embodiment", etc. refer to the specific features, structures or characteristics described in connection with this embodiment being included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in connection with any embodiment, it is intended that the implementation of such feature, structure or characteristic in combination with other embodiments also falls within the scope of the present invention.
[0063] Although the present invention has been described herein with reference to multiple illustrative embodiments of the present invention, it should be understood that those skilled in the art can design many other modifications and implementation manners, which will fall within the scope of the principles and spirit disclosed in this application. More specifically, within the scope of the disclosure, drawings and claims of this application, various variations and improvements can be made to the components and / or layout of the subject combination layout. In addition to the variations and improvements made to the components and / or layout, other uses will also be obvious to those skilled in the art.
Claims
1. A platform door control system for rail transit, characterized in that, Including: A logic control unit LCU, the power input terminal of the logic control unit LCU is connected to a first input power supply; A platform-side control panel PSL, the power input terminal of the platform-side control panel PSL is connected to a second input power supply, and the platform-side control panel PSL is connected to the logic control unit LCU; An integrated backup panel IBP, the power input terminal of the integrated backup panel IBP is connected to a second input power supply, and the integrated backup panel IBP is connected to both the logic control unit LCU and the platform-side control panel PSL; A signal system SIG, the power input terminal of the signal system SIG is connected to a third input power supply, and the signal system SIG is connected to both the logic control unit LCU, the platform-side control panel PSL, and the integrated backup panel IBP; A door controller DCU, the door controller DCU is connected to both the logic control unit LCU, the platform-side control panel PSL, and the integrated backup panel IBP; An integrated monitoring module, the power input terminal of the integrated monitoring module is connected to a fourth input power supply, and the integrated monitoring module is connected to the logic control unit LCU.
2. The rail transit platform door control system according to claim 1, characterized in that: The logic control unit LCU includes a main chassis circuit; The main chassis circuit includes a main chassis control chip, and relays K38, K40, K41, and K42; PL5_d32 of the main chassis control chip is connected to the 12th pin of relay K42, and the 11th pin of relay K42 is connected to the first input power supply; PL5_d30 of the main chassis control chip is connected to the 12th pin of relay K41, and the 11th pin of relay K41 is connected to the control power supply; PL5_d28 of the main chassis control chip is connected to the 1st pin of relay K38; Both PL9_z2 and z10 of the main chassis control chip are connected to L1 of the door head enabling power supply; both PL9_z6 and PL9_z14 of the main chassis control chip are connected to L2 of the door head enabling power supply; PL3_d2 of the main chassis control chip is connected to both the 5th pin of relay K38 and the 12th pin of relay K40, the 8th pin of relay K38 is connected to the 14th pin of relay K40, the 9th pin and the 12th pin of relay K38 are connected to the drive power supply, and the 11th pin of relay K40 is respectively connected to the first input power supply and the control power supply; PL4_z2, PL4_z4, PL4_z22, and PL4_z24 of the main chassis control chip are all connected to L1 of the PEDC power supply; PL4_z8, PL4_z10, PL4_z28, and PL4_z30 of the main chassis control chip are all connected to N1 of the PEDC power supply; PL1_z2, PL1_z4, PL1_z22, and PL1_z24 of the main chassis control chip are all connected to L1 of the indicator light power supply; PL1_z8, PL1_z10, PL1_z28, and PL1_z30 of the main chassis control chip are all connected to N1 of the indicator light power supply.
3. The rail transit platform door control system according to claim 2, characterized in that: The main chassis circuit further includes a CAN unit, relays K30, K31, K32, K33, K34, K35, K36, K37, K43, K44, K45, and K46; The pin SK9_9 of the main chassis control chip is connected to the 14th pin of relay K37, and the 11th pin of relay K37 is connected to CAN2_COM of the door controller DCU; the pin SK9_8 of the main chassis control chip is connected to the 14th pin of relay K36, and the 11th pin of relay K36 is connected to CAN2_L of the door controller DCU; the pin SK9_4 of the main chassis control chip is connected to the 14th pin of relay K35, and the 11th pin of relay K35 is connected to CAN2_H of the door controller DCU; the pin SK9_7 of the main chassis control chip is connected to the 14th pin of relay K34, and the 11th pin of relay K34 is connected to CAN1_COM of the door controller DCU; the pin SK9_6 of the main chassis control chip is connected to the 14th pin of relay K33, and the 11th pin of relay K33 is connected to CAN1_L of the door controller DCU; the pin SK9_2 of the main chassis control chip is connected to the 14th pin of relay K32, and the 11th pin of relay K32 is connected to CAN1_H of the door controller DCU; PL10_z18 of the main chassis control chip is connected to the 1st pin of relay K30; PL10_z22 of the main chassis control chip is connected to the 4th pin of relay K30, the 9th pin of relay K30 is connected to ENABLE_L1 of the door controller DCU, and the 12th pin of relay K30 is connected to ENABLE_L2 of the door controller DCU; PL10_z26 of the main chassis control chip is connected to the 1st pin of relay K31, and the 9th pin of relay K31 is connected to OPEN_L1 of the door controller DCU; PL3_z20 of the main chassis control chip is connected to the 12th pin of relay K43, and the 11th pin of relay K43 is connected to SUPLLY of the door controller DCU; PL3_z32 of the main chassis control chip is connected to the 12th pin of relay K46, and the 11th pin of relay K46 is connected to RETURN of the door controller DCU; Both PL6_d2 and PL6_d4 of the main chassis control chip are connected to the 12th pin of relay K44, and the 11th pin of relay K44 is connected to SW+ of the door controller DCU; both PL6_z2 and PL6_z4 of the main chassis control chip are connected to the 12th pin of relay K45, and the 11th pin of relay K45 is connected to SW- of the door controller DCU; A of the CAN unit is connected to the 12th pin of relay K32; B of the CAN unit is connected to the 12th pin of relay K33; C of the CAN unit is connected to the 12th pin of relay K34; D of the CAN unit is connected to the 12th pin of relay K35; E of the CAN unit is connected to the 12th pin of relay K36; F of the CAN unit is connected to the 12th pin of relay K37.
4. The rail transit platform screen door control system according to claim 3, characterized in that: The main chassis circuit further includes relays K28, K29, K47, K48, K49, and K50; Both PL6_d6 and PL6_d8 of the main chassis control chip are connected to the 4th pin of relay K47, and the 9th pin of relay K47 is connected to OPEN_SUPLLY of the signal system SIG; both PL6_z6 and PL6_z8 of the main chassis control chip are connected to the 1st pin of relay K48, and the 9th pin of relay K48 is connected to OPEN_SW- of the signal system SIG; both PL6_d10 and PL6_d12 of the main chassis control chip are connected to the 4th pin of relay K49, and the 9th pin of relay K49 is connected to CLOSE_SUPLLY of the signal system SIG; both PL6_z10 and PL6_z12 of the main chassis control chip are connected to the 1st pin of relay K50, and the 9th pin of relay K50 is connected to CLOSE_SW- of the signal system SIG; The 1st pin of relay K47 and the 1st pin of relay K49 are both connected to the 12th pin of relay K43; the 5th pin of relay K48 and the 5th pin of relay K50 are both connected to the 12th pin of relay K46; the 12th pin of relay K47 is connected to OPEN_SW+ of the signal system SIG; the 12th pin of relay K48 is connected to OPEN_RTN of the signal system SIG; the 12th pin of relay K49 is connected to CLOSE_SW+ of the signal system SIG; the 12th pin of relay K50 is connected to CLOSE_RTN of the signal system SIG; PL8_z2 of the main chassis control chip is connected to the 1st pin of relay K28; both PL8_z18 and PL8_z30 of the main chassis control chip are connected to the 4th pin of relay K28, the 9th pin of relay K28 is connected to CLOSED_60VDC of the signal system SIG, and the 12th pin of relay K28 is connected to CLOSE_SW+ of the signal system SIG; PL8_z22 of the main chassis control chip is connected to the 1st pin of relay K29; PL8_z6 of the main chassis control chip is connected to the 4th pin of relay K29; the 9th pin of relay K28 is connected to CLOSE_SW- of the signal system SIG, and the 12th pin of relay K29 is connected to CLOSED_0VDC of the signal system SIG.
5. The rail transit platform screen door control system according to claim 2, characterized in that: The integrated monitoring module includes an ISCS integrated monitoring unit, a MODBUS communication unit, a PSA monitoring unit, and relays K22, K23, K24, K25, K26, and K27; The GND of the ISCS integrated monitoring unit is connected to both the 11th pin of relay K24 and the 11th pin of relay K27. The 14th pin of relay K24 is connected to SK3_1 of the logic control unit PEDC, the 12th pin of relay K24 is connected to the 5th pin of the MODBUS communication unit, and the 14th pin of relay K27 is connected to SK3_5 of the main chassis control chip; The B- of the ISCS integrated monitoring unit is connected to the pin 11 of relay K23 and the pin 11 of relay K26. The pin 14 of relay K23 is connected to SK3_3 of the logic control unit PEDC. The pin 12 of relay K23 is connected to the pin 3 of the MODBUS communication unit. The pin 14 of relay K26 is connected to SK3_3 of the main chassis control chip; The A+ of the ISCS integrated monitoring unit is connected to the pin 11 of relay K22 and the pin 11 of relay K25. The pin 14 of relay K22 is connected to SK3_7 of the logic control unit PEDC. The pin 12 of relay K22 is connected to the pin 1 of the MODBUS communication unit. The pin 14 of relay K25 is connected to SK3_2 of the main chassis control chip; The L of the PSA monitoring unit is connected to the L of the fourth input power supply; the N of the PSA monitoring unit is connected to the N of the fourth input power supply; the CH1 of the PSA monitoring unit is connected to SK5 of the main chassis control chip.
6. The rail transit platform screen door control system according to claim 5, characterized in that: SK8_1 of the main chassis control chip is connected to SK4_8 of the logic control unit PEDC; SK8_5 of the main chassis control chip is connected to SK4_3 of the logic control unit PEDC; SK8_4 of the main chassis control chip is connected to SK4_5 of the logic control unit PEDC; SK8_2 of the main chassis control chip is connected to SK4_2 of the logic control unit PEDC; SK8_3 of the main chassis control chip is connected to SK4_7 of the logic control unit PEDC; SK8_8 of the main chassis control chip is connected to SK4_1 of the logic control unit PEDC; SK8_3 of the main chassis control chip is connected to SK4_5 of the logic control unit PEDC; SK8_5 of the main chassis control chip is connected to SK4_4 of the logic control unit PEDC; SK8_2 of the main chassis control chip is connected to SK4_2 of the logic control unit PEDC; SK8_7 of the main chassis control chip is connected to SK4_3 of the logic control unit PEDC.
7. The rail transit platform screen door control system according to claim 4, characterized in that: The main chassis circuit further includes relays K17, K18, K19, K20 and K21; TB1_5 of the integrated backup panel IBP is connected to the pin 11 of relay K17. The pin 12 of relay K17 is connected to both PL3_z4 and PL5_d4 of the main chassis control chip; TB1_4 of the integrated backup panel IBP is connected to the pin 11 of relay K18. The pin 12 of relay K18 is connected to PL5_d6 of the main chassis control chip; TB1_3 of the integrated backup panel IBP is connected to the pin 11 of relay K19. The pin 12 of relay K19 is connected to PL5_d18 of the main chassis control chip; TB1_8 of the integrated backup panel IBP is connected to PL5_z18 of the main chassis control chip; TB1_7 of the integrated backup panel IBP is connected to pin 11 of the relay K20, and pin 12 of the relay K20 is connected to PL5_d8 of the main control box control chip; TB1_9 of the integrated backup panel IBP is connected to pin 11 of the relay K21, and pin 12 of the relay K21 is connected to PL7_d8 of the main control box control chip.
8. The rail transit platform screen door control system according to claim 7, characterized in that: The main control box circuit further includes relays K1, K2, K3, K4, K5, K6, K7, K8, K9, K10, K11 and K16; TB2_6 of the end control panel PSL is connected to both PL3_z12 and PL5_z2 of the main control box control chip; TB2_12 of the end control panel PSL is connected to pin 11 of the relay K4, and pin 12 of the relay K4 is connected to pin 12 of the relay K20; TB2_10 of the end control panel PSL is connected to pin 11 of the relay K5, and pin 12 of the relay K5 is connected to PL7_z4 of the main control box control chip; TB2_9 of the end control panel PSL is connected to pin 11 of the relay K6, and pin 12 of the relay K6 is connected to PL7_b4 of the main control box control chip; TB1_2 of the end control panel PSL is connected to pin 11 of the relay K1, and pin 12 of the relay K1 is connected to PL5_d2 of the main control box control chip; TB2_7 of the end control panel PSL is connected to pin 11 of the relay K9, and pin 12 of the relay K9 is connected to PL7_d4 of the main control box control chip; TB2_8 of the end control panel PSL is connected to pin 11 of the relay K10, and pin 12 of the relay K10 is connected to PL7_z8 of the main control box control chip; TB2_11 of the end control panel PSL is connected to pin 11 of the relay K11, and pin 12 of the relay K11 is connected to PL7_b8 of the main control box control chip; TB2_5 of the end control panel PSL is connected to pin 11 of the relay K16, and pin 12 of the relay K16 is connected to PL5_d10 of the main control box control chip; TB1_1 of the end control panel PSL is connected to pin 11 of the relay K3, and pin 12 of the relay K3 is connected to PL3_z4 of the main control box control chip; TB1_4 of the end control panel PSL is connected to pin 11 of the relay K2, and pin 12 of the relay K2 is connected to PL3_z4 of the main control box control chip; TB1_10 of the end control panel PSL is connected to pin 11 of the relay K7, and pin 12 of the relay K7 is connected to PL5_d12 of the main control box control chip; TB1_11 of the end control panel PSL is connected to pin 11 of the relay K8, and pin 12 of the relay K8 is connected to PL5_d14 of the main control box control chip.
9. The rail transit platform screen door control system according to claim 8, characterized in that: The logic control unit LCU further includes a sub-control box circuit; The sub-control box circuit includes a sub-control box control chip; PL1_z2, PL1_z4, PL1_z22, and PL1_z24 of the secondary chassis control chip are all connected to L1 of the IBP power supply; PL1_z8, PL1_z10, PL1_z28, and PL1_z30 of the secondary chassis control chip are all connected to N1 of the IBP power supply; PL3_d14 of the secondary chassis control chip is connected to PL7_z12 of the secondary chassis control chip; PL3_d18 of the secondary chassis control chip is connected to PL7_b12 of the secondary chassis control chip; PL3_d20 of the secondary chassis control chip is connected to PL7_d12 of the secondary chassis control chip; PL3_d22 of the secondary chassis control chip is connected to PL7_z18 of the secondary chassis control chip; PL4_z12 of the secondary chassis control chip is connected to PL6_d14 of the secondary chassis control chip; PL4_b12 of the secondary chassis control chip is connected to PL6_d18 of the secondary chassis control chip; PL4_d12 of the secondary chassis control chip is connected to PL6_d20 of the secondary chassis control chip; PL4_z18 of the secondary chassis control chip is connected to PL6_d22 of the secondary chassis control chip; PL3_z32 of the secondary chassis control chip is connected to PL3_d14 of the secondary chassis control chip; PL4_z32 of the secondary chassis control chip is connected to PL3_z14 of the secondary chassis control chip; PL4_z26 of the secondary chassis control chip is connected to PL3_z6 of the secondary chassis control chip; PL3_d6 and PL3_d8 of the secondary chassis control chip are both connected to pin 4 of relay K47; PL3_z6 and PL3_z8 of the secondary chassis control chip are both connected to pin 1 of relay K47; PL3_d10 and PL3_d12 of the secondary chassis control chip are both connected to pin 4 of relay K49; PL3_z10 and PL3_z12 of the secondary chassis control chip are both connected to pin 1 of relay K50; PL3_d2 and PL3_d4 of the secondary chassis control chip are both connected to pin 12 of relay K44; PL3_z2 and PL3_z4 of the secondary chassis control chip are both connected to pin 12 of relay K45; PL2_d28 of the secondary chassis control chip is connected to pin 1 of relay K38; PL2_d30 of the secondary chassis control chip is connected to pin 12 of relay K41; PL2_d32 of the secondary chassis control chip is connected to pin 12 of relay K42; PL5_z2 of the secondary chassis control chip is connected to pin 1 of relay K28; PL5_z18 and PL5_z26 of the secondary chassis control chip are both connected to pin 4 of relay K28; PL5_z6 of the secondary chassis control chip is connected to pin 4 of relay K29; PL5_z22 of the secondary chassis control chip is connected to pin 1 of relay K29; PL5_z6 of the secondary chassis control chip is connected to pin 4 of relay K29; PL7_z18 of the secondary chassis control chip is connected to pin 1 of relay K30; PL7_z22 of the secondary chassis control chip is connected to pin 4 of relay K30; PL7_z26 of the secondary chassis control chip is connected to pin 1 of relay K31.
10. The rail transit platform screen door control system according to claim 9, characterized in that: PL6_z2 and PL6_z10 of the secondary chassis control chip are both connected to L1 of the door head enable power supply; PL6_z6 and PL6_z14 of the secondary chassis control chip are both connected to L2 of the door head enable power supply; PL2_z2 of the secondary chassis control chip is connected to TB2_6 of the end control panel PSL; PL2_d2 of the secondary chassis control chip is connected to pin 12 of relay K1; PL2_d4 of the secondary chassis control chip is connected to pin 12 of relay K3; PL2_d6 of the secondary chassis control chip is connected to pin 12 of relay K18; PL2_d8 of the secondary chassis control chip is connected to pin 12 of relay K20; PL2_d10 of the secondary chassis control chip is connected to pin 12 of relay K16; PL2_z12 of the secondary chassis control chip is connected to TB1_8 of the end control panel PSL; PL2_d12 of the secondary chassis control chip is connected to pin 12 of relay K7; PL2_d14 of the secondary chassis control chip is connected to pin 12 of relay K8; PL2_d18 of the secondary chassis control chip is connected to pin 12 of relay K19; PL4_z4 of the secondary chassis control chip is connected to pin 12 of relay K5; PL4_b4 of the secondary chassis control chip is connected to pin 12 of relay K6; PL4_d4 of the secondary chassis control chip is connected to pin 12 of relay K9; PL4_z8 of the secondary chassis control chip is connected to pin 12 of relay K10; PL4_b8 of the secondary chassis control chip is connected to pin 12 of relay K11; PL4_d8 of the secondary chassis control chip is connected to pin 12 of relay K21.