Semiconductor package

Abstract

The utility model provides a semiconductor packaging piece. The semiconductor packaging piece comprises a first semiconductor crystal grain; a first encapsulation surrounding the first semiconductor die in a top view; a bonding layer on the first semiconductor die and the first encapsulation body; a first plurality of dummy pads in the bonding layer; a second semiconductor die bonded to a bonding layer between the first semiconductor die and the second semiconductor die; a first dummy die bonded to the bonding layer, where the first dummy die covers the first plurality of dummy pads, the first dummy die including: a substrate, where a first side of the substrate faces the bonding layer; a first dielectric layer is arranged on the first side of the substrate; and a second dielectric layer, wherein the second dielectric layer is bonded to the bonding layer; and a second encapsulation surrounding the second semiconductor die and the first dummy die in a top view.

Description

Technical Field

[0001] Embodiments of the present utility model relate to semiconductor packages. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the increase in integration density is due to the iterative reduction of the minimum feature size, which allows more components to be integrated into a given area. With the growing demand for shrinking electronic devices, there is a trend towards smaller and more innovative semiconductor die packaging technologies. An example of such a packaging system is the Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and taking up less space on a printed circuit board (PCB). Summary of the Utility Model

[0003] The present application provides a semiconductor package including a first semiconductor die; a first encapsulant surrounding the first semiconductor die in a top view; a bonding layer on the first semiconductor die and the first encapsulant; a first plurality of dummy pads in the bonding layer; a second semiconductor die bonded to the bonding layer, with the bonding layer between the first semiconductor die and the second semiconductor die; a first dummy die bonded to the bonding layer, wherein the first dummy die covers the first plurality of dummy pads, and the first dummy die includes: a substrate, where a first side of the substrate faces the bonding layer; a first dielectric layer on the first side of the substrate; and a second dielectric layer, where the second dielectric layer is bonded to the bonding layer; and a second encapsulant surrounding the second semiconductor die and the first dummy die in a top view. Brief Description of the Drawings

[0004] Reading the following detailed description in conjunction with the accompanying drawings will best understand various aspects of the present disclosure. It should be noted that, according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the sizes of various features can be arbitrarily increased or decreased.

[0005] Figure 1 、 2 、3, 4, 5A, 5B, 5C, 6, 7, 8, 9, 10, and 11 show cross-sectional and top views of intermediate steps in the manufacturing process of a semiconductor package according to some embodiments.

[0006] Figure 12 、 13A 、13B, 13C, 13D, 13E, 14A, 14B, 15A, and 15B show cross-sectional and top views of various semiconductor packages according to some embodiments. Detailed Implementation Manner

[0007] The following disclosure provides numerous different embodiments or examples for implementing different features of the embodiments of the present utility model. Specific examples of components and arrangements are set forth below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming the first feature on or above the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of illustration, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0009] A semiconductor package and a method of forming the same are provided. According to some embodiments, the semiconductor package may include one or more dummy dies bonded to a semiconductor die. The one or more dummy dies may be bonded to the semiconductor die by bonding a first dielectric layer in each dummy die to a second dielectric layer on the semiconductor die. The semiconductor die may include a heat-generating electrical device. Each dummy die may include a material layer that contacts a first dummy pad extending through the first dielectric layer and the first dielectric layer. A second dummy pad may be disposed in the second dielectric layer and in contact with the first dummy pad. The material layer and the first dummy pad in each dummy die and the second dummy pad in the second dielectric layer may transfer heat generated by the electrical device during operation away from the semiconductor package, resulting in higher efficiency and better long-term reliability of the semiconductor package.

[0010] Figures 1 to 11 is a cross-sectional and top view of an intermediate step in the manufacturing process of a semiconductor package including a dummy die having a heat dissipation layer according to some embodiments.

[0011] Reference Figure 1, the bottom semiconductor die 100 is attached to the first carrier 119. The bottom semiconductor die 100 can be a bare semiconductor die (e.g., an unpackaged semiconductor die) formed as part of a larger wafer. For example, the bottom semiconductor die 100 can be a logic die (e.g., an application processor (AP), a central processing unit (CPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a hybrid memory cube (HBC), a static random access memory (SRAM) die, a wide input / output (wide I / O) memory die, a magnetoresistive random access memory (mRAM) die, a resistive random access memory (rRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical systems (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), a biomedical die, or the like. The bottom semiconductor die 100 can be a package including one or more bare semiconductor dies.

[0012] The bottom semiconductor die 100 can be processed according to an applicable manufacturing process to form an integrated circuit in the bottom semiconductor die 100. The bottom semiconductor die 100 can be formed as part of a larger wafer together with other semiconductor dies and then cut out from the wafer. The bottom semiconductor die 100 can include a substrate 102, such as doped or undoped silicon, or the active layer of an insulated-gate semiconductor (SOI) substrate. The substrate 102 can include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multi-layer or gradient substrates, can also be used.

[0013] An electrical device 104 (i.e., an active and / or passive device), such as a transistor, diode, capacitor, resistor, and the like, can be formed in and / or on a substrate 102. The electrical devices 104 can be interconnected by an interconnect structure 106 that includes metallization patterns 108 in one or more dielectric layers 109 on the substrate 102. The interconnect structure 106 is electrically connected to the electrical devices 104 on the substrate 102 to form one or more integrated circuits. The metallization patterns 108 can include a conductive material, such as copper, aluminum, or the like. The one or more dielectric layers 109 can include a low-k dielectric material, such as silicon oxide or the like. A seal ring 107 can be formed in the interconnect structure 106 and can extend through one or more dielectric layers 109 of the interconnect structure 106. In a top-down view, the seal ring 107 can surround the electrical devices 104. In some embodiments, the seal ring 107 is formed of the same material as the metallization patterns 108. The electrical devices 104 may generate relatively high heat during operation, thereby creating thermal hotspots.

[0014] The bottom semiconductor die 100 can further include vias 105 that can be electrically connected to the metallization patterns 108 in the interconnect structure 106. The vias 105 can include a conductive material, such as copper, aluminum, or the like, and can extend from the interconnect structure 106 into the substrate 102. One or more insulating barrier layers (not shown) can be formed around at least a portion of the vias 105 in the substrate 102. In subsequent process steps (e.g., see Figure 2 ), the substrate 102 can be thinned to expose the vias 105. After exposure, the vias 105 can provide an electrical connection from the back side of the substrate 102 to the front side of the substrate 102. In some embodiments, the back side of the substrate 102 can refer to the side of the substrate 102 opposite the electrical devices 104 and the interconnect structure 106, while the front side of the substrate 102 can refer to the side of the substrate 102 on which the electrical devices 104 and the interconnect structure 106 are disposed.

[0015] The bottom semiconductor die 100 can further include one or more passivation layers 110 on the interconnect structure 106 and vias 112 that extend through the one or more passivation layers 110. The vias 112 can be electrically connected to the metallization patterns 108. The one or more passivation layers 110 can include a dielectric material, such as silicon nitride, silicon carbonitride, or the like. The vias 112 can include a conductive material, such as copper, aluminum, or the like. A dielectric layer 114 is disposed on the one or more passivation layers 110, and contact pads 116 are embedded in the dielectric layer 114. The contact pads 116 can be electrically connected to the vias 112. In subsequent process steps, an opening can be formed in the dielectric layer 114 to expose the contact pads 116 (asFigure 8 As shown). After exposure, the contact pad 116 provides an electrical connection to the electrical device 104 and the interconnect structure 106. The dielectric layer 114 may include a dielectric material such as silicon oxide, silicon nitride, or the like. The contact pad 116 may include a conductive material such as copper, aluminum, or the like. A dielectric layer 118 is disposed on the dielectric layer 114. The dielectric layer 118 may include a dielectric material such as silicon oxide, silicon oxynitride, or the like.

[0016] The first carrier 119 may be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The first carrier 119 may be a wafer. Figure 1 Taking one bottom semiconductor die 100 bonded to the first carrier 119 as an example, two or more bottom semiconductor dies 100 may be bonded to the first carrier 119 and processed together in subsequent manufacturing steps until singulated into individual semiconductor packages. A bonding layer 120 may be disposed on the first carrier 119. In some embodiments, the bonding layer 120 includes a first bonding layer 121 on the first carrier 119 and a second bonding layer 123 on the first bonding layer 121. The first bonding layer 121 may include a dielectric material such as silicon oxynitride or the like, and the second bonding layer 123 may include a dielectric material such as silicon oxide or the like.

[0017] The bottom semiconductor die 100 may be attached to the first carrier 119 by bonding the dielectric layer 118 and the bonding layer 120. The bonding process may include pre-bonding and annealing. During pre-bonding, a small pressure may be applied to press the bottom semiconductor die 100 against the bonding layer 120. Pre-bonding may be performed at a low temperature, such as room temperature, and after pre-bonding, the dielectric layer 118 is bonded to the bonding layer 120. Then the bonding strength may be increased in a subsequent annealing step, in which the dielectric layer 118 and the bonding layer 120 are annealed. After annealing, a dielectric-to-dielectric bond, such as a covalent bond, may be formed that bonds the dielectric layer 118 to the bonding layer 120.

[0018] In Figure 2In [the above], a bottom encapsulant 125 is formed on the first carrier 119, and the substrate 102 and the bottom encapsulant 125 are thinned to expose the vias 105. The bottom encapsulant 125 can extend along the sidewalls of the bottom semiconductor die 100 and surround the bottom semiconductor die 100 in a top view. In some embodiments, the bottom encapsulant 125 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, undoped silicate glass (USG), or the like, and can be formed using a suitable deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or the like. In some embodiments, the bottom encapsulant 125 can include a molding compound, an epoxy resin, a resin, or the like, and can be formed by applying compression molding, transfer molding, or the like before curing.

[0019] The substrate 102 is thinned to expose the vias 105. A portion of the bottom encapsulant 125 can also be removed by the thinning process. The thinning process can be a chemical mechanical polishing (CMP) process, a grinding process, a back-etching process, or the like, or a combination thereof. In some embodiments, the substrate 102 is further recessed to expose the sidewalls of the vias 105. The recessing process can be a selective etching process, such as dry etching, wet etching, or a combination thereof. After the recessing process, the vias 105 can protrude from the backside of the substrate 102.

[0020] In Figure 3 [the above], a bonding layer 126 is formed on the substrate 102, the bottom encapsulant 125, and the vias 105, and bonding pads 128 are formed in the bonding layer 126. The bonding layer 126 can be used to bond to another device in a subsequent process, such as bonding to a top semiconductor die 200 as shown in Figure 4 [the figure]. The bonding layer 126 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, USG, or the like, and can be formed using a suitable deposition process (such as CVD, PVD, ALD, or the like).

[0021] Bonding pads 128 are formed in the bonding layer 126 by techniques such as damascene process, dual damascene process, or the like. The bonding pads 128 may be embedded in the bonding layer 126, where the top surface of the bonding pads 128 is exposed, and the sidewalls and bottom surface of the bonding pads 128 are in contact with the bonding layer 126. Some of the bonding pads 128 may be electrically connected to the vias 105 and may be electrically connected to the electrical devices 104 of the bottom semiconductor die 100 through the vias 105. Thus, the bonding pads 128 may provide a path for external devices to the electrical devices 104. Some of the bonding pads 128 may be dummy bonding pads and may be electrically isolated from the circuitry of the bottom semiconductor die 100. As an example of forming the bonding pads 128, openings may be formed in the bonding layer 126 and may expose the underlying vias 105. Forming the openings may include forming a patterned mask, such as a photoresist or one or more dielectric layers over the bonding layer 126, and performing a selective etching process, such as wet or dry etching, to remove the exposed portions of the bonding layer 126 and expose the top surface of the vias 105. The patterned mask may be removed after the etching process. The bonding pads 128 may be formed in the openings. The bonding pads 128 may include a conductive material, such as copper, aluminum, or the like, and are formed by an electro-chemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. A planarization process, such as CMP, may be performed to remove the excess conductive material. Thus, the top surfaces of the bonding layer 126 and the bonding pads 128 may be substantially coplanar or level.

[0022] In Figure 4 FIG., on the bottom semiconductor die 100, the top semiconductor die 200 is bonded to the bonding layer 126 and the bonding pads 128. As an example, Figure 4 FIG. shows one top semiconductor die 200 bonded to the bottom semiconductor die 100. In some embodiments, multiple top semiconductor dies 200 may be bonded to the bottom semiconductor die 100. The top semiconductor die 200 may be a bare semiconductor die (e.g., an unpackaged semiconductor die) that is formed as part of a larger wafer or package that includes one or more bare semiconductor dies, similar to the bottom semiconductor die 100. The top semiconductor die 200 may be processed according to applicable manufacturing processes to form integrated circuits in the top semiconductor die 200. The materials and manufacturing processes of the features in the top semiconductor die 200 may be found by reference to similar features in the bottom semiconductor die 100, where the similar features in the bottom semiconductor die 100 have reference numbers starting with the number "1", corresponding to the features in the top semiconductor die 200 having reference numbers starting with the number "2".

[0023] The top semiconductor die 200 includes a substrate 202 and electrical devices 204 (i.e., active and / or passive devices such as transistors, diodes, capacitors, resistors, and the like) formed in and / or on the substrate 202. An interconnect structure 206 is located on the substrate 202. The interconnect structure 206 may include metallization patterns 208 in one or more dielectric layers 209, and the metallization patterns 208 electrically connect the electrical devices 204 on the substrate 202 to form one or more integrated circuits. A seal ring 207 may extend through one or more dielectric layers 209 of the interconnect structure 206 and surround the electrical devices 204 in a top view. In some embodiments, the back side of the substrate 202 may refer to the side of the substrate 202 opposite to the electrical devices 204 and the interconnect structure 206, and the front side of the substrate 202 may refer to the side of the substrate 202 provided with the electrical devices 204 and the interconnect structure 206.

[0024] The top semiconductor die 200 may further include one or more passivation layers 210 on the interconnect structure 206 and vias 212 extending through the one or more passivation layers 210. The vias 212 may be electrically connected to the metallization pattern 108. A dielectric layer 214 is on the one or more passivation layers 210 and contact pads 216 are embedded in the dielectric layer 214. The contact pads 216 may be electrically connected to the vias 212. A dielectric layer 218 is on the dielectric layer 214, and vias 220 extend through the dielectric layer 218 and into the dielectric layer 214. The vias 212 may be electrically connected to the contact pads 216. The vias 220 may include the same or similar materials as the vias 212. A bonding layer 222 is on the dielectric layer 218 and bonding pads 224 extend through the bonding layer 222. Some of the bonding pads 224 may be electrically connected to the vias 220 and may be electrically connected to the electrical devices 204 of the top semiconductor die 200. Thus, the bonding pads 224 may provide a path for external devices to the electrical devices 204. Some of the bonding pads 224 may be dummy bonding pads and may be electrically isolated from the circuit of the top semiconductor die 200. The bottom surfaces of the bonding layer 222 and the bonding pads 224 may be substantially coplanar or horizontal. The bonding layer 222 may be formed of the same or similar materials as the bonding layer 126 and by the same or similar methods as the bonding layer 126. The bonding pads 224 may be formed of the same or similar materials as the bonding pads 128 and by the same or similar methods as the bonding pads 128. The materials of the bonding layer 126 and the bonding layer 222 may be selected such that a dielectric-to-dielectric bonding may be formed between the bonding layer 126 and the bonding layer 222, and the materials of the bonding pads 128 and the bonding pads 224 may be selected such that a metal-to-metal bonding may be formed between the bonding pads 128 and the bonding pads 224, as described below.

[0025] The top semiconductor die 200 can be bonded to the bonding layer 126 and bonding pads 128 on the bottom semiconductor die 100 using a bonding process, where the bonding layer 222 of the top semiconductor die 200 can be directly bonded to the bonding layer 126 on the bottom semiconductor die 100, and the bonding pads 224 of the top semiconductor die 200 can be directly bonded to the bonding pads 128 on the bottom semiconductor die 100. The top semiconductor die 200 can be disposed face down such that the front side of the substrate 202 faces the back side of the substrate 102, which can be referred to as a front-to-back package configuration. In some embodiments, the bond between the bonding layer 222 and the bonding layer 126 is a dielectric-to-dielectric bond or the like, and the bond between the bonding pads 224 and the bonding pads 128 is a metal-to-metal bond, thereby providing an electrical connection between the bottom semiconductor die 100 and the top semiconductor die 200.

[0026] As an example, the bonding process can start with surface treatment of the bonding layer 126 and the bonding layer 222. The surface treatment can include plasma treatment in a vacuum environment. The surface treatment can also include a cleaning process, such as rinsing with deionized water or the like. Then the bonding process can continue by aligning the bonding pads 224 with the bonding pads 128 such that the bonding pads 224 can overlap the corresponding bonding pads 128. Next, pre-bonding can be performed, during which the top semiconductor die 200 is brought into contact with the bonding layer 126 and the bonding pads 128 at room temperature (e.g., between about 21°C and about 25°C). During pre-bonding, a small pressure can be applied to press the top semiconductor die 200 against the bottom semiconductor die 100. The bonding process can continue with annealing such that the metal in the bonding pads 224 and the metal in the bonding pads 128 diffuse through the interface between the bonding pads 224 and the bonding pads 128 to form a metal-to-metal bond, and the materials of the bonding layer 126 and the bonding layer 222 react to form a dielectric-to-dielectric bond.

[0027] At Figure 5AOne or more dummy dies 300 are bonded to the bonding layer 126. The dummy dies 300 can be a path for transferring heat generated by the electrical device 104 during operation away from the semiconductor package, which can relieve hot spots in the bottom semiconductor die 100, resulting in higher efficiency and better long-term reliability of the semiconductor package. Each dummy die 300 can include a substrate 302, a dielectric layer 304 on the substrate 302, and a material layer 306 on the dielectric layer 304. The dielectric layer 304 can be an adhesive layer that adheres the material layer 306 to the substrate 302. In some embodiments, the dielectric layer 304 is omitted, as described in more detail below. The material layer 306 can have a high thermal conductivity and a high Young's modulus (e.g., high stiffness), both of which result in higher heat transfer efficiency of the dummy die 300, as described in more detail below. Each dummy die 300 can further include a dielectric layer 308 on the material layer 306. The dielectric layer 308 can be a bonding layer that bonds the dummy die 300 to the bonding layer 126. In the bonding process, the dielectric layer 308 of each dummy die 300 can be bonded to the bonding layer 126 by dielectric-to-dielectric bonding, which is similar to Figure 4 the bonding between the bonding layer 222 and the bonding layer 126 described in. After the bonding process, the side of the substrate 302 facing the bonding layer 126 can be referred to as the front side of the substrate 302, and the side of the substrate 302 opposite to the front side of the substrate 302 can be referred to as the back side of the substrate 302.

[0028] The substrate 302 may include the same or similar materials as the substrate 102. The dielectric layer 304 may include silicon oxide, silicon oxynitride, silicon carbonitride, or the like. The dielectric layer 304 may have a first thickness T1 in the range of about 45 nm (nanometers) to about 55 nm, such as about 50 nm. The dielectric layer 304 may have a first thermal conductivity and a first Young's modulus. The material layer 306 may include materials having a high thermal conductivity (e.g., greater than 1.5 W / m·K) and / or a high Young's modulus (e.g., greater than 80 GPa). The high thermal conductivity of the material layer 306 may result in a higher heat transfer efficiency of the dummy die 300. The high Young's modulus of the material layer 306 may result in a reduced thickness of the dielectric layer 304 and the dielectric layer 308 while maintaining a similar level of warp control of the dummy die 300, which may contribute to the effectiveness of the bonding between the dummy die 300 and the bonding layer 126. Reducing the thickness of the dielectric layer 304 and the dielectric layer 308 may also result in a higher heat transfer efficiency of the dummy die 300, as described in more detail below. The material layer 306 may have a second thermal conductivity and a second Young's modulus. The material layer 306 may include amorphous silicon, silicon nitride, silicon carbide, or the like. The material layer 306 may have a second thickness T2 in the range of about 400 nm to about 500 nm, such as about 450 nm. The dielectric layer 308 may include silicon oxide, silicon oxynitride, silicon carbonitride, or the like. The dielectric layer 308 may have a third thickness T3 in the range of about 45 nm to about 55 nm, such as about 50 nm. The dielectric layer 308 may have a third thermal conductivity and a third Young's modulus. The second thickness T2 may be greater than the first thickness T1 and the third thickness T3. The second thermal conductivity may be greater than the first thermal conductivity and the third thermal conductivity. The second Young's modulus may be greater than the first Young's modulus and the third Young's modulus.

[0029] The substrate 302 may have a fourth thermal conductivity greater than the first thermal conductivity of the dielectric layer 304 and the third thermal conductivity of the dielectric layer 308. When the thicknesses of the dielectric layer 304 and the dielectric layer 308 are reduced while the thickness of the dummy die 300 remains unchanged, the thickness of the substrate 302 may be increased. Thus, reducing the thicknesses of the dielectric layer 304 and the dielectric layer 308 may improve the heat transfer efficiency of the dummy die 300.

[0030] Figure 5B and 5C shows a top view of the structure shown in Figure 5A according to some embodiments. Figure 5A The cross-sectional view shown may be obtained from Figure 5B and 5C the reference section A-A' in the top view shown, where the same reference numerals denote the same features. For illustrative purposes, the bottom semiconductor die 100 covered by the bonding layer 126 is shown in dashed lines. Figure 5BAn example of arranging four dummy dies 300 on the bonding layer 126 is shown. Each dummy die 300 has a rectangular shape and extends along one side of the top semiconductor die 200 in a top view. Figure 5C An example of disposing a dummy die 300 having a frame shape on the bonding layer 126 is shown. In a top view, the dummy die 300 can surround the top semiconductor die 200. Other shapes, sizes, numbers, and arrangements of the dummy die 300 can also be contemplated.

[0031] In Figure 6 a top encapsulant 310 is formed on the remaining portion of the bonding layer 126, and a dielectric layer 316 is formed on the top encapsulant 310, the top semiconductor die 200, and the dummy dies 300. The top encapsulant 310 can extend along the sidewalls of the top semiconductor die 200 and the dummy dies 300 and surround the top semiconductor die 200 and the dummy dies 300 in a top view. The top encapsulant 310 can be formed of the same or similar materials as those discussed above with respect to the bottom encapsulant 125 and formed by the same or similar methods. A thinning process can be applied to expose the substrate 202 and the substrate 302. The thinning process can include performing a CMP process, a grinding process, a back-etching process, a combination thereof, or the like. Thus, the back side of the substrate 202, the back side of the substrate 302, and the top surface of the top encapsulant 310 can be substantially coplanar or horizontal. The dielectric layer 316 can be formed of the same or similar materials as those discussed above with respect to the bonding layer 126 and formed by the same or similar methods. The dielectric layer 316 can serve as a bonding layer in subsequent processes.

[0032] In Figure 7 the structure above the first carrier 119 (as Figure 6 shown) is bonded to the second carrier 312, and the first carrier 119 and the bonding layer 120 are removed. The second carrier 312 can be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. The second carrier 312 can be a wafer having the same or similar dimensions as the first carrier 119. One or more bonding layers can be provided on the second carrier 312. In some embodiments, a bonding layer 314 is provided on the second carrier 312. The bonding layer 314 can be formed of the same or similar materials as those discussed above with respect to the bonding layer 126 and formed by the same or similar methods. The dielectric layer 316 and the bonding layer 314 can be bonded by the same or similar processes as those used to bond the bonding layer 126 and the bonding layer 222, thereby bonding the structure above the first carrier 119 to the second carrier 312. The first carrier 119 and the bonding layer 120 can be removed by a thinning process. The thinning process can be a CMP process, a grinding process, a back-etching process, a combination thereof, or the like. After the thinning process, the bottom surface of the dielectric layer 118 and the bottom encapsulant 125 can be substantially coplanar or horizontal.

[0033] In Figure 8 Figure 8 , an opening 317 is formed through the dielectric layer 118 and the dielectric layer 114 to expose the contact pad 116, and a protective layer 318 is formed on the bottom surfaces of the dielectric layer 118 and the bottom encapsulant 125. The opening 317 can be formed by the same or similar method as the opening in which the bonding pad 128 is formed. The opening 317 can expose the contact pad 116 and the sidewalls of the dielectric layer 118 and the dielectric layer 114. The protective layer 318 can be formed of an insulating material such as polyimide or the like and by a coating method such as spin coating or the like. The protective layer 318 can cover the exposed portion of the contact pad 116 and the sidewalls of the dielectric layer 118 and the dielectric layer 114 and the bottom surface of the dielectric layer 118 and the bottom encapsulant 125. Then, a portion of the protective layer 318 covering the exposed portion of the contact pad 116 can be removed to re-expose the contact pad 116.

[0034] In Figure 9 Figure 9 , an under bump metallization (UBM) 320 is formed in the opening 317 (as Figure 8 shown), and an electrical connection member 322 is formed on the UBM 320. The UBM 320 has a bump portion on and extending along the surface of the protective layer 318, and has a via portion extending through the opening 317 to connect to the contact pad 116. Thus, the UBM 320 is electrically connected to the bottom semiconductor die 100. As an example of forming the UBM 320, a seed layer can be formed on the protective layer 318 and the exposed portion of the contact pad 116. The seed layer can be a metal layer, which can be a single layer or a composite layer including multiple sub-layers formed of different materials using a deposition process (such as PVD or the like). Then, a photoresist can be formed on the seed layer and patterned. The pattern of the photoresist can have an opening through the photoresist to expose the seed layer and can correspond to the UBM 320. A conductive material can be formed in the opening of the photoresist and on the exposed portion of the seed layer by plating such as electroless plating, electroplating or the like. The conductive material can include a metal or a metal alloy, such as copper, titanium, tungsten, aluminum or the like or a combination thereof. Then, the photoresist and a portion of the seed layer on which the conductive material is not formed can be removed by an acceptable ashing or stripping process (such as using oxygen plasma or the like). Once the photoresist is removed, the exposed portion of the seed layer can be removed by using an acceptable etching process (such as by wet or dry etching). The remaining portions of the seed layer and the conductive material can be collectively referred to as the UBM 320.

[0035] The electrical connection member 322 is formed on the UBM 320. The UBM 320 and the electrical connection member 322 can be used to provide input / output connections to external electrical components (such as other device dies, redistribution structures, printed circuit boards (PCBs), motherboards, or the like). The electrical connection member 322 can be a ball grid array (BGA) connector, solder ball, metal post, controlled collapse chip connection (C4) bump, micro-bump, electroless nickel palladium immersion gold (ENEPIG) formed bump, or the like. The electrical connection member 322 can include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like or a combination thereof. In some embodiments, the electrical connection member 322 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, or the like and then reflowing the solder layer to shape the material into a desired bump shape. In some embodiments, the electrical connection member 322 includes a metal post (such as a copper post) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. Figure 9 The structure shown can be referred to as the wafer structure 400'.

[0036] In Figure 10 , the wafer structure 400' is singulated into discrete semiconductor packages 400. The wafer structure 400' can be placed on the tape 324 supported by the frame 326. Then, the wafer structure 400' can be cut along the scribe lines 328 such that the wafer structure 400' is separated into discrete semiconductor packages 400. The singulation process can include a sawing process, a laser cutting process, or the like. A cleaning process or a rinsing process can be performed after the singulation process. Then, each semiconductor package 400 can be removed from the tape 324, as Figure 11 shown.

[0037] As an example, the manufacturing process discussed above corresponds to a front-to-back package configuration. In the front-to-back package configuration, the top semiconductor die 200 and the bottom semiconductor die 100 are oriented such that the front side of the substrate 202 of the top semiconductor die 200 faces the back side of the substrate 102 of the bottom semiconductor die 100. Other package configurations can also be envisioned, such as a front-to-front package configuration. In the front-to-front package configuration, the top semiconductor die 200 and the bottom semiconductor die 100 are oriented such that the front side of the substrate 202 of the top semiconductor die 200 faces the front side of the substrate 102 of the bottom semiconductor die 100.

[0038] Figure 12 A cross-sectional view of a semiconductor package 401 having a structure similar to that of the semiconductor package 400 Figure 11 shown is presented, where the same reference numerals denote the same elements. Figure 12An embodiment is shown in which the dielectric layer 304 between the substrate 302 and the material layer 306 in each of one or more dummy dies 300 is omitted. Thus, the material layer 306 is in contact with the substrate 302.

[0039] Figure 13A A cross-sectional view of a semiconductor package 402 having a structure similar to that of the Figure 11 semiconductor package 400 shown is presented, where like reference numerals denote like elements. Figure 13A An embodiment is shown in which a dummy pad is disposed in the bonding layer 126. The dummy pad 127 may have a higher thermal conductivity than the bonding layer 126, thereby improving heat transfer from the electrical device 104 of the bottom semiconductor die 100 to one or more dummy dies 300. The dummy pad 127 may be embedded in the bonding layer 126, where the top surface of the dummy pad 127 may be in contact with the dielectric layer 308, and the sidewalls and bottom surface of the dummy pad 127 may be in contact with the bonding layer 126. The dummy pad 127 may be electrically isolated from the circuitry of the semiconductor package 402. The dummy pad 127 may be a metal pad and may be formed of the same or similar material and by the same or similar method as the bonding pad 128. In some embodiments, the dummy pad 127 and the bonding pad 128 are formed simultaneously. In some embodiments, the dummy pad 127 is formed before or after the bonding pad 128.

[0040] Figure 13B A top view of the semiconductor package 402 according to some embodiments is shown Figure 13A as shown in. Figure 13A The cross-sectional view shown can be obtained from the reference section A-A' in the Figure 13B top view shown, where like reference numerals denote like features. For illustrative purposes, the second carrier 312, the bonding layer 314, and the dielectric layer 316 are omitted, and the dummy pad 127 covered by one or more dummy dies 300 is shown in dashed lines.

[0041] Figure 13C A top view of the semiconductor package 402 according to some embodiments is shown Figure 13BRegion 129 of a top view of the semiconductor package 402 shown. In region 129 which can represent the whole region and the dummy pads 127, the dummy pads 127 can be arranged in an array having various columns and rows. The number of columns and rows shown is for illustrative purposes, and some embodiments can have more or fewer columns and / or rows. The dummy pads 127 can have a circular shape with a diameter D1, where the diameter D1 is in the range of about 1 μm to about 10 μm, such as about 3.5 μm. The distance D2 between two adjacent dummy pads 127 in the same column can be in the range of about 1 μm to about 100 μm, such as about 5.5 μm. The distance D3 between two adjacent dummy pads 127 in the same row can be in the range of about 1 μm to about 100 μm, such as about 5.5 μm. In some embodiments, the distance D2 is the same as the distance D3. In some embodiments, the distance D2 is different from the distance D3. The density of the dummy pads 127 can be greater than about 10%, such as about 11.9%. The density of the dummy pads 127 can be the ratio of the total area of the dummy pads 127 in region 131 to the total area of region 131. Region 131 can be rectangular and can be formed by connecting the center points of two adjacent dummy pads 127 in the first column and two adjacent dummy pads 127 in the second row adjacent to the first row, where the two adjacent dummy pads 127 in the second row are closest to the adjacent dummy pads 127 in the first row.

[0042] Figure 13D Region 129 of a top view of the semiconductor package 402 shown is presented according to some embodiments. Figure 13B In region 129 which can represent the whole region and the dummy pads 127, the dummy pads 127 can be arranged in an array of columns and rows similar to the arrangement described with respect to Figure 13C Region 129 of a top view of the semiconductor package 402 shown. The dummy pads 127 can be selectively formed over hot spots generated under the electrical device 104. Thus, certain regions within the array (such as region 133) may be devoid of dummy pads 127. The dummy pads 127 can have a circular shape with a diameter D4, where the diameter D4 is in the range of about 1 μm to about 10 μm, such as about 3.5 μm. The distance D5 between two adjacent dummy pads 127 in the same column can be in the range of about 1 μm to about 100 μm, such as about 5.5 μm. The distance D6 between two adjacent dummy pads 127 in the same row can be in the range of about 1 μm to about 100 μm, such as about 5.5 μm. In some embodiments, the distance D5 is the same as the distance D6. In some embodiments, the distance D5 is different from the distance D6.

[0043] Figure 13E Region 129 of a top view of the semiconductor package 402 shown is presented according to some embodiments. Figure 13BRegion 129 of the top view of the semiconductor package 402 shown. In region 129 that can represent the entire region and the dummy pad 127, the dummy pad 127 can be arranged in a staggered array with various columns. The dummy pad 127 can have a circular shape with a diameter D7, and the diameter D7 is in the range of about 1 μm to about 10 μm, for example, about 3.5 μm. The distance D8 between two adjacent dummy pads 127 in the first row can be in the range of about 1 μm to about 100 μm, for example, about 5.5 μm. The distance D9 between two adjacent dummy pads 127 in the second row adjacent to the first row can be in the range of about 1 μm to about 100 μm, for example, about 5.5 μm. The distance D10 between two adjacent dummy pads 127 in two adjacent rows along the first direction can be in the range of about 1 μm to about 100 μm, for example, about 5.5 μm. The distance D11 between two adjacent dummy pads 127 in two adjacent rows along the second direction can be in the range of about 1 μm to about 100 μm, for example, about 5.5 μm. In some embodiments, the distance D8 is the same as the distance D9, the distance D10 is the same as the distance D11, and the distance D8 is different from the distance D10. In some embodiments, the distance D8 is the same as the distance D9, the distance D10, and the distance D11. The density of the dummy pad 127 can be greater than about 10%, for example, about 11.9%. The density of the dummy pad 127 can be the ratio of the total area of the dummy pads 127 in region 135 to the total area of region 135. Region 135 can be a parallelogram, which can be formed by connecting the center points of two adjacent dummy pads 127 in the first row and two adjacent dummy pads 127 in the second row, where the two adjacent dummy pads 127 in the second row are closest to the two adjacent dummy pads 127 in the second row.

[0044] Figure 13B , Figure 13C , Figure 13D and Figure 13E The shape, size, quantity, and arrangement of the dummy pad 127 shown are provided as examples. Other shapes, sizes, quantities, and arrangements of the dummy pad 127 can also be envisioned.

[0045] Figure 14A shows a cross-sectional view of a semiconductor package 404 having a structure similar to that of the Figure 11 semiconductor package 400 shown, where the same reference numerals represent the same elements. Figure 14AAn embodiment is shown in which dummy pads 307 are disposed in a dielectric layer 308 of one or more dummy dies 300. The dummy pads 307 may have a higher thermal conductivity than the dielectric layer 308, thereby improving heat transfer from an electrical device 104 of a bottom semiconductor die 100 to the one or more dummy dies 300. The dummy pads 307 may extend through the dielectric layer 308, wherein a top surface of the dummy pads 307 may be in contact with a material layer 306 and a bottom surface of the dummy pads 307 may be in contact with a bonding layer 126. The dummy pads 307 may be electrically isolated from the circuitry of the semiconductor package 404. The dummy pads 307 may be metal pads and may be formed of the same or similar material and by the same or similar method as the bonding pads 224. In some embodiments, the shape, size, number, and arrangement of the dummy pads 307 are substantially the same as the shape, size, number, and arrangement of the dummy pads 127, as described in the top views of Figure 13B , 13C , 13D, and 13E. Other shapes, sizes, numbers, and arrangements of the dummy pads 307 are also contemplated. In some embodiments, the dummy pads 307 are omitted in a portion of the one or more dummy dies 300.

[0046] Figure 14B A cross-sectional view of a semiconductor package 406 is shown having a structure similar to the semiconductor package 402 shown in Figure 13A and the semiconductor package 404 shown in Figure 14A , wherein like reference numerals represent like elements. Figure 14BAn embodiment is shown in which dummy pads 127 are disposed in a bonding layer 126 and dummy pads 307 are disposed in a dielectric layer 308 of one or more dummy dies 300. Each dummy pad 127 may be bonded to a corresponding dummy pad 307. The dummy pads 127 may have a higher thermal conductivity than the bonding layer 126, and the dummy pads 307 may have a higher thermal conductivity than the dielectric layer 308, thereby improving heat transfer from the electrical device 104 of the bottom semiconductor die 100 to the one or more dummy dies 300. The dummy pads 127 may be embedded in the bonding layer 126, wherein the top surface of the dummy pad 127 may contact the dummy pad 307, and the sidewalls and bottom surface of the dummy pad 127 may contact the bonding layer 126. The dummy pads 307 may extend through the dielectric layer 308, wherein the top surface of the dummy pad 307 may contact the material layer 306, and the bottom surface of the dummy pad 307 may contact the dummy pad 127. The dummy pads 127 and the dummy pads 307 may be bonded by a metal-to-metal bond, and the bonding layer 126 and the dielectric layer 308 may be bonded by a dielectric-to-dielectric bond. Each dummy pad 127 and the corresponding dummy pad 307 may be collectively referred to as a dummy feature 309 after bonding. The dummy feature 309 may be electrically isolated from the circuitry of the semiconductor package 406. In some embodiments, the shape, size, number, and arrangement of the dummy feature 309 are substantially the same as the shape, size, number, and arrangement of the dummy pads 127, as described in the top views with respect to Figure 13B , 13C , 13D, and 13E. Other shapes, sizes, numbers, and arrangements of the dummy feature 309 are also contemplated. In some embodiments, the dummy pads 307 are omitted in a portion of the one or more dummy dies 300.

[0047] Figure 15A And Figure 15B Show cross-sectional views and top views of a semiconductor package 408 having a structure similar to the semiconductor package 402 shown in Figure 13A And Figure 13B , respectively, where like reference numerals denote like elements. Figure 15A The cross-sectional view shown can be obtained from the reference section A-A' in the top view shown in Figure 15B , where like reference numerals denote like features. For illustrative purposes, the second carrier 312, the bonding layer 314, and the dielectric layer 316 are omitted, and the dummy pads 127 covered by the one or more dummy dies 300 are shown in dashed lines. Figure 15A And 15BAn embodiment is shown in which a kill zone (KOZ) 137 is disposed in the bonding layer 126 above the seal ring 107 of the bottom semiconductor die 100, where the KOZ 137 may be free of dummy pads 127. A mismatch between the coefficient of thermal expansion (CTE) of the seal ring 107 and the CTE of one or more dielectric layers 109 may cause stress in portions of the bonding layer 126 within the KOZ 137, which may increase the risk of delamination of one or more dummy dies 300 bonded to the bonding layer 126. Omitting the dummy pads 127 in the KOZ 137 may improve the bonding strength between one or more dummy dies 300 and the bonding layer 126, thereby reducing the risk of delamination of one or more dummy dies 300. The width D12 of the KOZ 137 may be in the range of about 10 μm to about 50 μm, such as about 20 μm.

[0048] In some embodiments, the KOZ 137 is applied to a semiconductor package 404, where the KOZ 137 is disposed in the dielectric layer 308 of one or more dummy dies 300 above the seal ring 107, and the KOZ 137 is free of dummy pads 307. In some embodiments, the KOZ 137 is applied to a semiconductor package 406, where the KOZ 137 is disposed in the bonding layer 126 above the dielectric layer 308 of one or more dummy dies 300 and the seal ring 107, and the KOZ 137 is free of dummy features 309.

[0049] Embodiments of the present disclosure have some advantageous features. By utilizing the material layer 306 and dummy pads 307 in one or more dummy dies 300 and the dummy pads 127 in the bonding layer 126 bonded to one or more dummy dies 300, heat generated by the electrical devices 104 in the bottom semiconductor die 100 during operation can be transferred out of the semiconductor packages 400, 401, 402, 404, 406, and 408, which may result in the semiconductor packages 400, 401, 402, 404, 406, and 408 having higher efficiency and better long-term reliability.

[0050] In one embodiment, a semiconductor package includes a first semiconductor die; a first bonding layer on the first semiconductor die; a second semiconductor die bonded to the first bonding layer; and a first dummy die bonded to the first bonding layer, the first dummy die including: a substrate; a material layer on the substrate, wherein the material layer is between the substrate and the first bonding layer, and wherein the material layer includes a first material having a first thermal conductivity and a second bonding layer on the material layer, wherein the second bonding layer is between the material layer and the first bonding layer, and wherein the second bonding layer includes a second material having a second thermal conductivity different from the first thermal conductivity. In one embodiment, the first thermal conductivity is greater than the second thermal conductivity. In one embodiment, the first material has a first Young's modulus and the second material has a second Young's modulus, and wherein the first Young's modulus is greater than the second Young's modulus. In one embodiment, the first dummy die further includes an adhesive layer on the substrate, wherein the adhesive layer is between the substrate and the first bonding layer, and wherein the adhesive layer includes a third material different from the first material. In one embodiment, the first bonding layer is bonded to the second bonding layer by dielectric-to-dielectric bonding. In one embodiment, the semiconductor package further includes a dummy pad in the first bonding layer, wherein the dummy pad includes metal, and wherein the dummy pad is in contact with the second bonding layer. In one embodiment, the semiconductor package further includes a dummy pad in the second bonding layer, wherein the dummy pad includes metal, and wherein the dummy pad is in contact with the first bonding layer. In one embodiment, the semiconductor package further includes a first dummy pad in the first bonding layer; and a second dummy pad in the second bonding layer, and wherein each first dummy pad is bonded to one of the corresponding second dummy pads by metal-to-metal bonding.

[0051] In one embodiment, a semiconductor package includes a first semiconductor die; a first encapsulant surrounding the first semiconductor die in a top view; a bonding layer on the first semiconductor die and the first encapsulant; a first plurality of dummy pads in the bonding layer; a second semiconductor die bonded to the bonding layer, with the bonding layer between the first semiconductor die and the second semiconductor die; a first dummy die bonded to the bonding layer, wherein the first dummy die covers the first plurality of dummy pads, and the first dummy die includes: a substrate, where a first side of the substrate faces the bonding layer; a first dielectric layer on the first side of the substrate; and a second dielectric layer, where the second dielectric layer is bonded to the bonding layer; and in a top view, a second encapsulant surrounding the second semiconductor die and the first dummy die. In one embodiment, the second semiconductor die is electrically coupled to the first semiconductor die, and the first dummy die is electrically isolated from the first semiconductor die. In one embodiment, the first dummy die further includes a material layer located between the first dielectric layer and the second dielectric layer, and the material layer has better thermal conductivity than the first dielectric layer and the second dielectric layer. In one embodiment, the first plurality of dummy pads form an array pattern in a top view. In one embodiment, the first plurality of dummy pads form a staggered array pattern in a top view. In one embodiment, the first dummy die further includes a second plurality of dummy pads extending through the second dielectric layer, where the second plurality of dummy pads are in contact with one of the corresponding first plurality of dummy pads, and the first dummy die is bonded to the bonding layer and the first plurality of dummy pads through dielectric-to-dielectric bonding and metal-to-metal bonding respectively.

[0052] In one embodiment, a method of fabricating a semiconductor package includes forming a first dielectric layer on a first semiconductor die, wherein the first dielectric layer includes a first material; forming a first metal pad in the first dielectric layer; bonding a second semiconductor die to the first dielectric layer and the first metal pad using dielectric-to-dielectric and metal-to-metal bonding; and bonding one or more dummy dies to the first dielectric layer, and wherein each of the one or more dummy dies includes: a substrate; a second dielectric layer bonded to the first dielectric layer, wherein the second dielectric layer includes a second material; and a material layer between the substrate and the second dielectric layer, wherein the material layer includes a third material different from the second material, and wherein the third material has a higher thermal conductivity than the second material. In one embodiment, the method further includes forming a second metal pad in the first dielectric layer; and contacting the second dielectric layer of each of the one or more dummy dies with the first dielectric layer and the second metal pad, wherein the one or more dummy dies are bonded to the first dielectric layer using dielectric-to-dielectric bonding. In one embodiment, in a top view, the first semiconductor die includes one or more electrical devices and a sealing ring surrounding the one or more electrical devices, wherein a prohibited area in the first dielectric layer is directly disposed above the sealing ring, and wherein the prohibited area does not contain the second metal pad. In one embodiment, the method further includes forming a second metal pad in the first dielectric layer; contacting the second dielectric layer of each of the one or more dummy dies with the first dielectric layer; and contacting a third metal pad of each of the one or more dummy dies with a corresponding second metal pad in the second metal pad, wherein the third metal pad extends through the second dielectric layer of each of the one or more dummy dies, and wherein the one or more dummy dies are bonded to the first dielectric layer and the second metal pad using dielectric-to-dielectric and metal-to-metal bonding. In one embodiment, the first semiconductor die includes one or more electrical devices and a sealing ring surrounding the one or more electrical devices in a top view, wherein a first prohibited area in the first dielectric layer is directly disposed above the sealing ring, wherein the first prohibited area does not contain the second metal pad, wherein a second prohibited area in each of the one or more dummy dies is directly disposed above the sealing ring, and wherein the second prohibited area does not contain the third metal pad. In one embodiment, the method further includes forming a first encapsulant surrounding the first semiconductor die in a top view; and forming a second encapsulant surrounding the second semiconductor die and the one or more dummy dies in a top view, wherein the first dielectric layer is located between the first encapsulant and the second encapsulant. In one embodiment, the first dielectric layer has a first thickness, the material layer has a second thickness, the second dielectric layer has a third thickness, and the second thickness is greater than the first thickness and the third thickness. In one embodiment, the first thickness ranges from 45 nanometers to 55 nanometers, and the third thickness ranges from 45 nanometers to 55 nanometers.

[0053] The foregoing has outlined features of several embodiments in order that the skilled person in the art may better understand the various aspects of the present disclosure. The skilled person in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. The skilled person in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor package, characterized in that, Comprising: A first semiconductor die; A first encapsulant surrounding the first semiconductor die; A bonding layer on the first semiconductor die and the first encapsulant; A first plurality of dummy pads in the bonding layer; A second semiconductor die bonded to the bonding layer, the bonding layer being between the first semiconductor die and the second semiconductor die; A first dummy die bonded to the bonding layer, wherein the first dummy die covers the first plurality of dummy pads, and the first dummy die comprises: A substrate, wherein a first side of the substrate faces the bonding layer; A first dielectric layer on the first side of the substrate; and A second dielectric layer, wherein the second dielectric layer is bonded to the bonding layer; and A second encapsulant surrounding the second semiconductor die and the first dummy die.

2. The semiconductor package according to claim 1, wherein The second semiconductor die is electrically coupled to the first semiconductor die, and wherein the first dummy die is electrically isolated from the first semiconductor die.

3. The semiconductor package according to claim 1, wherein The first dummy die further comprises a material layer between the first dielectric layer and the second dielectric layer, and wherein the material layer has better thermal conductivity than the first dielectric layer and the second dielectric layer.

4. The semiconductor package according to claim 3, wherein The first dielectric layer has a first thickness, the material layer has a second thickness, the second dielectric layer has a third thickness, and the second thickness is greater than the first thickness and the third thickness.

5. The semiconductor package according to claim 4, characterized in that, The first thickness is in the range of 45 nanometers to 55 nanometers, and the third thickness is in the range of 45 nanometers to 55 nanometers.

6. The semiconductor package according to claim 1, wherein The first plurality of dummy pads form an array pattern.

7. The semiconductor package according to claim 1, wherein The first plurality of dummy pads form a staggered array pattern.

8. The semiconductor package according to claim 1, wherein, The first dummy die further comprises a second plurality of dummy pads extending through the second dielectric layer, wherein the second plurality of dummy pads are in contact with one of the corresponding first plurality of dummy pads, and wherein the first dummy die is bonded to the bonding layer and the first plurality of dummy pads by dielectric-to-dielectric bonding and metal-to-metal bonding, respectively.

9. The semiconductor package according to claim 1, wherein The first semiconductor die includes one or more electrical devices and a sealing ring surrounding the one or more electrical devices, wherein a prohibited region in the first dielectric layer is directly disposed above the sealing ring.

10. The semiconductor package according to claim 9, wherein, A prohibited region in the first dummy die is directly disposed above the sealing ring.

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