Semiconductor device

Abstract

The embodiment of the utility model provides a semiconductor device comprising a first semiconductor package which comprises a first semiconductor tube core packaged in an insulating material; a first thermal expansion resistant layer over the first semiconductor die; a bonding layer over the first heat-resistant expansion layer and the insulating material; and a second semiconductor die directly bonded to the bonding layer.

Description

Technical Field

[0001] Embodiments of the present utility model relate to a semiconductor device. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, the increase in integration density is due to the iterative reduction of the minimum feature size, which enables more components to be integrated into a given area. With the growing demand for shrinking electronic devices, there has also emerged a need for packaging technologies for smaller and more innovative semiconductor dies. An example of such a packaging system is the Package-on-Package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration density and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the Utility Model

[0003] Embodiments of the present utility model provide a semiconductor device, including: a first semiconductor package including a first semiconductor die encapsulated in an insulating material; a first thermal expansion layer located above the first semiconductor die; a bonding layer located above the first thermal expansion layer and the insulating material; and a second semiconductor die directly bonded to the bonding layer.

[0004] Embodiments of the present utility model provide a semiconductor device, including: a first semiconductor die embedded in a first insulating layer; a second semiconductor die adjacent to the first semiconductor die embedded in the first insulating layer; a first nitride layer located above the first semiconductor die; a bonding layer located above the first nitride layer opposite to the first semiconductor die; and a third semiconductor die bonded to the bonding layer opposite to the first semiconductor die.

[0005] To make the above features and advantages of the embodiments of the present utility model more obvious and understandable, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0006] As will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figures 1-10Shows various views of steps for forming a first PoP device according to some embodiments, the first PoP device having an oxide liner surrounding a thermal expansion layer over a top surface of a bottom semiconductor die.

[0008] Figure 11 Shows a view of a first PoP device having a local interconnect bridge connecting multiple bottom semiconductor dies according to some embodiments.

[0009] Figure 12 Shows a view of a first PoP device having a thermal expansion layer directly over a top surface of a bottom semiconductor die according to some embodiments.

[0010] Figures 13-16 Shows various views of steps for forming a second PoP device according to some embodiments, the second PoP device having a thermal expansion layer over a top surface of a bottom device package.

[0011] Figure 17 Shows a view of a second PoP device having a local interconnect bridge connecting multiple bottom semiconductor dies according to some embodiments.

[0012] Figures 18-20 Shows various views of steps for forming a third PoP device according to some embodiments, the third PoP device having a thermal expansion layer between a top device package and a carrier substrate.

[0013] Description of reference numerals:

[0014] 100: First carrier substrate

[0015] 101: First bonding layer

[0016] 103: Second bonding layer

[0017] 1000: First PoP device

[0018] 1001: First die connector

[0019] 1003: Conductive connector

[0020] 1100: Local interconnect

[0021] 1101: Interconnect substrate

[0022] 1103: Second interconnect structure

[0023] 1105: Second metallization pattern

[0024] 1107: Second interconnect dielectric layer

[0025] 1301: Oxide layer

[0026] 1401: Second thermal expansion layer

[0027] 1500: Third packaging device

[0028] 1501: Seventh bonding layer

[0029] 1600: Second PoP device

[0030] 1800: Fourth packaging device

[0031] 1900: Fifth packaging device

[0032] 1901: Third thermal expansion layer

[0033] 201: Encapsulation body

[0034] 203: First planarization process

[0035] 2000: Third PoP device

[0036] 301: Etching process

[0037] 303: Groove

[0038] 401: Oxide material

[0039] 403: Thermal expansion material

[0040] 50: First integrated circuit die

[0041] 50A: First semiconductor die

[0042] 50B: Second semiconductor die

[0043] 51: First semiconductor substrate

[0044] 53: First interconnect structure

[0045] 55: First metallization pattern

[0046] 57: First interconnect dielectric layer

[0047] 59: Through-silicon via

[0048] 500: First packaging device

[0049] 501: Oxide liner

[0050] 503: Thermal expansion layer

[0051] 505: Planarization process

[0052] 61: Guard ring structure

[0053] 601: Third bonding layer

[0054] 603: First dielectric layer

[0055] 605: First bonding pad

[0056] 607: First alignment structure

[0057] 701: Second integrated circuit die

[0058] 701A: Third semiconductor die

[0059] 701B: Fourth semiconductor die

[0060] 703:Dummy die

[0061] 703A: Dummy die substrate

[0062] 703B: Dummy die bonding layer

[0063] 709: Fourth bonding layer

[0064] 711: Second dielectric layer

[0065] 713: Second contact pad

[0066] 715: Second interconnect structure

[0067] 717: Second interconnect dielectric layer

[0068] 719: Second metallization pattern

[0069] 721: Second semiconductor substrate

[0070] 800: Second packaging device

[0071] 801: Second insulating material

[0072] 900: Second carrier substrate

[0073] 901: Fifth bonding layer

[0074] 903: Sixth bonding layer

[0075] 905: Second alignment structure

[0076] 950: Second planarization process

[0077] 951: Third dielectric layer

[0078] 953: First passivation film

[0079] TH1: First thickness Detailed implementation manners

[0080] The following disclosure provides many different embodiments or examples for implementing different features of the utility model. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for simplicity and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0081] Furthermore, as shown in the figures, spatial relative terms, such as "beneath", "below", "lower", "over", "upper", etc., may be used herein to facilitate describing the relationship of one element or feature to another element or feature. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0082] According to some embodiments, a thermally expandable material layer is deposited at the bonding boundary points within a semiconductor packaging device. The thermally expandable material layer helps to mitigate the strain caused by the thermal mismatch between materials within the semiconductor packaging device (e.g., the thermal expansion between a gap-fill oxide having a coefficient of thermal expansion (CTE) of 0.6 and a silicon bottom die having a CTE of 2.8). The CTE difference between these materials may cause punchup of the material with the higher CTE (e.g., silicon punchup), which may lead to delamination at the boundary layer. The addition of a thermally expandable material having sufficient hardness helps to inhibit such punchup and reduce the risk of delamination.

[0083] Figure 1A cross-sectional view of one or more first integrated circuit dies 50 bonded to a first bonding layer 101 of a first carrier substrate 100 is shown in accordance with some embodiments. In accordance with some embodiments, the first carrier substrate 100 includes silicon or the like. The first bonding layer 101 may include an oxide, such as silicon oxide, silicon oxynitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., chemical vapor deposition-based material deposition and post-curing in a remote plasma system to convert the material into an oxide), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like, or a combination thereof. Other oxide materials formed by any acceptable process may be used to form the first bonding layer 101 over the first carrier substrate 100.

[0084] In accordance with some embodiments, the first integrated circuit die 50 may be a bare die semiconductor die (e.g., an unpackaged semiconductor die). For example, the first integrated circuit die 50 may be a logic die (e.g., an AP, a central processing unit, a microcontroller, etc.), a memory die (e.g., a DRAM die, an HBC, an SRAM die, a wideIO memory die, an mRAM die, an rRAM die, etc.), a power management die (e.g., a PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., a DSP die), a front-end die (e.g., an AFE die), a biomedical die, etc.

[0085] The first integrated circuit die 50 may be processed in accordance with an applicable manufacturing process to form an integrated circuit therein. For example, each of the first integrated circuit dies 50 may include a first semiconductor substrate 51, such as an active layer of a doped or undoped silicon or semiconductor-on-insulator (SOI) substrate. The first semiconductor substrate 51 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or a combination thereof. Other substrates, such as multi-layer or gradient substrates, may also be used.

[0086] For example, devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on the first semiconductor substrate 51 and may be interconnected by a first interconnect structure 53 that includes a first metallization pattern 55 (e.g., conductive lines, vias, and conductive pads) in one or more first interconnect dielectric layers 57 to form one or more integrated circuits. The first interconnect dielectric layers 57 may include silicon oxide, silicon nitride, silicon oxynitride, polymers, etc., and are deposited by PVD, CVD, ALD, etc. The first metallization pattern 55 may be, for example, conductive features formed in the first interconnect dielectric layers 57 by a damascene process.

[0087] In addition, the first integrated circuit die 50 may include one or more through silicon vias (TSVs) 59 extending into the first semiconductor substrate 51 of the first integrated circuit die 50 to provide a fast path for data signals. In an embodiment, the TSVs 59 may be formed by initially forming TSV openings (e.g., before the formation of active devices) in the first semiconductor substrate 51. The TSV openings may be formed by applying and developing a suitable photoresist (not shown) and removing portions of the first semiconductor substrate 51 exposed to a desired depth. The TSV openings may be formed to extend into the first semiconductor substrate 51 at least further than the active devices formed in and / or on the first semiconductor substrate 51 and may extend to a greater depth than the final desired height of the first semiconductor substrate 51. Once the TSV openings are formed in the first semiconductor substrate 51, the TSV openings are lined with a liner. The liner may be, for example, an oxide formed from tetraethylorthosilicate (TEOS) or silicon nitride, but any suitable dielectric material may alternatively be used. A plasma enhanced chemical vapor deposition (PECVD) process may be used to form the liner, but other suitable processes, such as physical vapor deposition or thermal processes, may alternatively be used.

[0088] Once the liner is formed along the sidewalls and bottom of the TSV opening, a barrier layer (not shown separately) can be formed and the remaining portion of the TSV opening can be filled with a first conductive material. The first conductive material can include copper, but other suitable materials can alternatively be used, such as aluminum, alloys, doped polysilicon, combinations thereof, etc. The first conductive material can be formed by electroplating copper onto a seed layer (not shown), filling, and overfilling the TSV opening. Once the TSV opening is filled, the excess liner, barrier layer, seed layer, and first conductive material outside the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process can be used. Additionally, in embodiments, a guard ring structure 61 can be formed in one or more of the first interconnect dielectric layers 57, and the guard ring structure 61 surrounds each of one or more TSVs 59. The guard ring structure 61 can have multiple functions, such as isolation, stress relief, current leakage prevention, electrostatic discharge (ESD) protection, etc. or combinations thereof. For example, to help prevent current leakage protection, the guard ring structure 61 can be grounded to help prevent or reduce electrical interference caused by current flowing through one or more TSVs 59.

[0089] According to some embodiments, a second bonding layer 103 can be deposited over what can be referred to as the active side or front side of a first integrated circuit die 50. The active side / front side of the first integrated circuit die 50 can be referred to as the side of the first semiconductor substrate 51 on which active devices are formed. The back side of the first integrated circuit die 50 can be referred to as the side of the first semiconductor substrate 51 opposite the active side / front side. In some embodiments, the second bonding layer 103 can be an oxide, such as silicon oxide, silicon oxynitride, etc. or combinations thereof, and can be formed by HDP-CVD, FCVD, CVD, ALD, PVD, etc. or combinations thereof. Other oxide materials formed by any acceptable process can be used to form the second bonding layer 103 over the first integrated circuit die 50.

[0090] In an embodiment, one or more first integrated circuit dies 50 may be bonded to a first carrier substrate 100 by a first dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) that forms a first dielectric-to-dielectric bond (e.g., oxide-to-oxide bond). The first dielectric-to-dielectric bond may be initiated by activating the first bonding layer 101 and / or the second bonding layer 103 and then applying pressure, heat, and / or other bonding process steps to join the first bonding layer 101 to the surface of the second bonding layer 103. Activation of the first bonding layer 101 and the second bonding layer 103 may be performed using, for example, dry processing, wet processing, plasma processing, exposure to H2, exposure to N2, exposure to O2, combinations thereof, etc. In an embodiment using wet processing, for example, an RCA cleaning process may be used. This activation promotes the first dielectric-to-dielectric bonding of the first bonding layer 101 and the second bonding layer 103, for example, by allowing the use of lower pressure and temperature in a subsequent first dielectric-to-dielectric bonding process. By this treatment, the number of OH groups at the surface of the first bonding layer 101 and / or the second bonding layer 103 is increased. After the surface of the first bonding layer 101 and / or the second bonding layer 103 is activated, the first bonding layer 101 and the second bonding layer 103 may be brought into contact with each other at a relatively low temperature (e.g., room temperature) to form a weak bond. Subsequently, annealing is performed to strengthen the weak bond and form the first dielectric-to-dielectric bond. During annealing, the H of the OH bond is exhausted, thereby forming an Si-O-Si bond between the first bonding layer 101 and the second bonding layer 103, thus strengthening the bond.

[0091] Figure 2 A cross-sectional view showing a first insulating material 201 (also referred to as a gap-filling material or an encapsulant) encapsulating the first integrated circuit die 50 is shown. According to some embodiments, the first insulating material 201 may be an oxide, such as silicon oxide (e.g., silicon dioxide), etc. The first insulating material 201 may be formed by spin coating, HDPCVD, etc. In some embodiments, the first insulating material 201 is formed to overfill one or more first integrated circuits 50 and fill any gaps between one or more first integrated circuits 50. In an embodiment, a first planarization process 203 may be performed to remove excess material of the first insulating material 201 above the first integrated circuit die 50. Additionally, in an embodiment, the first planarization process 203 may remove a portion of the first semiconductor substrate 51 exposing the TSV 59 and may form a flat top surface (within process variations) shared between the first insulating material 201 and the first integrated circuit die 50. The first planarization process 203 may be a grinding process, a chemical mechanical polishing (CMP) process, etc. However, any suitable planarization process may be used.

[0092] Figure 3A cross-sectional view of an etching process 301 performed on a first semiconductor substrate 51 is shown to form a groove 303 in the first semiconductor substrate 51 between the TSVs 59. In an embodiment, the etching process 301 can be any acceptable etching process, for example, reactive ion etch (RIE), neutral beam etch (NBE), etc. or a combination thereof. The etching can be anisotropic. In an embodiment, the etching process 301 is a time-controlled anisotropic plasma etching process that produces the groove 303. In an embodiment, the groove can be formed to a sufficient depth to facilitate the thickness of a thermal expansion resistant layer subsequently formed in the groove 303.

[0093] Figure 4 A cross-sectional view of an oxide material 401 above the top surface of the first insulating layer 201, in the groove 303, and above the exposed portions of the TSVs 59 and a thermal expansion resistant material 403 above the oxide material is shown. In an embodiment, the oxide material 401 can be deposited by a conformal deposition process, for example, by atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. In an embodiment, the oxide material 401 can be silicon oxide, etc. In an embodiment, the thermal expansion resistant material 403 can be deposited by a conformal deposition process, for example, by ALD, HDPCVD, CVD, etc. In an embodiment, the thermal expansion resistant material 403 can be silicon nitride, for example, SiN, SiCN, SiON, etc. The thermal expansion resistant material 403 can have a first hardness in the range of 10 GPa to 30 GPa. The hardness of the thermal expansion resistant material 403 helps to suppress the thermal expansion mismatch below the thermal expansion resistant material 403, thereby reducing the risk of delamination between the first integrated circuit die 50 and the subsequently bonded structure. If the hardness of the thermal expansion resistant material 403 is less than the first hardness, the thermal expansion resistant material 403 may not sufficiently suppress the thermal mismatch between the bonding layers. If the hardness of the thermal expansion resistant material 403 is greater than the first hardness, the thermal expansion resistant material 403 may be too hard for subsequent processes.

[0094] Figure 5A cross-sectional view of the oxide liner 501 around the thermal expansion layer 503 after the planarization process 505 is shown. In an embodiment, after the deposition of the oxide material 401 and the deposition of the thermal expansion material 403, a planarization process 505 is performed to remove the excess materials of the oxide material 401 and the thermal expansion material 403 from above the first insulating material 201 and from above the TSV 59 exposing the TSV 59. In an embodiment, after the planarization process 505, the thermal expansion layer 503 isolates the first semiconductor substrate 51 of the first integrated circuit die 50 from the structure subsequently formed above the first integrated circuit die 50, and the first integrated circuit die 50 is encapsulated by the first insulating material 201. In this embodiment, the first insulating material 201, the oxide liner 501 (if present), the thermal expansion layer 503, and the TSV 59 of the first integrated circuit die 50 share a planar top surface (within process variations). The first insulating material 201, the thermal expansion layer 503, and the first integrated circuit die 50 after the planarization process 505 may be referred to as the first packaging device 500, and the first packaging device 500 has a planar top surface.

[0095] After the planarization process 505, the thermal expansion layer 503 may have a first thickness TH1, and the first thickness is in to range. If the thickness of the thermal expansion layer 503 is less than the first thickness TH1, the thermal expansion layer 503 may provide sufficient rigidity to suppress the thermal expansion mismatch from below the thermal expansion layer 503, thereby increasing the risk of delamination. If the thickness of the thermal expansion layer 503 is greater than the first thickness THl, the overall resulting structure may be too rigid and increase the risk of corner cracking at the interface of the thermal expansion layer 503.

[0096] Figure 6 A cross-sectional view of the third bonding layer 601 formed on the planar top surface of the first packaging device 500 is shown. In an embodiment, the third bonding layer 601 may include a first dielectric layer 603 and a first bonding pad 605 embedded in the first dielectric layer 603. The first dielectric layer 603. In some embodiments, the first bonding pad 605 may include a conductive material, such as copper, etc. Some of the first bonding pads 605 may be physically and electrically coupled to the TSV 59. In an embodiment, the first dielectric layer 603 may include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the first dielectric layer 603 may be deposited using a suitable deposition process, such as CVD, PVD, ALD, HDPCVD, combinations of these, etc. The first bonding pad 605 may be formed within the first dielectric layer 603 or before the first dielectric layer 603, using any suitable process, such as damascene process, electroplating, etc.

[0097] For example, in an embodiment where the first dielectric layer 603 is formed before the first bonding pad 605 is formed, an opening corresponding to the position of the first bonding pad 605 can be formed in the first dielectric layer 603 using a combination of photolithography and etching processes. Once the opening is formed in the first dielectric layer 603, the opening can be filled with a seed layer (not shown separately) and a plate metal to form the first bonding pad 605 within the first dielectric layer 603. The seed layer can be a blanket deposited over the top surface of the first dielectric layer 603 and the exposed conductive portions of the bottom and sidewalls of the opening. The seed layer can include a copper layer. Depending on the desired material, the seed layer can be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), etc. The plate metal can be deposited over the seed layer through an electroplating process such as electroplating or electroless plating. The plate metal can include copper, copper alloy, etc.

[0098] As another example, in an embodiment where the first dielectric layer 603 is formed after the first bonding pad 605 is formed, the seed layer can be a blanket deposited over the flat surface of the first packaging device 500. A photoresist (not shown separately) can be formed and patterned to define the layout of the first bonding pad 605, and an electroplating process can be applied to form the plate metal in the opening of the photoresist. Subsequently, the portions of the photoresist and the seed layer not covered by the plate metal can be removed, and the remaining portions of the seed layer and the plate metal form the first bonding pad 605. Then, the first dielectric layer 603 is deposited around the first bonding pad 605.

[0099] Optionally, a planarization step can then be performed to make the top surfaces of the third bonding layer 601 and the first bonding pad 605 flush, such that the third bonding layer 601 and the first bonding pad 605 have a high degree of flatness (within process variations). Other materials and forming methods are also possible.

[0100] In addition, in some embodiments, a first alignment structure 607 (also referred to as an alignment mark) can be formed in the first dielectric layer 603. In an embodiment, the first alignment structure 607 can be formed in a similar manner and from similar materials as the first bonding pad 605. However, any suitable material or method can be utilized to form the first alignment structure 607. The first alignment structure 607 can be used for subsequent alignment of the bonding structure over the first packaging device 500.

[0101] Figure 7 A cross-sectional view showing one or more second integrated circuit dies 701 and one or more dummy dies 703 attached to the first packaging device 500 through the third bonding layer 601 is shown. According to some embodiments, the dummy dies 703 can be placed to subsequent formation of the second packaging device 800 (see Figure 8) Provide structural support and reduce warping or cracking, especially when multiple integrated circuit dies are attached to the third bonding layer 601. The dummy die 703 can be formed of a material having suitable mechanical stiffness or rigidity. In some embodiments, the dummy die 703 can be formed of a semiconductor material, such as, silicon, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, etc. or a combination thereof. In some embodiments, the dummy die 703 can be formed of a dielectric material, such as, a ceramic material, quartz, another electrically inert material, etc. or a combination thereof. In some embodiments, the dummy die 703 can be a metal or a metal alloy, such as, a tin-nickel alloy (e.g., "Alloy 42"), etc. In some embodiments, the dummy die 703 is formed of two or more different materials, such as, multiple layers of different materials. In some embodiments, the material of the dummy die 703 is selected based on the mechanical stiffness or rigidity of the material.

[0102] In some embodiments, including the dummy die 703 is to improve the uniformity in the second packaging device 800, which can result in improved planarization. The dummy die 703 can also be included to reduce the CTE mismatch between various components in the second packaging device 800. The dummy die 703 can also serve as a heat dissipation feature. In this embodiment, the material of the dummy die 703 can be selected to have a relatively high thermal conductivity (e.g., higher than the thermal conductivity of the subsequently deposited second insulating material 801, see Figure 8 ). According to some embodiments, the dummy die 703 can substantially have no active devices, functional circuits, etc. For example, the dummy die 703 can include a dummy die substrate 703A (e.g., a bulk silicon substrate) and a dummy die bonding layer 703B. The dummy die bonding layer 703B can be used to bond the dummy die 703 to the third bonding layer 601 using, for example, a fusion bonding process.

[0103] The second integrated circuit die 701 can be a bare die semiconductor die (e.g., an unpackaged semiconductor die). For example, the second integrated circuit die 701 can be a logic die (e.g., an AP, a central processing unit, a microcontroller, etc.), a memory die (e.g., a DRAM die, an HBC, an SRAM die, a wideIO memory die, an mRAM die, an rRAM die, etc.), a power management die (e.g., a PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., a DSP die), a front-end die (e.g., an AFE die), a biomedical die, etc.

[0104] The second integrated circuit die 701 can be processed according to an applicable manufacturing process to form an integrated circuit in the second integrated circuit die 701. For example, the second integrated circuit die 701 can include a second semiconductor substrate 721, e.g., an active layer of doped or undoped silicon or an SOI substrate. The second semiconductor substrate 721 can include other semiconductor materials, e.g., germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates can also be used, e.g., multi-layer or gradient substrates.

[0105] For example, devices such as transistors, diodes, capacitors, resistors, etc. can be formed in and / or on the second semiconductor substrate 721 and can be interconnected by a second interconnect structure 715 that includes a second metallization pattern 719 (e.g., conductive lines and vias) in one or more second interconnect dielectric layers 717 to form one or more integrated circuits. The second interconnect dielectric layers 717 can include silicon oxide, silicon nitride, silicon oxynitride, polymers, etc. and are deposited by PVD, CVD, ALD, etc. The second metallization pattern 719 can be, for example, a conductive feature formed in the second interconnect dielectric layer 717 by a damascene process.

[0106] The second integrated circuit die 701 also includes second contact pads 713 that allow for external connection to the second interconnect structure 715 and the devices on the second semiconductor substrate 721. The second contact pads 713 can include copper, aluminum (e.g., 28K aluminum), or another conductive material that is electrically connected to the second metallization pattern 719 of the second interconnect structure 715. The second contact pads 713 are disposed on what can be referred to as the active side or front side of the second integrated circuit die 701. The active side / front side of the second integrated circuit die 701 can be referred to as the side of the second semiconductor substrate 721 on which active devices are formed. The back side of the second integrated circuit die 701 can be referred to as the side of the second semiconductor substrate 721 opposite the active side / front side.

[0107] The second integrated circuit die 701 can be formed as part of a larger wafer (e.g., connected to other second integrated circuit dies 701). In some embodiments, the second integrated circuit dies 701 can be singulated from each other prior to packaging. The singulation process can include mechanical sawing, laser cutting, plasma cutting, combinations thereof, etc. In other embodiments, the second integrated circuit dies 701 are singulated after they are integrated into a semiconductor package. For example, the second integrated circuit dies 701 can be packaged while still connected as part of a wafer.

[0108] According to some embodiments, the second integrated circuit die 701 is attached to the third bonding layer 601 via a fourth bonding layer 709. The second integrated circuit die 701 may be attached to the third bonding layer 601 simultaneously with, before, or after attaching the dummy die 703 to the third bonding layer 601. The fourth bonding layer 709 may include a second dielectric layer 711 and second contact pads 713. The second dielectric layer 711 may include a silicon-containing dielectric material, such as silicon oxide, silicon nitride, etc., and the second dielectric layer 711 may be deposited using a suitable deposition process, such as CVD, PVD, ALD, HDPCVD, oxidation of the underlying material, combinations thereof, etc. The second contact pads 713 may be formed in a similar manner to the first bonding pads 605. Optionally, a planarization step may then be performed to make the top surface of the fourth bonding layer 709 flush, such that the fourth bonding layer 709 has a high degree of flatness (within process variations). Other materials and forming methods are also possible.

[0109] In some embodiments, the second integrated circuit die 701 is bonded to the third bonding layer 601 through a dielectric-to-dielectric bonding process and a metal-to-metal bonding process performed between the third bonding layer 601 and the fourth bonding layer 709. In some embodiments, the dielectric-to-dielectric bonding process forms a direct bond (e.g., a fusion bond such as an oxide-to-oxide bond) between the first dielectric layer 603 and the second dielectric layer 711. Additionally, the metal-to-metal bonding process can directly bond the first bonding pad 605 of the third bonding layer 601 to the second contact pad 713 of the second integrated circuit die 701 through direct metal-to-metal bonding. Thus, the electrical connection between the first integrated circuit die 50 and the second integrated circuit die 701 can be provided through the physical connection of the first bonding pad 605 to the second contact pad 713. The dielectric-to-dielectric bonding process can start from a surface treatment applied to one or both of the first dielectric layer 603 and the second dielectric layer 711, which promotes the dielectric-to-dielectric bond (e.g., a fusion bond such as an oxide-to-oxide bond) between the first dielectric layer 603 and the second dielectric layer 711. The surface treatment can include plasma treatment. The plasma treatment can be performed in a vacuum environment. After the plasma treatment, the surface treatment can further include a cleaning process (e.g., rinsing with deionized water, etc.) that can be applied to one or both of the first dielectric layer 603 and the second dielectric layer 711. Then, the dielectric-to-dielectric bonding process and the metal-to-metal bonding process can be continued to align the second contact pad 713 of the second integrated circuit die 701 with the first bonding pad 605 of the third bonding layer 601. Then, during the contact of the second integrated circuit die 701 with the third bonding layer 601, the dielectric-to-dielectric bonding process and the metal-to-metal bonding process include a pre-bonding step. The pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). The dielectric-to-dielectric bonding process and the metal-to-metal bonding process continue with annealing, for example, at a temperature between about 150°C and about 400°C for a duration between about 0.5 hours and about 3 hours, such that the first bonding pad 605 (e.g., copper) and the second contact pad 713 (e.g., copper) inter-diffuse with each other, thereby forming a direct metal-to-metal bond.

[0110] Figure 8A cross-sectional view showing one or more dummy dies 703 and one or more second integrated circuit dies 701 encapsulated by a second insulating material 801 is shown. The second insulating material 801 can be deposited over the one or more dummy dies 703 and the second integrated circuit dies 701, and can also be deposited in the gaps between the one or more dummy dies 703 and the second integrated circuit dies 701. The second insulating material 801 can be formed in a similar manner as the first insulating material 201. In some embodiments, the second insulating material 801 can be thinned in a similar manner as the first insulating material 201 such that the one or more dummy dies 703, the second integrated circuit dies 701, and the second insulating material 801 share a flat top surface (within process variations). The resulting structure of the one or more dummy dies 703, the second integrated circuit dies 701, and the thinned second insulating material 801 can be referred to as a second packaging device 800. In this embodiment, the second packaging device 800 can have a flat surface (within process variations).

[0111] Figure 9 A cross-sectional view showing the removal of the first carrier substrate 100 and the attachment of the second carrier substrate 900 is shown. In an embodiment, a fifth bonding layer 901 can be formed over the flat surface of the second packaging device 800. In an embodiment, the fifth bonding layer 901 can include oxides, such as silicon oxide, silicon oxynitride, etc. or a combination thereof, and can be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., chemical vapor deposition-based material deposition in a remote plasma system followed by post-curing to transform the material into an oxide), ALD, physical vapor deposition, etc. or a combination thereof. Other oxide materials formed by any acceptable process can be used to form the fifth bonding layer 901 over the second packaging device 800.

[0112] After forming the fifth bonding layer 901, the second carrier substrate 900 can be bonded to the fifth bonding layer 901 through a sixth bonding layer 903 of the second carrier substrate 900. In an embodiment, the sixth bonding layer 903 is formed over the second carrier substrate 900 and is formed in a similar manner and from similar materials as the fifth bonding layer 901. According to some embodiments, the second carrier substrate 900 includes silicon, etc. In an embodiment, the sixth bonding layer 903 is bonded to the fifth bonding layer 901 through a second dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding), forming a second dielectric-to-dielectric bond (e.g., oxide-to-oxide bond). The second dielectric-to-dielectric bonding process can be performed in a similar manner as the first dielectric-to-dielectric bonding process used to form the first dielectric-to-dielectric bond.

[0113] In addition, in an embodiment, the sixth bonding layer 903 may include a second alignment structure 905 embedded within the sixth bonding layer 903 to facilitate alignment of the second carrier substrate 900 with the second packaging device 800. The second alignment structure 905 may be formed in a similar manner and from similar materials as the first alignment structure 607.

[0114] Figure 9 The removal of the first carrier substrate 100 is further illustrated. In an embodiment, the first carrier substrate 100 and the first bonding layer 101 may be removed by a second planarization process 950. The second planarization process 950 may be a grinding process, a CMP process, etc. However, any suitable planarization process may be utilized. After removing the first carrier substrate 100 and the first bonding layer 101, a third dielectric layer 951 may be formed over the exposed bottom surface of the first packaging device 500. In an embodiment, the third dielectric layer 951 may include silicon oxide, silicon nitride, silicon oxynitride, a polymer, etc., and may be deposited by PVD, CVD, ALD, etc. Additionally, in an embodiment, a first passivation film 953 may be formed over the third dielectric layer 951. The first passivation film 953 may include silicon oxide, silicon oxynitride, silicon nitride, etc., and may be deposited by CVD, ALD, PVD, etc.

[0115] Figure 10A cross-sectional view of a first die interconnect 1001 formed in a first opening (not shown separately) through a third dielectric layer 951 and a first passivation film 953 is shown, and a conductive interconnect 1003 is formed over the first die interconnect 1001. In some embodiments, the first die interconnect 1001 extends through the first passivation film 951, the third dielectric layer 951, and the second bonding layer 103 to physically and electrically couple to a conductive pad of a first metallization pattern 55 of the first integrated circuit die 50. The first die interconnect 1001 may be formed of the same material as the second contact pad 713. In an embodiment, the conductive interconnect 1003 may be a ball grid array (BGA) interconnect, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel - electroless palladium - immersion gold (ENEPIG) technology, etc. The conductive interconnect 1003 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive interconnect 1003 is initially formed by evaporation, electroplating, printing, solder transfer, ball placement, etc. to form a solder layer. Once the solder layer is formed on the structure, a reflow may be performed to shape the material into a desired bump shape. In another embodiment, the conductive interconnect 1003 includes a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, etc. The metal pillar may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin - lead, gold, silver, palladium, indium, nickel - palladium - gold, nickel - gold, etc. or a combination thereof, and may be formed by an electroplating process.

[0116] According to some embodiments of the present disclosure, after the conductive interconnect 1003 is formed over the first die interconnect 1001, a first PoP device 1000 is formed. In an embodiment, the first PoP device 1000 includes a second carrier substrate 900 that supports a second packaging device 800 stacked over a first packaging device 500.

[0117] Figure 11A cross-sectional view showing an alternative embodiment of the first PoP device 1000 is presented, where the first packaging device 500 includes a plurality of first integrated circuit dies 50 (e.g., the first semiconductor die 50A and the second semiconductor die 50B) that are electrically coupled to local interconnects 1100 (also known as silicon bridges). In this embodiment, the first packaging device 500 is formed in the same or a similar manner as described above, including the formation of a thermal expansion layer 503, which is associated with each first integrated circuit die 50 and is associated with the shown first semiconductor die 50A and second semiconductor die 50B. The second packaging device 800 is formed in the same or a similar manner as described above, but has a plurality of second integrated circuit dies 701 shown (e.g., the third semiconductor die 701A and the fourth semiconductor die 701B). In the embodiment, in a manner similar to that described above regarding bonding and electrically coupling the first integrated circuit die 50 to the second integrated circuit die 701, the first semiconductor die 50A is bonded to and electrically coupled to the third semiconductor die 701A, and the second semiconductor die 50B is bonded to and electrically coupled to the fourth semiconductor die 701B. The circuit die 50 is bonded and electrically coupled to the second integrated circuit die 701. It should be noted that, although not shown separately, dummy die 703 may or may not be present in the second device package 800.

[0118] In this embodiment, the local interconnect 1100 includes an interconnect substrate 1101 that supports a second interconnect structure 1103, and the second interconnect structure 1103 includes a second metallization pattern 1105 (e.g., wires, vias, and conductive pads) in one or more second interconnect dielectric layers 1107. The second metallization pattern 1105 and the second interconnect dielectric layers 1107 may be formed in a manner similar to and from similar materials as those described regarding the first metallization pattern 55 and the first interconnect dielectric layer 57. In the embodiment, the interconnect substrate 1101 may be formed of silicon, e.g., bulk silicon. In the embodiment, the interconnect substrate 1101 may be formed in a manner similar to and from similar materials as the first semiconductor substrate 51. One of the conductive pads of the second metallization pattern 1105 and the second interconnect dielectric layer 1107 may be used to bond the local interconnect structure 1100 to the third bonding layer 601 within the second packaging device 800 in a manner similar to that described regarding bonding the fourth bonding layer 709 to the third bonding layer 601.

[0119] It should be noted that the other features and processes regarding the formation of the first PoP device 1000 described above are intended to be represented in Figure 11 the shown embodiment and may be formed in a manner similar to and from similar materials as those described regarding the formation of the first PoP device 1000.

[0120] Figure 12A cross-sectional view showing an alternative embodiment of the first PoP device 1000 is presented, where the oxide liner 501 is omitted during the formation of the first encapsulation device 800. In this embodiment, after the groove 303 is formed in the first integrated circuit die 50, the thermally expandable material 403 is deposited in a manner similar to the above, but without first depositing the oxide material 401, such that the thermally expandable material 403 is directly deposited on top of the first insulating material 201, on top of the exposed surface of the first semiconductor substrate 51, and on top of the exposed surface of the TSV 59. In this embodiment, after the planarization process 505, the thermally expandable layer 503 is in direct physical contact with the sidewalls of the first insulating material 201, the first semiconductor substrate 51, and the TSV 59.

[0121] It should be noted that the other features and processes regarding the formation of the first PoP device 1000 are intended to be represented in Figure 12 the embodiment shown, and can be formed in a similar manner and from similar materials as those regarding the formation of the first PoP device 1000 above.

[0122] Figure 13 A cross-sectional view showing the first integrated circuit die 50 is presented, where the oxide material 401 is deposited to completely fill the groove 303. In this embodiment, after the groove 303 is formed, the oxide material 401 is deposited in a manner similar to the above, but completely fills the groove 303. Then, a planarization process 505 can be performed to expose the TSV 59 through the oxide material 401 and form the oxide layer 1301 from the oxide material 401 in the groove 303. In this embodiment, the first insulating material 201, the oxide layer 1301, and the TSV 59 share a flat top surface (within process variations).

[0123] Figure 14 A cross-sectional view showing the second thermally expandable layer 1401 formed on top of the flat top surfaces of the first insulating material 201, the oxide layer 1301, and the TSV 59 is presented. In this embodiment, the second thermally expandable layer 1401 can be deposited in a manner similar to the thermally expandable material 403 and from similar materials, but extends on top of the top surface of the TSV 59 and on top of the top surface of the first insulating material 201, rather than extending between the TSV 59s and between the first insulating materials 201. In this embodiment, the second thermally expandable layer 1401 can have a first thickness TH1 and a first hardness. If the second thermally expandable layer 1401 does not have the first thickness TH1 or the first hardness, the overall structure may experience the same results as those regarding the first thickness TH1 and the first hardness of the thermally expandable layer 503.

[0124] Figure 15A cross-sectional view is shown in which a seventh bonding layer 1501 is formed over a second thermally expandable layer 1401. In this embodiment, the seventh bonding layer 1501 may be formed in a similar manner and from similar materials as the third bonding layer 601, except that during the formation of the first bonding pad 605, the first bonding pad 605 extends through the first dielectric layer 603 and through the second thermally expandable layer 1401 to physically and electrically couple to the TSV 59. Additionally, in this embodiment, the first alignment structure 607 may also extend through the first dielectric layer 603 and through the second thermally expandable layer 1401. In Figure 15 The resulting structure shown may be referred to as a third packaged device 1500.

[0125] Figure 16 A cross-sectional view of a second PoP device 1600 is shown that includes a third packaged device 1500, a second packaged device 800, a second carrier substrate 900, and conductive connectors 1003. It should be noted that when forming the second PoP device 1600, the other features and processes regarding the formation of the first PoP device 1000 described above are intended to be represented in Figure 16 the embodiment shown and may be formed in a similar manner and from similar materials as described above regarding the formation of the first PoP device 1000.

[0126] Figure 17 A cross-sectional view of an alternative embodiment of the second PoP device 1600 is shown, in which the third packaged device 1500 includes a plurality of first integrated circuit dies 50 (e.g., a first semiconductor die 50A and a second semiconductor die 50B) that are electrically coupled to local interconnects 1100. In this embodiment, the third packaged device 1500 is formed in the same or a similar manner as described above, including the formation of a second thermally expandable layer 1401 that is associated with each first integrated circuit die 50 and is associated with the first semiconductor die 50A and the second semiconductor die 50B shown. The second packaged device 800 is formed in the same or a similar manner as described above, but has a plurality of second integrated circuit dies 701 (e.g., a third semiconductor die 701A and a fourth semiconductor die 701B) shown. In the embodiment, the first semiconductor die 50A is bonded to and electrically coupled to the third semiconductor die 701A, and the second semiconductor die 50B is bonded to and electrically coupled to the fourth semiconductor die 701B in a similar manner as described above regarding bonding and electrically coupling the first integrated circuit die 50 to the second integrated circuit die 701. It should be noted that although not shown separately, dummy die 703 may or may not be present in the second device package 800. The local interconnects 1100 may be formed in the same or a similar manner and from the same or similar materials as described above.

[0127] It should be noted that when forming the second PoP device 1600, the other features and processes regarding the formation of the first PoP device 1000 described above are intended to be represented in Figure 17 the embodiment shown, and can be formed in a similar manner and from similar materials as described above regarding the formation of the first PoP device 1000.

[0128] Figure 18 A cross-sectional view is shown in which an oxide layer 1301 is formed in a groove 303 over a first integrated circuit die 50 and a third bonding layer 601 is formed directly over the oxide layer 1301. In this embodiment, after forming the oxide layer 1301, the formation of the second thermal expansion layer 1401 is omitted, and the third bonding layer 601 is formed directly over the oxide layer 1301 and over the top surface of the first insulating material 201. Figure 18 The structure shown can be referred to as a fourth packaging device 1800.

[0129] Figure 19 A cross-sectional view is shown in which a fifth packaging device 1900 is formed over the fourth packaging device 1800. In the embodiment, the fifth packaging device 1900 includes a second integrated circuit die 701, dummy dies 703, a second insulating material 801 encapsulating both the second integrated circuit die 701 and the dummy dies 703, a third thermal expansion layer 1901, and a fifth bonding layer 901. The second integrated circuit die 701 and the dummy dies 703 can be bonded to the third bonding layer 601 in a similar manner as described above regarding bonding the dummy dies 703 to the third bonding layer 601 and bonding the second integrated circuit die 701 to the third bonding layer 601. In some embodiments, the second insulating material 801 can be thinned in a similar manner as the first insulating material 201 such that one or more of the dummy dies 703, the second integrated circuit die 701, and the second insulating material 801 share a flat top surface (within process variations). After thinning the second insulating material 801, the third thermal expansion layer 1901 can be formed over the flat top surface. In the embodiment, the third thermal expansion layer 1901 can be formed in a similar manner and from similar materials as described regarding the second thermal expansion layer 1401. In the embodiment, the third thermal expansion layer 1901 can be formed to have a first thickness TH1 and a first hardness. If the third thermal expansion layer 1901 does not have the first thickness TH1 or the first hardness, the overall structure may experience the same results as described regarding the first thickness TH1 and the first hardness of the thermal expansion layer 503. After forming the third thermal expansion layer 1901, the fifth bonding layer 901 can be formed over the third thermal expansion layer 1901.

[0130] Figure 20A cross-sectional view of a third PoP device 2000 including a fourth encapsulation device 1800, a fifth encapsulation device 1900, a second carrier substrate 900, and a conductive connection member 1003 is shown. It should be noted that when forming the third PoP device 2000, other features and processes regarding the formation of the first PoP device 1000 as described above are intended to be represented in Figure 20 the embodiment shown and may be formed in a similar manner and from similar materials as those regarding the formation of the first PoP device 1000 described above. In addition, it should be noted that the third PoP device 2000 may also include a plurality of first integrated circuit dies 50 (not shown separately), a plurality of second integrated circuit dies 701 (not shown separately), and local interconnections 1100 in a similar manner to the representative embodiments shown in Figure 11 and Figure 17 .

[0131] Other features and processes may also be included. For example, a test structure may be included to assist in verifying the testing of 3D packaging or 3DIC devices. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, which allow the use of testing, probing, and / or probe cards for 3D packaging or 3DIC. Verification testing may be performed on intermediate structures as well as final structures. Additionally, the structures and methods disclosed herein may be used in combination with testing methods incorporating intermediate verification of known good dies to increase yield and reduce costs.

[0132] Embodiments may achieve advantages. According to some embodiments, the use of a thermally expandable material (e.g., silicon nitride), such as in the thermally expandable layer 503, the second thermally expandable layer 1401, and the third thermally expandable layer 1901, reduces the risk of delamination within the first PoP device 1000, the second PoP device 1600, and the third PoP device 2000, which may cause delamination at the boundary layer (e.g., between the third bonding layer 601 and the fourth bonding layer 709) by suppressing stamping caused by thermal mismatch within the PoP device. By utilizing the thermally expandable layers within the PoP device, the reliability of the PoP device can be improved, which may additionally help reduce the overall cost of manufacturing the PoP device.

[0133] According to some embodiments, a device includes a first semiconductor package, the first semiconductor package including a first semiconductor die encapsulated in an insulating material, a first thermal expansion layer positioned over the first semiconductor die, a bonding layer positioned over the first thermal expansion layer and the insulating material, and a second semiconductor die directly bonded to the bonding layer. In an embodiment, the first thermal expansion layer extends over a top surface of the insulating material. In an embodiment, the insulating material encapsulates both the first semiconductor package and the first thermal expansion layer. In an embodiment, the first thermal expansion layer has a thickness in the range of to . In an embodiment, the first thermal expansion layer includes silicon nitride. In an embodiment, a third semiconductor die adjacent to the first semiconductor die is further included, wherein the first thermal expansion layer extends over the third semiconductor die. In an embodiment, a third semiconductor die adjacent to the first semiconductor die is further included, wherein the bonding layer extends over the third semiconductor die, and a second thermal expansion layer is disposed between the third semiconductor die and the bonding layer. In an embodiment, a third semiconductor die adjacent to the first semiconductor die and a local silicon interconnect adjacent to the second semiconductor die are further included, the local silicon interconnect electrically coupling the first semiconductor die to the third semiconductor die.

[0134] According to some embodiments, a method of manufacturing a semiconductor device includes depositing a thermal expansion layer over a first semiconductor die, forming a bonding layer over the thermal expansion layer opposite the first semiconductor die, and bonding a second semiconductor die to the bonding layer using dielectric-to-dielectric bonding and metal-to-metal bonding, wherein bonding the second semiconductor die to the bonding layer electrically couples the first semiconductor die to the second semiconductor die. In an embodiment, forming the thermal expansion layer has a hardness in the range of 10 GPa to 30 GPa. In an embodiment, forming an oxide pad around the thermal expansion layer is further included. In an embodiment, the thermal expansion layer extends over a third semiconductor die adjacent to the first semiconductor die. In an embodiment, forming the bonding layer includes forming a bonding pad embedded in the bonding layer, the bonding pad contacting a top surface of the thermal expansion layer. In an embodiment, forming the bonding layer includes forming a bonding pad in the bonding layer and extending into the thermal expansion layer.

[0135] According to some embodiments, a device includes a first semiconductor die embedded in a first insulating layer, a second semiconductor die adjacent to the first semiconductor die embedded in the first insulating layer, a first nitride layer over the first semiconductor die, a bonding layer over the first nitride layer opposite the first semiconductor die, and a third semiconductor die bonded to the bonding layer opposite the first semiconductor die. In an embodiment, the first nitride layer extends over the second semiconductor die. In an embodiment, a second nitride layer is further included over the second semiconductor die, wherein the second nitride layer is disposed between the second semiconductor die and the bonding layer. In an embodiment, a silicon bridge bonded to the bonding layer is further included, and the silicon bridge electrically couples the first semiconductor die to the second semiconductor die. In an embodiment, a dummy die bonded to the bonding layer opposite the first semiconductor die is further included. In an embodiment, a conductive bonding pad extending through both the bonding layer and the first nitride layer is further included.

[0136] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A first semiconductor package including a first semiconductor die encapsulated in an insulating material; A first thermal expansion layer positioned over the first semiconductor die; A bonding layer positioned over the first thermal expansion layer and the insulating material; And A second semiconductor die directly bonded to the bonding layer.

2. The semiconductor device according to claim 1, wherein The first thermal expansion layer extends over the top surface of the insulating material.

3. The semiconductor device according to claim 1, wherein Further comprising a third semiconductor die adjacent to the first semiconductor die, wherein the first thermal expansion layer extends over the third semiconductor die.

4. The semiconductor device according to claim 1, wherein Further comprising a third semiconductor die adjacent to the first semiconductor die, wherein the bonding layer extends over the third semiconductor die, and wherein a second thermal expansion layer is disposed between the third semiconductor die and the bonding layer.

5. The semiconductor device according to claim 1, wherein Further comprising: A third semiconductor die adjacent to the first semiconductor die; And A local silicon interconnect adjacent to the second semiconductor die, the local silicon interconnect electrically coupling the first semiconductor die to the third semiconductor die.

6. A semiconductor device, characterized in that, Comprising: A first semiconductor die embedded in a first insulating layer; A second semiconductor die adjacent to the first semiconductor die embedded in the first insulating layer; A first nitride layer positioned over the first semiconductor die; A bonding layer positioned over the first nitride layer opposite the first semiconductor die; And A third semiconductor die bonded to the bonding layer opposite the first semiconductor die.

7. The semiconductor device according to claim 6, wherein The first nitride layer extends over the second semiconductor die.

8. The semiconductor device according to claim 6, wherein Further comprising a second nitride layer over the second semiconductor die, wherein the second nitride layer is disposed between the second semiconductor die and the bonding layer.

9. The semiconductor device according to claim 6, wherein Further comprising a silicon bridge bonded to the bonding layer, the silicon bridge electrically coupling the first semiconductor die to the second semiconductor die.

10. The semiconductor device according to claim 6, wherein, Further comprising a conductive bonding pad extending through both the bonding layer and the first nitride layer.

Images