Photonic device structure and photonic semiconductor device

Abstract

A photonic device structure and a photonic semiconductor device are provided, the photonic device structure including a substrate having a top-side oxide layer thereon. The photonic device structure includes a silicon layer on the top side oxide layer, and one or more waveguide components in the silicon layer. In addition, the photonic device structure includes a reflection device trench structure in the silicon layer, and the reflection device trench structure includes a first inclined surface, a bottom surface, and a second inclined surface. The photonic device structure includes a reflective device adjacent to the first inclined surface, and the reflective device has a reflective device angle relative to the bottom surface and is configured to guide light into the waveguide assembly.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a photon device structure and a photon semiconductor device. Background Art

[0002] As integrated circuits (ICs) become smaller and faster, the electrical signals used in various types of ICs are also affected by increasing delays caused by capacitance, inductance, or resistance in the ICs. At certain high speeds and / or frequencies, such delays become a design problem. To avoid potential signal delay problems, in some cases, optical signals are used instead of electrical signals for data transmission. Summary of the Utility Model

[0003] According to some embodiments, a photon device structure is provided, including a substrate having a top oxide layer thereon. The photon device structure further includes a silicon layer located on the top oxide layer, and at least one waveguide component located in the silicon layer. The photon device structure further includes a reflection device trench structure located in the silicon layer, the reflection device trench structure having a first inclined surface, a bottom surface, and a second inclined surface. The photon device structure further includes a reflection device adjacent to the first inclined surface, the reflection device having a reflection device angle relative to the bottom surface and configured to guide light into the waveguide component.

[0004] According to some embodiments, a photon semiconductor device is provided, including a substrate and a first top oxide layer located on the substrate. The photon semiconductor device further includes a silicon layer located on the first top oxide layer, the silicon layer including a strip waveguide component, a rib-to-strip waveguide component, and at least one rib waveguide component. The photon semiconductor device further includes a reflection device trench structure located in the silicon layer, the reflection device having a first inclined surface, a bottom surface, and a second inclined surface. The photon semiconductor device further includes a reflection device adjacent to the first inclined surface. The reflection device has a reflection device angle relative to the bottom surface and is configured to guide light into at least one of the strip waveguide component, the rib-to-strip waveguide component, and the rib waveguide component.

[0005] According to some embodiments, a photon device structure is provided. The photon device structure includes a substrate having a top oxide layer thereon. The photon device structure further includes a silicon layer located on the top oxide layer, and at least one waveguide component located in the silicon layer. The photon device structure further includes a reflection device trench structure located in the silicon layer, the reflection device trench structure having a first inclined surface, a bottom surface, and a second inclined surface. The photon device structure further includes a reflection device adjacent to the first inclined surface, the reflection device having a reflection device angle relative to the bottom surface and configured to guide light into the waveguide component, wherein the reflection device further includes a plurality of high-reflection coatings. Description of the Drawings

[0006] As will be best understood in conjunction with the accompanying drawings, aspects of some embodiments of the present disclosure will be best understood from the following detailed description. Note that, in accordance with standard practice in the art, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a cross-sectional view of a photon device according to some embodiments; Figures 2A to 2V is a cross-sectional view of a stage of a portion of a photon device being fabricated according to some embodiments Figure 1 of; Figures 3A to 3D is a cross-sectional view of a stage of a portion of a photon device being fabricated according to some embodiments Figure 1 and Figures 2A to 2V of;

[0008] Figures 4A to 4I is a cross-sectional view of a stage of fabricating a reflection device and a reflection device trench structure of a photon device according to some embodiments Figure 1 of;

[0009] Figures 5A to 5C is a cross-sectional view of different embodiments of a reflection device and a reflection device trench structure;

[0010] Figure 6 is a flowchart of a method of fabricating a photon device structure according to some embodiments;

[0011] Figure 7 is a flowchart of a method of fabricating a photon device according to some embodiments.

[0012]

Symbol Description

[0013] 100: Photon device

[0014] 102: Substrate

[0015] 104: Back oxide layer

[0016] 106: First top-side oxide layer

[0017] 108: Silicon layer

[0018] 110: Distributed Bragg reflector

[0019] 112: First etch stop layer

[0020] 114: Reflection device

[0021] 116: Reflection device trench structure

[0022] 118: Waveguide assembly

[0023] 120: Waveguide assembly

[0024] 122: Waveguide component

[0025] 124: Waveguide component

[0026] 128: Silicate glass material

[0027] 130: Undoped silicate glass component

[0028] 132: Contact etch stop layer

[0029] 134: Contact hole

[0030] 135: First inclined plane

[0031] 136: Bottom surface

[0032] 137: Second inclined plane

[0033] 138: Contact

[0034] 142: Bump pad

[0035] 140: Metal component

[0036] 144: Thickness

[0037] 146: Thickness

[0038] 148: Thickness

[0039] 152: Metal component

[0040] 154: Second top-side oxide layer

[0041] 156: Second etch stop layer

[0042] 158: Third top-side oxide layer

[0043] 160: Third etch stop layer

[0044] 162: Fourth top-side oxide layer

[0045] 164: Fourth etch stop layer

[0046] 166: Doped component

[0047] 168: Doped component

[0048] 170: Depth

[0049] 172: Hard mask

[0050] 174,180,184,188,192,194,196,200,204,218: Photoresist

[0051] 176: Hole

[0052] 178: Polyimide layer

[0053] 182: Hole

[0054] 186: Strip-shaped hole

[0055] 190: R2S hole

[0056] 198: Contact cavity

[0057] 202: Oxide

[0058] 206: Hard mask opening

[0059] 208: Angle

[0060] 210: Length

[0061] 212: Oxide layer

[0062] 214: Thickness

[0063] 216: Reflective layer

[0064] 220: Thickness

[0065] 222: Length

[0066] 224: Angle

[0067] 226: Reflective device

[0068] 600,700: Flowchart

[0069] 602,604,606,608,610,612,614,616,620,622,624,626,628,702,704,706,708,710,712,714,716,718,720,722,724: Steps Detailed implementation

[0070] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify some embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, forming the first feature above or on the second feature in the following description may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, some embodiments of the present disclosure may repeat reference numerals and / or letters in various instances. This repetition is for simplicity and clarity purposes and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0071] In addition, for ease of description, in some embodiments of the present disclosure, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used to describe the relationship of one element or feature to another (other) element or feature, as shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used in some embodiments of the present disclosure may be interpreted accordingly.

[0072] The term "about" may be used to include any numerical value that can be varied without changing the basic function of the value. When used with a range, "about" also discloses the range defined by the absolute values of the two endpoints. For example, "about 2 to about 4" also discloses the range of "2 to 4". The term "about" may refer to plus or minus 10% of the indicated number.

[0073] Some embodiments of the present disclosure relate to structures composed of different layers. When the terms "on" or "above" are used with respect to two different layers (including the substrate), they only indicate that one layer is on or above the other layer. These terms do not require the two layers to be in direct contact with each other, and allow other layers to be located between the two layers. For example, all layers of the structure can be considered to be "on" the substrate, even if they do not all directly contact the substrate. The term "directly" can be used to indicate that two layers are in direct contact with each other and there is no layer between them. Additionally, when referring to performing a process step on the substrate, this should be understood, depending on the context, to also perform such a step on any layer that may be present on the substrate.

[0074] The rib waveguide includes a contact that extends through the contact etch stop layer to contact the underlying dopant region. An oxide hard mask or layer deposited on the contact etch stop layer may collapse during patterning of the contact etch stop layer and / or patterning of the contact itself. According to some embodiments described in the present disclosure, rib grooves are used to prevent mask collapse during patterning of the etch stop layer. Light sources used in photon devices, such as lasers or optical fibers, require subsequent processing of the device for cutting, insertion, facet formation, and in the case of lasers, require separate manufacturing processes. According to some embodiments, a photon device is described in which an external light source can be used without post-device modification. That is, in some embodiments described in the present disclosure, a photon device is provided that has an integrated mirror assembly formed within the photon device, and the integrated mirror assembly guides an external light source to a waveguide formed therein.

[0075] Now turning to Figure 1 , a photon device 100 according to one embodiment is illustrated. As Figure 1As shown, the photon device 100 includes a substrate 102 having a back oxide layer 104 and a first top-side oxide layer 106. According to some embodiments, the substrate 102 may comprise, for example and without limitation, silicon, such as silicon in the form of, for example and without limitation, crystalline Si or polycrystalline Si. In alternative embodiments, the substrate 102 may be made of other elemental semiconductors such as germanium, or may include compound semiconductors such as silicon carbide (SiC), gallium arsenide (GaAs), gallium carbide, gallium phosphide, indium arsenide (InAs), indium phosphide (InP), silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or gallium indium phosphide. According to one embodiment, the substrate 102 may be implemented as a SOI substrate, i.e., a silicon-on-insulator substrate. In such an embodiment, the substrate 102 may comprise, for example and without limitation, silicon oxide or other suitable insulating materials.

[0076] According to some embodiments, the back oxide layer 104 and the first top-side oxide layer 106 may comprise, for example and without limitation, non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. In such embodiments, the back oxide layer 104 and the first top-side oxide layer 106 may have a thickness 144 in the range of 0.5 micrometer (μm) to 3 μm, and in some embodiments, may have a thickness of 2 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. As Figure 1 shown, the photon device 100 further includes a first silicon layer 108 formed on the first top-side oxide layer 106. According to some embodiments, the first silicon layer 108 may comprise silicon, such as silicon in the form of, for example and without limitation, crystalline Si or polycrystalline Si. According to some embodiments, the first silicon layer 108 may be implemented as having a thickness 146 in the range of 1 μm to 5 μm, and in some embodiments, may have a thickness of 3 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. A distributed Bragg reflector (DBR) 110 is formed on the top portion of the first silicon layer 108, as Figure 1 depicted therein. It should be understood that the construction and / or location of the distributed Bragg reflector 110 may depend on the particular application in which the photon device 100 is used, the desired wavelength traveling therethrough, etc.

[0077] Figure 1The photonic device 100 further includes a first etch stop layer 112, which is formed on various portions of the substrate 102 and additional layers of the photonic device 100, as described in some embodiments of the present disclosure. It should be understood that the first etch stop layer 112 may include any suitable barrier material for protecting underlying layers and components from damage during subsequent etching processes. The first etch stop layer 112 can be implemented as tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc. It should be understood that the first etch stop layer 112 corresponds to a material layer having etching characteristics that are significantly different from the material to be etched, thereby stopping or terminating the etching process of the layer deposited on the etch stop layer. According to one embodiment, a reflective device 114, such as a metal film, a quarter-wave stack (high reflective coating / Bragg mirror), is formed on one side of the photonic device 100 from a material having suitable reflective characteristics within a portion of the first top side oxide layer 106, such as Figure 1 In some embodiments, the reflector 114 is positioned adjacent to a reflector groove structure 116 extending downwardly into the substrate 102, such as Figure 1 According to such an embodiment, the reflector 114 may include a metal alloy material, such as but not limited to Al, AlCu, AlSiCu, AlSi, AlCr, etc. In other embodiments, the reflector 114 may utilize a reflective coating or a high reflective coating on its surface, including, for example but not limited to SiO2 / TiOx, AlAs / GaAs, AlN / GaN, etc. Figures 5A to 5C An exemplary illustration of the reflective device 114 is discussed in more detail.

[0078] Figure 1 The photonic device 100 shown in FIG. 1 further includes an echelle grating component 118, a strip waveguide component 120, a rib to strip (R2S) waveguide component 122, and a rib waveguide component 124. Each of the above waveguide components 118-124 is suitably at least partially located in the first silicon layer 108. Figure 1 As shown, a silicate glass material 128 is formed within each of the waveguide components 118-124, as described below with respect to Figures 2A to 2V More detailed description. That is, Figure 1 , a silicate glass material 128 may be deposited between portions of the first silicon layer 108, the combination of which provides a structure for the waveguide components 118-124 described above. According to an exemplary embodiment, the silicate glass material 128 is a borophosphosilicate glass (BPSG) material. It should be understood that other suitable silicate glasses or materials that provide similar optical properties and / or insulating properties may be used in other embodiments.

[0079] According to some embodiments, the echelle grating waveguide assembly 118 may correspond to a type of diffraction grating having a relatively low groove density and a groove shape optimized for use at high incident angles and thus having high diffraction orders. In such embodiments, the echelle grating waveguide assembly 118 may further include a metal assembly 152, such as an AlCu assembly, which may be used as a mirror to reflect incident light. According to additional embodiments, the strip waveguide assembly 120 may correspond to a type of waveguide having the form of a channel extending along the surface of a solid transparent host medium, such as a dielectric or semiconductor. The rib-to-strip waveguide assembly 122 may correspond to a converter assembly that converts a rib waveguide output to a strip waveguide input and / or converts a strip waveguide output to a rib waveguide input. Additionally, as Figure 1 shown, the photonic device 100 includes a rib waveguide assembly 124, which may correspond to a waveguide in which the guiding layer may be composed of a bottom plate and a strip (or strips) superimposed thereon. As will be understood by those skilled in the art, a rib waveguide can provide confinement of waves in two dimensions, and nearly uniform confinement is possible in a multi-layer rib structure. It should be understood that although Figure 1 a single rib waveguide assembly 124 is shown in Figure 1 , the photonic device 100 may be implemented with multiple rib waveguide assemblies, such as three, four, five, etc., depending on the desired design configuration. Thus,

[0080] as Figure 1 shown, the photonic device 100 further includes an undoped silicate glass (USG) assembly 130 disposed on the first silicon layer 108 and the borophosphosilicate glass (BPSG) material 128. In some embodiments, the undoped silicate glass (USG) assembly 130 may be implemented with a thickness 148 in the range of 5,000 angstroms to 10,000 angstroms. In one embodiment, the undoped silicate glass (USG) assembly 130 is implanted with a thickness of 8 angstroms. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0081] A second etch stop layer 156 is formed on the undoped silicate glass assembly 130, as Figure 1As shown. According to some embodiments, the second etch stop layer 156 may include any suitable barrier material for protecting the underlying layers and components from damage during subsequent etch processes. The second etch stop layer 156 may be implemented as tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc. It should be understood that the second etch stop layer 156 corresponds to a material layer having etching characteristics that are significantly different from the material to be etched, thereby stopping or aborting the etching process of the layer deposited on the etch stop layer.

[0082] Above the second etch stop layer 156 is the second top-side oxide layer 154. The third top-side oxide layer 158 is suitably formed on the second etch stop layer 156, as Figure 1 shown. According to some embodiments, the second top-side oxide layer 154 and the third top-side oxide layer 158 may include, for example and without limitation, non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxynitride (SiOCN), etc. Figure 1 The third etch stop layer 160 is depicted in which is formed on the third top-side oxide layer 158. As indicated above regarding the first etch stop layer 112 and the second etch stop layer 156, the third etch stop layer 160 suitably includes a material layer having etching characteristics that are significantly different from the material to be etched, thereby stopping or aborting the etching process of the layer deposited on the etch stop layer. Thus, the third etch stop layer 160 may include, for example and without limitation, tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc.

[0083] According to some embodiments, Figure 1 the photon device 100 further includes a fourth top-side oxide layer 162 formed or deposited on the third etch stop layer 160. Such a fourth top-side oxide layer 162 may include, for example and without limitation, non-low-k dielectric materials such as silicon oxide, SiC, SiCN, SiOCN, etc. The fourth etch stop layer 164 may be formed on the fourth top-side oxide layer 162, as Figure 1 shown. In some embodiments, the fourth etch stop layer 164 may include, for example and without limitation, tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc. In the different embodiments disclosed in this disclosure, the first top-side oxide layer 106, the second top-side oxide layer 154, the third top-side oxide layer 158, and the fourth top-side oxide layer 162 may include the same or different oxide materials. In some embodiments, the above-mentioned first top-side oxide layer 106, second top-side oxide layer 154, third top-side oxide layer 158, and fourth top-side oxide layer 162 may include the same oxide material deposited or formed at different times or stages during the manufacture of the photon device 100.

[0084] In Figure 1In [description], the ribbed waveguide assembly 124 includes ribbed contact holes 134 extending a preselected distance into the first silicon layer 108, a contact etch stop layer (CESL) 132 formed on the bottom of the ribbed contact holes 134, ribbed contacts 138 formed of a suitable conductive material extending through the ribbed contact holes 134, ribbed N+ doped components 166, and P+ doped components 168 located below the contact etch stop layer (CESL) 132 within the first silicon layer 108. As Figure 1 As shown in [description], each contact hole 134 includes the above-mentioned silicate glass material 128. According to some embodiments, the thickness or depth of the contact etch stop layer (CESL) 132 is 5% or more of the depth 170 of the contact hole 134.

[0085] As will be appreciated, doping for forming the doped components 166 and 168 can be accomplished, for example, by ion implantation. Briefly, an ion implanter is used to implant atoms into the silicon lattice, thereby changing the conductivity of the lattice at the implantation location. An ion implanter typically includes an ion source, a beam line, and a processing chamber. The ion source generates the desired ions (e.g., Co, Ti, Ni, Pt, or Pb, depending on the desired N-type or P-type electrode). The beam line organizes the ions into a beam with high purity in terms of ion mass, energy, and species. Then, the wafer substrate in the processing chamber is irradiated with the ion beam. The ion beam impinges on the exposed areas on the wafer substrate, and the ions can be implanted into the substrate as dopants at the desired depth. Alternatively, the substrate can be partially etched, then a blanket deposition of metal is performed, followed by annealing, where the metal reacts with the underlying exposed silicon. Then, the unreacted metal can be removed, for example, by a selective etching process. As Figure 1 As shown in [description], the contact hole 134 has a contact hole depth 170 extending into the first silicon layer 108 between 8,000 angstroms and 14,000 angstroms. In other embodiments, the contact hole depth 170 ranges from extending into the first silicon layer 108 between 9,000 angstroms and 12,000 angstroms. However, other values and ranges are within the scope of some embodiments of the present disclosure. It should also be understood that the contacts 138 extend through the contact etch stop layer (CESL) 132 to contact the corresponding first ribbed doped components 166 and 168.

[0086] According to some embodiments, the contacts 138 are in electrical contact with a metal component 140 partially formed between the second top-side oxide layer 154 and the third top-side oxide layer 158, as Figure 1As shown. According to such an embodiment, each metal component 140 that provides a function similar to that of a conductor is in electrical contact with a corresponding bump pad 142. It should be understood that the metal component 140 can be implemented as, for example and without limitation, any suitable conductive material, including, for example and without limitation, suitable conductive metals, including, for example and without limitation, copper, aluminum, iron, and their alloys. In addition, some embodiments disclosed in the present disclosure may utilize bump pads 142 including, for example and without limitation, Al, Fe, Cu, Al-Cu, their alloys, or any other suitable materials, as will be understood by those skilled in the art. As Figure 1 shown, each of the bump pads 142 is suitably disposed through the fourth top-side oxide layer 162. Subsequent manufacturing (not shown) may include adding one or more solder bumps, which include lead alloy solder, lead-free solder, flux-cored solder, silver alloy solder, etc.

[0087] As Figure 1 shown, the photon device 100 further includes a reflective device trench structure 116 formed in the substrate 102. The reflective device trench structure 116 includes a first inclined surface 135, a bottom surface 136, and a second inclined surface 137. As Figure 1 shown, the first inclined surface 135 and the second inclined surface 137 are positioned opposite to each other and separated by the bottom surface 136. It should be understood that the length of the bottom surface 136 can vary according to design requirements. In addition, as Figure 1 shown, the size of the reflective device trench structure 116 can vary such that it can extend below the echelle grating assembly 118 or be located in front of the echelle grating assembly 118. As Figure 1 shown, the reflective device 114 is positioned relatively parallel to the first inclined surface 135, that is, having the same angle with respect to the waveguide assembly 118-124. According to one embodiment, Figure 1 the photon device 100 of

[0088] Now turning to Figures 2A to 2V , there is shown a manufacturing according to some embodiments Figure 1A series of intermediate stages of the optical components of the photon device 100. The patterning of the layer can employ any suitable patterning technique, such as photolithography patterning techniques, which use photoresist layer deposition and selective exposure via a photomask to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), etc., and then develop the exposed photoresist, followed by etching, deposition, or other process steps laterally scribed by the developed photoresist. In other embodiments, the patterning of the electron-sensitive resist layer can be performed by electron beam exposure (electron beam lithography, i.e., e-beam lithography). Those skilled in the art will understand that the foregoing are merely illustrative examples.

[0089] As Figure 2A shown, the substrate 102 is formed to have a back oxide layer 104. In some embodiments, the back oxide layer 104 includes a polyimide layer 178 formed on its surface opposite to the surface in contact with the substrate 102. According to one embodiment, the substrate 102 is an SOI substrate, as described above with respect to Figure 1 described.

[0090] In Figure 2B this, a first top-side oxide layer 106 is formed on the substrate 102. As Figure 2B shown, the first top-side oxide layer 106 is deposited on the top side of the substrate, which is opposite to the side of the substrate 102 to which the back oxide layer 104 is attached. As described above, the first top-side oxide layer 106 can include, for example and without limitation, non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. According to some embodiments, the formation of the first top-side oxide layer 106 can be accomplished via any suitable deposition or layer process, including, for example and without limitation, deposition by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. In some embodiments, chemical-mechanical polishing (CMP) can be performed after depositing the first top-side oxide layer 106, resulting in a planar surface as Figure 2B shown.

[0091] The first silicon layer 108 is then deposited on the first top-side oxide layer 106, as Figure 2CAs shown. Suitable methods for forming the first silicon layer 108 may include, for example and without limitation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. In some embodiments, chemical-mechanical polishing (CMP) may be performed after depositing the first silicon layer 108, resulting in a planar surface as shown in Figure 2C The first silicon layer 108 may comprise silicon, such as, for example and without limitation, silicon in the form of crystalline Si or polycrystalline Si. According to some embodiments, the first silicon layer 108 may be implemented with a thickness in the range of 1 μm to 5 μm, and in some embodiments, may have a thickness of 3 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0092] A hard mask 172 is then formed on the first silicon layer 108, as depicted in Figure 2D According to some embodiments, the hard mask 172 comprises a plurality of oxide material layers with a polyimide layer disposed therebetween. In some embodiments, a first oxide material is deposited, followed by CMP, and then a polyimide material is deposited. After performing CMP on the polyimide material, a second oxide material is deposited, followed by CMP, resulting in an intermediate manufacturing stage as shown in Figure 2D As discussed above, various deposition methods may be used to produce the hard mask 172, as will be understood by those skilled in the art.

[0093] A photoresist 174 is then deposited and patterned on the hard mask 172, as shown in Figure 2E In some embodiments, the photoresist 174 is coated onto the hard mask 172 and then portions of the photoresist 174 are developed by exposure from a suitable light source to form a pattern thereon. The unexposed portions are then removed, resulting in Figure 2EThe patterned photoresist 174 as shown. Then, etching is performed to remove those portions of the hard mask 172 and / or the underlying first silicon layer 108 to form distributed Bragg reflector (DBR) holes 176. Suitable removal processes include, for example and without limitation, etching processes implemented as dry etching processes, RIE processes, wet etching processes, some other etching process, or a combination of the foregoing processes. According to some embodiments, the DBR holes 176 can be implemented to have a depth in the range of 0.01 μm to 0.6 μm, and in some embodiments, the depth of the DBR holes 176 can be less than or equal to 0.4 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. Figure 2F A diagram of the photon device 100 after the formation of the DBR holes 176 is provided. Then, the DBR holes 176 are filled with a suitable material having a desired refractive index to form the distributed Bragg reflector 110, as Figure 2G shown. According to some embodiments, the DBR holes 176 are filled with silicate glass, oxide materials (including, for example and without limitation, undoped silicate glass, BPSG glass, etc.).

[0094] In Figure 2H , then, a photoresist 180 is deposited and patterned on the hard mask 172. In some embodiments, the photoresist 180 is coated onto the hard mask 172, and then portions of the photoresist 180 are developed by exposure from a suitable light source to form a pattern thereon. Then, the unexposed portions are removed, resulting in Figure 2H the patterned photoresist 180 as shown. Then, etching is performed to remove those portions of the hard mask 172 and / or the underlying first silicon layer 108 to form strip-shaped and rib-shaped hard mask holes 182, as Figure 2I shown. Suitable removal processes include, for example and without limitation, etching processes implemented as dry etching processes, RIE processes, wet etching processes, some other etching process, or a combination of the foregoing processes.

[0095] Then, a photoresist 184 is deposited and patterned on the hard mask 172, as Figure 2J shown. In some embodiments, the photoresist 184 is coated onto the hard mask 172, and then portions of the photoresist 184 are developed by exposure from a suitable light source to form a pattern thereon. Then, the unexposed portions are removed, resulting in Figure 2J the patterned photoresist 184 as shown. Then, etching is performed to remove those portions of the first silicon layer 108 to enable the formation of strip-shaped holes 186 and a portion of the R2S holes 190, as Figure 2Kas shown. Suitable removal processes include, for example and without limitation, etching processes, which are implemented as dry etching processes, RIE processes, wet etching processes, some other etching process, or a combination of the foregoing processes.

[0096] In Figure 2L , photoresist 188 is deposited and patterned on hard mask 172 and in a portion of strip holes 186. As Figure 2L shown, the photoresist is further patterned to enable the formation of rib waveguide assembly 124. Then the photoresist 188 is exposed, and the unexposed portions of the photoresist 188 are removed, resulting in Figure 2L the intermediate manufacturing stage of the photon device 100 shown. Thereafter, etching is performed to remove those portions of the first silicon layer 108 to enable the formation of R2S holes 190 and rib contact holes 134, as Figure 2M shown. Suitable etching processes include, for example and without limitation, dry etching processes, RIE processes, wet etching processes, some other etching process, or a combination of the foregoing processes.

[0097] Then photoresist 192 is formed and patterned on the photon device 100, as Figure 2N shown. Thus, the photoresist 192 is deposited into strip holes 186 and R2S holes 190. Then doping is performed on the silicon layer 108 exposed in the rib contact holes 134. As Figure 2O shown, ribbed N+ doped component 166 and ribbed P+ doped component 168 are formed in the rib contact holes 134 within the first silicon layer 108. As will be appreciated, the doping for forming the doped components 166 and 168 can be accomplished, for example, by ion implantation. As discussed above, an ion implanter is used to implant atoms into the silicon lattice, thereby changing the conductivity of the lattice at the implantation location. An ion implanter typically includes an ion source, a beam line, and a processing chamber. The ion source generates the desired ions (e.g., Co, Ti, Ni, Pt, or Pb, depending on the desired N-type or P-type electrode). The beam line organizes the ions into a beam with high purity in terms of ion mass, energy, and species. Then the ion beam is used to irradiate the wafer substrate in the processing chamber. The ion beam strikes the exposed area on the wafer substrate, and the ions can be implanted into the substrate as dopants at the desired depth. Alternatively, the substrate can be partially etched, then a blanket deposition of metal is performed, and then annealing is carried out, where the metal reacts with the underlying exposed silicon. Then the unreacted metal can be removed, for example, by a selective etching process.

[0098] As Figure 2P shown, then photoresist 194 is deposited into strip holes 186 and R2S holes 190, thereby exposing the rib contact holes 134. Thereafter, a contact etch stop layer (CESL) 132 is deposited in the rib contact holes 134, and asFigure 2Q As shown, it is located above the corresponding doping components 166-168. According to some embodiments, a contact etch stop layer (CESL) 132 suitably includes a material layer having etching characteristics that are significantly different from the material to be etched, thereby stopping or aborting the etching process of the layer deposited on the etch stop layer. Thus, the contact etch stop layer (CESL) 132 may include, for example and without limitation, tantalum oxide (TaO), tantalum (Ta), titanium (Ti), silicon nitride (SiN), etc.

[0099] The silicate glass material 128 is then deposited on the photon device 100, as Figure 2R shown. As indicated above, the silicate glass material 128 is suitably formed in the strip holes 186, R2S holes 190, and rib contact holes 134. Thereafter, CMP and polyimide etching (i.e., removing the hard mask 172) are performed, as Figure 2S depicted. Then an undoped silicate glass component 130 is deposited, as Figure 2T shown. According to some embodiments, the undoped silicate glass (USG) component 130 can be implemented to have a thickness in the range of 5000 angstroms to 10,000 angstroms. In one embodiment, the undoped silicate glass (USG) component 130 has an implantation thickness of 8 angstroms. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0100] In Figure 2U , a photoresist 196 is deposited and patterned on the undoped silicate glass (USG) component 130. As shown, the photoresist 196 is suitably patterned to allow subsequent formation of a rib contact cavity 198 within the rib contact hole 134. Then etching is performed to form the rib contact cavity 198, as Figure 2U shown. According to some embodiments, CMP may also be performed to planarize the undoped silicate glass (USG) component 130. Thereafter, as will be understood, subsequent formation of the photon device 100 may be performed, for example, forming a reflective device trench structure 116 and a reflective device 114, forming rib contacts 138, interlayer dielectric fabrication, metal components 140, bump pads 142, etc. Additionally, formation of the reflective device trench structure 116 may be performed according to some embodiments. It should be understood that although shown and described as in waveguide formation (i.e., Figures 2A to 2U) is performed afterwards, but the reflective device trench structure 116 can be formed before other photon device components, and the descriptions provided in some embodiments of the present disclosure are only intended as an exemplary formation strategy.

[0101] Now turning to Figures 3A to 3D , a close-up cross-sectional view of a manufacturing stage of a portion of the photon device 100 according to some embodiments is shown, where the reflective device 114 and the reflective device trench structure 116 are located in the portion. As Figure 3A shown, a photoresist 200 is deposited and patterned on the photon device 100 to protect portions of the photon device 100 from subsequent processing. That is, the portions located adjacent to the echelle grating waveguide assembly 118 remain exposed after the patterning of the photoresist 200. In Figure 3B , an initial etching operation is performed to remove portions of the undoped silicate glass component 130, the second top-side oxide layer 154, the third top-side oxide layer 158, the fourth top-side oxide layer 162, and the first silicon layer 108, thereby exposing the first top-side oxide layer 106.

[0102] Then an oxide 202 is deposited and CMP can be performed on the photon device 100, as Figure 3C shown. According to one embodiment, the oxide 202 can include, for example and without limitation, a non-low-k dielectric material such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), etc. In some embodiments, the oxide 202 can include the same material as the first top-side oxide layer 106. Then an etching is performed, as Figure 3D shown, to leave a portion of the oxide 202 and / or the first top-side oxide layer 106 in place on the substrate 102. Further processing is described below with respect to Figures 4A to 4I .

[0103] Now turning to Figures 4A to 4I , a manufacturing stage of the reflective device 114 and the reflective device trench structure 116 according to some embodiments is shown. It should be understood that Figures 4A to 4I the manufacturing stage shown continues to form the Figure 3D photon device 100 depicted in Figure 4A . In Figure 4A , a close-up cross-sectional view of portions of the substrate 102 and the first top-side oxide layer 106 is shown. In some embodiments, the first top-side oxide layer 106 and the oxide 202 are used as a hard mask to enable the subsequent formation of trenches, as will be understood. Thus, in Figure 4A , a photoresist 204 is deposited and patterned on the first top-side oxide layer 106 / oxide 202. Then a hard mask opening 206 is formed through the first top-side oxide layer 106 / oxide 202, as Figure 4B shown.

[0104] AsFigure 4C As shown, etching is performed into the substrate 102 through the hard mask opening 206 to form the reflective device trench structure 116. Thus, Figure 4C An illustration of the formation of the first inclined surface 135, the bottom surface 136, and the second inclined surface 137 is provided. Suitable etching processes can include, for example and without limitation, etching processes implemented as dry etching processes, RIE processes, wet etching processes, some other etching processes, or combinations of the foregoing processes. In some embodiments, wet etching is used to form the planes 135-137 of the reflective device trench structure 116. As Figure 4C shown, the first inclined surface 135 is inclined with respect to the bottom surface 136. The first inclined surface angle 208, as Figure 4C shown, can be in the range of about 0° to 55°, and in some embodiments, in the range of about 0° to 45°. However, other values and ranges are within the scope of some embodiments of the present disclosure. According to some embodiments, the first inclined surface 135 can have a length 210 in the range of about 1 μm to 20 μm, and in some embodiments, can be greater than or equal to 10 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. In such embodiments, the length 210 of the first inclined surface 135 is greater than the length of the reflective device 114.

[0105] In Figure 4D this step, the remaining first top oxide layer 106 and / or the oxide 202, i.e., the hard mask, is removed via etching or other suitable removal processes. Thus, as Figure 4D shown in this step, the reflective device trench structure 116 can be accessed in the substrate 102. In Figure 4E this step, an oxide layer 212 is deposited for profile transfer. As Figure 4E shown, the oxide layer 212 is deposited on the substrate 102, the first inclined surface 135, the bottom surface 136, and the second inclined surface 137. According to some embodiments, the oxide layer 212 is deposited to form a layer on the planes 135-137, as shown. It should be understood that, according to some embodiments, the thickness of the oxide layer 212 is used to reflect the position of the reflective device 114. In some embodiments, the oxide layer 212 is deposited to have a thickness 214 in the range of about 1 μm to 10 μm, and in some embodiments, the thickness 214 of the oxide layer 212 is greater than or equal to 7 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0106] In Figure 4FIn [the figure], a reflective layer 216 is deposited on the oxide layer 212. The reflective layer 216 can be deposited via any suitable method, including, for example and without limitation, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. The reflective layer 216 can include, for example and without limitation, Al, AlCu, AlSiCu, AlSi, AlCr, or other suitable reflective metals, metal alloys, etc. The reflective layer 216 can be formed to have a thickness 220 in the range of about 1 μm to 7 μm, and in some embodiments, in the range of about 3 μm to 5 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. According to other embodiments, the reflective layer 216 can include multiple different reflective material layers or coatings. Thus, in such embodiments, a metal layer can be deposited, and then one or more high-reflectivity coatings, such as, for example and without limitation, SiO2 / TiO2, AlAs / GaAs, AlN / GaN, etc., can be deposited. According to some embodiments, the number of high-reflectivity material layers is greater than or equal to three high-reflectivity material layers, and can be greater than four high-reflectivity material layers.

[0107] Figure 4G Shows a subsequent stage of manufacturing the photonic device 100 according to some embodiments. As Figure 4G shown, a photoresist 218 is deposited and patterned on the reflective layer 216. That is, a photoresist layer 218 is formed on the reflective layer 216, and is subjected to selective exposure to visible light, ultraviolet light, deep ultraviolet light (i.e., DUV lithography), extreme ultraviolet light (i.e., EUV lithography), etc. via a photomask, and then the exposed photoresist is developed. Thereafter, the unexposed portions of the photoresist material are removed, thereby obtaining Figure 4G the photoresist 218 on a portion of the reflective layer 216 as shown in [the figure], and this portion will be used as the reflective device 114.

[0108] As Figure 4H shown, etching is performed to remove the portions of the reflective layer 216 that are not protected by the photoresist 218, and then the photoresist is removed. Figure 4H Thus, the reflective device 114 located adjacent to the oxide layer 212 on the first inclined surface 135 is shown. As Figure 4H shown, the reflective device 114 is located at the thickness 214 of the oxide layer 212, at a reflective device angle 224 with respect to the first inclined surface 135. The reflective device angle 224, as Figure 4HAs shown, it can be in the range of about 0° to 55°, and in some embodiments, in the range of about 0° to 45°. However, other values and ranges are within the scope of some embodiments of the present disclosure. According to some embodiments, the reflective device 114 can be implemented to have a length 222 corresponding to the length of the first inclined surface 135. Thus, in such embodiments, the length 222 of the reflective device 114 can be implemented to have a length 222 in the range of about 1 μm to 20 μm, and in some embodiments, can be greater than or equal to 10 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. According to some embodiments, the length 210 of the first inclined surface 135 is greater than the length of the reflective device 114. Thereafter, additional oxide material is deposited on the oxide layer 212 and the reflective device 114 to fill the reflective device trench structure 116, as Figure 4I shown therein.

[0109] Now turning to Figures 5A to 5C , different implementations of the reflective device 114 in the photon device 100 according to some embodiments are illustrated. As Figure 5A shown in the embodiment of Figures 4A to 4I , the reflective device 114 is shown in the form of a single-layer solid material (such as a metal), as previously described with respect to Figure 5B An embodiment is provided in which the reflective device 226 is formed of a plurality of high-reflection coatings. Figure 5C An embodiment is provided in which a plurality of reflective devices 114 are located in the respective reflective device trench structures 116 of the photon device 100. This may be useful for reflecting light over a larger area, or reflecting light from multiple light sources or light having different wavelengths. It should be understood that although shown as having two reflective devices 114, the photon device 100 can be implemented to have any suitable number of reflective devices 114, including for example and without limitation 1, 2, 3, 4, 5, etc., in combination with a corresponding number of associated reflective device trench structures 116.

[0110] Now referring to Figure 6 , a flowchart 600 of a method for manufacturing a photon device structure according to an exemplary embodiment is illustrated. As Figure 6 shown, the method starts at step 602, where a first top-side oxide layer 106 is formed on the substrate 102, as Figure 2B shown. In some embodiments, the substrate 102 can be a silicon-on-insulator (SOI) substrate. Then a silicon layer 108 is formed on the first top-side oxide layer 106 in step 604. Figure 2C An illustrative example of the deposition of the silicon layer 108 is provided. In step 606, a hard mask 172 is formed on the silicon layer 108, as Figure 2D shown therein.

[0111] Then, in step 608, the distributed Bragg reflector 110 is patterned in the hard mask 172 and the silicon layer 108. Figure 2E and Figure 2F , as discussed above, provides an illustrative example of the process performed in step 608. In step 610, the strip-shaped, R2S, and rib-shaped hard mask openings (or holes) 182 are patterned, as Figures 2G to 2I shown. Thereafter, in step 612, etching is performed to remove portions of the silicon layer 108 to form strip-shaped holes 186 and R2S holes 190. Figures 2J to 2K Provides an illustration of the formation of the strip-shaped holes 186 and R2S holes 190 according to some embodiments.

[0112] In step 614, rib-shaped contact holes 134 corresponding to the rib waveguide assembly 124 are formed in the silicon layer 108. As Figures 2L to 2M shown, a photoresist 188 may be deposited and patterned on the silicon layer 108, and then etching is performed to remove portions of the silicon layer 108, thereby defining the rib-shaped contact holes 134. In step 616, the silicon layer 108 of the first contact hole 134 is doped, as Figures 2N to 2O shown. As discussed above, an N+ doped component 166 and a P+ doped component 168 are formed in the first contact hole 134 of the rib waveguide assembly 124.

[0113] Thereafter, in step 620, a contact etch stop layer (CESL) 132 is formed in the contact hole 134 above the doped components 166 and 168. The formation of the contact etch stop layer (CESL) 132 may include patterning (coating, developing, etc.) of the photoresist 194, as Figure 2P shown. As Figure 2Q shown, the formation of the contact etch stop layer (CESL) 132 may result in the deposition of the contact etch stop layer (CESL) 132 material on the doped components 166 and 168.

[0114] In step 622, a silicate glass material 128 is deposited, and the silicate glass material 128 fills the contact hole 134, as Figure 2R shown. Thereafter, in step 624, CMP and polyimide etching (i.e., removing the hard mask 172) are performed, as Figure 2S depicted. In step 626, an undoped silicate glass component 130 is deposited on the silicon layer 108, as Figure 2T shown. In step 628, a contact cavity 198 is formed in the contact hole 134, as Figures 2U to 2Vas shown. As Figure 2V shown, the contact cavity 198 extends through the undoped silicate glass component 130, the silicate glass material 128, and the contact etch stop layer 132, thereby allowing subsequent formation of the contact 138, as Figure 1 shown therein.

[0115] Then the operation continues to Figure 7 , and thus the reflective device 114 and the reflective device trench structure 116 are formed on the photon device 100 according to an exemplary embodiment. Figure 7 The method of the flowchart 700 starts at step 702, and thus a photoresist 200 is deposited and patterned on the photon device 100 to protect portions of the photon device 100 from subsequent processing. That is, as Figure 3A shown, the portions located adjacent to the echelle grating waveguide component 118 remain exposed after patterning of the photoresist 200. In step 704, an etch is performed to remove the unprotected portions of the photon device 100, as Figure 3B shown therein. According to some embodiments, portions of the undoped silicate glass component 130, the second top-side oxide layer 154, the third top-side oxide layer 158, the fourth top-side oxide layer 162, and the first silicon layer 108 are removed, thereby exposing the first top-side oxide layer 106. Alternatively, the etch performed in step 704 may result in exposing the substrate 102, that is, removing all layers above the portion of the substrate 102 that is not covered by the aforementioned photoresist 200.

[0116] In step 706, an oxide hard mask (oxide 202) is formed on the photon device 100 by deposition and CMP, as Figure 3C shown. According to some embodiments, adding the material of the oxide 202 on the first top-side oxide layer 106 may help form the hard mask, that is, thickening the oxide to allow subsequent etching processes on the substrate 102, as discussed below. In step 708, a photoresist 204 is deposited and patterned on the hard mask (i.e., the combination of the oxide 106 and the oxide 202) to allow subsequent opening of the aforementioned hard mask. Figure 4A Provide an illustrative example of the process performed in step 708.

[0117] Then the operation continues to step 710, and thus the hard mask opening 206 is formed, thereby exposing the substrate 102, as shown in Figure 4B figure. In step 712, the reflective device trench structure 116 is formed in the substrate 102, as Figure 4CAs shown. According to some embodiments, etching, such as wet etching, is performed through the hard mask opening 206 to form the first inclined surface 135, the bottom surface 136, and the second inclined surface 137 of the reflective device trench structure 116 in the substrate 102. Although the use of a wet etching process is mentioned above, those skilled in the art will understand that other suitable methods can be used to form the reflective device trench structure 116, including, for example and without limitation, dry etching processes, RIE processes, some other etching processes, or combinations of the foregoing processes. As discussed above and Figure 4C As shown, the first inclined surface 135 is inclined with respect to the bottom surface 136 at a first inclined surface angle 208, and the first inclined surface angle 208 is in the range of about 0° to 55°, and in some embodiments, in the range of about 0° to 45°. However, other values and ranges are within the scope of some embodiments of the present disclosure. Additionally, according to some embodiments, the first inclined surface 135 may have a length 210 in the range of about 1 μm to 20 μm, and in some embodiments, may be greater than or equal to 10 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0118] In step 714, the remaining hard mask material is removed via etching or other suitable removal processes, as Figure 4C shown. In step 716, an oxide layer 212 is deposited to perform profile transfer in the reflective device trench structure 116, as Figure 4E shown. According to some embodiments, the oxide layer 212 is deposited on the substrate 102, the first inclined surface 135, the bottom surface 136, and the second inclined surface 137, having a thickness 214 in the range of about 1 μm to 10 μm, and in some embodiments, the thickness 214 of the oxide layer 212 is greater than or equal to 7 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0119] In step 718, a reflective layer 216 is deposited on the oxide layer 212, as Figure 4FAs shown. As discussed above, the reflective layer 216 can be deposited via any suitable means, including for example and not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, another deposition process, or any suitable combination thereof. In some embodiments, the reflective layer 216 can include, for example and not limited to, Al, AlCu, AlSiCu, AlSi, AlCr, or other suitable reflective metals, metal alloys, etc. According to other embodiments, the reflective layer 216 can include multiple different reflective material layers or coatings. That is, the reflective layer 216 can be formed by depositing one or more high-reflectivity coatings (such as, for example and not limited to, SiO2 / TiO2, AlAs / GaAs, AlN / GaN, etc.) on a base layer. According to some embodiments, the number of high-reflectivity material layers is greater than or equal to three high-reflectivity material layers, and can be greater than four high-reflectivity material layers. According to one embodiment, the reflective layer 216 can be formed to have a thickness 220 in the range of about 1 μm to 7 μm, and in some embodiments, in the range of about 3 μm to 5 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure.

[0120] In step 720, a photoresist 218 is deposited and patterned on the reflective layer 216, as Figure 4G shown. In step 722, the reflective layer 216 is etched to remove those portions not covered by the photoresist. Figure 4H An illustrative example of the reflective device trench structure 116 and the reflective device 114 at this manufacturing stage is provided. According to one embodiment, the reflective device 114 corresponds to, for example and not limited to, a metal film, a quarter-wavelength stack (high-reflectivity coating / Bragg mirror, etc.). That is, the reflective device 114 is located at the thickness 214 of the oxide layer 212, at a reflective device angle 224 with respect to the first inclined surface 135. The reflective device angle 224, as Figure 4H shown, can be in the range of about 0° to 55°, and in some embodiments, in the range of about 0° to 45°. However, other values and ranges are within the scope of some embodiments of the present disclosure. According to some embodiments, the reflective device 114 includes a length 222 corresponding to the length of the first inclined surface 135. Thus, the length 222 of the reflective device 114 can be in the range of about 1 μm to 20 μm, and in some embodiments, can be greater than or equal to 10 μm. However, other values and ranges are within the scope of some embodiments of the present disclosure. In step 724, additional oxide material is deposited on the oxide layer 212 and the reflective device 114 to fill the reflective device trench structure 116, as Figure 4I shown.

[0121] According to some embodiments disclosed herein, a photon device and a manufacturing method are provided, which provide process integration in a CMOS process flow. In addition, the disclosed method and device provide die-level and wafer-level improvements and benefits in testing. Therefore, an additional metal film or quarter-wavelength stack on the first inclined surface 135 of the reflective device trench structure 116, i.e., the reflective device 114, serves as a mirror to reflect laser light for operating the photon device 100. In some embodiments, the structures described in some embodiments of the present disclosure provide additional benefits in terms of manufacturing steps, enabling the use of an external light source (instead of a mounted laser) and enabling rapid compliance testing.

[0122] According to a first embodiment, a photon device structure is provided, including a substrate having a top-side oxide layer thereon. The photon device structure further includes a silicon layer located on the top-side oxide layer, and one or more waveguide components located in the silicon layer. Additionally, the photon device structure includes a reflective device trench structure located in the silicon layer, and the reflective device trench structure includes a first inclined surface, a bottom surface, and a second inclined surface. The photon device structure further includes a reflective device adjacent to the first inclined surface, and the reflective device has a reflective device angle relative to the bottom surface and is configured to direct light into the waveguide components. In some embodiments, the reflective device trench structure further includes an oxide layer thereon, and the reflective device is located on the oxide layer. In some embodiments, the oxide layer has a thickness in the range of 1 micrometer to 10 micrometers. In some embodiments, the reflective device further includes a plurality of high-reflection coatings. In some embodiments, the reflective device includes a reflective device length in the range of 1 micrometer to 20 micrometers. In some embodiments, the reflective device is positioned at an angle between 0 degrees and 55 degrees. In some embodiments, the first inclined surface has an angle relative to the substrate in the range of 0 degrees and 55 degrees. In some embodiments, the first inclined surface has a length in the range of 1 micrometer to 20 micrometers. In some embodiments, the reflective device has a thickness in the range of 1 micrometer to 7 micrometers.

[0123] According to a second embodiment, a photonic semiconductor device is provided, including a substrate and a first top-side oxide layer located on the substrate. The photonic semiconductor device further includes a silicon layer located on the first top-side oxide layer, and the silicon layer includes a strip waveguide component, a rib-to-strip waveguide component, and one or more rib waveguide components. The photonic semiconductor device further includes a reflective device trench structure located in the silicon layer, and the reflective device has a first inclined surface, a bottom surface, and a second inclined surface. Additionally, the photonic semiconductor device includes a reflective device adjacent to the first inclined surface. The reflective device includes a reflective device angle relative to the bottom surface and is configured to direct light to the strip waveguide component, the rib-to-strip waveguide component, or the rib waveguide component. In some embodiments, the reflective device trench structure further includes an oxide layer located thereon, and the reflective device is located on the oxide layer. In some embodiments, the reflective device further includes a plurality of high-reflection coatings. In some embodiments, the reflective device includes at least one of a metal or a quarter-wavelength stack. In some embodiments, the quarter-wavelength stack includes at least one high-reflection coating or a Bragg mirror. In some embodiments, the first inclined surface has an angle relative to the substrate, the angle being between 0 degrees and 55 degrees. In some embodiments, the reflective device further includes a reflective device length in the range of 1 micron to 20 microns, a reflective device angle between 0 degrees and 55 degrees, and a reflective device thickness in the range of 1 micron to 7 microns. In some embodiments, the first inclined surface has an angle relative to the substrate, the angle being between 0 degrees and 55 degrees, and the first inclined surface has a length in the range of 1 micron to 20 microns.

[0124] According to a third embodiment, a method of manufacturing a photonic semiconductor device is provided. The method includes forming a silicon layer on a first top-side oxide layer of a substrate, and forming one or more waveguide components in the silicon layer. The method further includes etching to remove a portion of the silicon layer and the first top-side oxide layer adjacent to at least one waveguide component to expose the substrate. Then a hard mask is formed on the exposed substrate. Then a reflective device trench structure is formed through the hard mask in the substrate. The reflective device trench structure includes a first inclined surface, a bottom surface, and a second inclined surface. Then an oxide layer is deposited in the reflective device trench structure such that the oxide layer is formed on the first inclined surface, the bottom surface, and the second inclined surface. Thereafter, a reflective device is formed on the oxide layer of the first inclined surface. In some embodiments, forming the reflective device further includes depositing a reflective layer on the oxide layer, patterning a photoresist on the reflective layer to define the reflective device, and etching the reflective layer to form the reflective device. In some embodiments, depositing the reflective layer further includes depositing a plurality of high-reflection coatings.

[0125] According to some embodiments, a photon device structure is provided. The photon device structure includes a substrate having a top-side oxide layer thereon. The photon device structure further includes a silicon layer located on the top-side oxide layer, and at least one waveguide component located in the silicon layer. The photon device structure further includes a reflective device trench structure located in the silicon layer, the reflective device trench structure having a first inclined surface, a bottom surface, and a second inclined surface. The photon device structure further includes a reflective device adjacent to the first inclined surface, the reflective device having a reflective device angle relative to the bottom surface and configured to direct light into the waveguide component, wherein the reflective device further includes a plurality of high-reflection coatings.

[0126] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of some embodiments of the present disclosure. Those skilled in the art should understand that they may readily use some embodiments of the present disclosure as a basis to design or modify other processes and structures in order to achieve the same purposes and / or achieve the same advantages of the embodiments introduced in the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations in some embodiments of the present disclosure without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A photon device structure, characterized in that, Comprising: A substrate, comprising a top-side oxide layer thereon; A silicon layer, located on the top-side oxide layer; At least one waveguide component, located in the silicon layer; A reflective device trench structure, located in the silicon layer, the reflective device trench structure having a first inclined surface, a bottom surface and a second inclined surface; and A reflective device, adjacent to the first inclined surface, the reflective device having a reflective device angle relative to the bottom surface and configured to guide light into the at least one waveguide component.

2. The photon device structure according to claim 1, wherein, Wherein the reflective device trench structure further comprises an oxide layer thereon, and wherein the reflective device is located on the oxide layer.

3. The photon device structure according to claim 2, wherein, Wherein the oxide layer has a thickness in the range of 1 micron to 10 microns.

4. The photon device structure according to claim 1, wherein Wherein the reflective device comprises a reflective device length in the range of 1 micron to 20 microns.

5. The photon device structure according to claim 1, wherein, Wherein the first inclined surface has an angle relative to the substrate, the angle being between 0 degrees and 55 degrees.

6. The photon device structure according to claim 1, characterized in that, Wherein the reflective device has a thickness in the range of 1 micron to 7 microns.

7. A photon semiconductor device, characterized in that, Comprising: A substrate; A first top-side oxide layer, located on the substrate; A silicon layer, located on the first top-side oxide layer, the silicon layer comprising: A strip waveguide component; A rib-to-strip waveguide component; and At least one rib waveguide component; A reflective device trench structure, located in the silicon layer, the reflective device trench structure having a first inclined surface, a bottom surface and a second inclined surface; and A reflective device, adjacent to the first inclined surface, the reflective device having a reflective device angle relative to the bottom surface and configured to guide light into at least one of the strip waveguide component, the rib-to-strip waveguide component and the at least one rib waveguide component.

8. The photon semiconductor device according to claim 7, characterized in that, Wherein the reflective device further comprises: A reflective device length in the range of 1 micron to 20 microns; A reflective device angle between 0 degrees and 55 degrees; and A reflective device thickness in the range of 1 micron to 7 microns.

9. The photon semiconductor device according to claim 8, characterized in that, Wherein the first inclined surface has an angle relative to the substrate, the angle being between 0 degrees and 55 degrees, and wherein the first inclined surface has a length in the range of 1 micron to 20 microns.

10. A photon device structure, characterized in that, Comprising: A substrate, comprising a top-side oxide layer thereon; A silicon layer, located on the top-side oxide layer; At least one waveguide component, located in the silicon layer; A reflective device trench structure, located in the silicon layer, the reflective device trench structure having a first inclined surface, a bottom surface and a second inclined surface; and A reflective device, arranged adjacent to the first inclined surface, the reflective device having a reflective device angle relative to the bottom surface and configured to guide light into the at least one waveguide component, wherein the reflective device further comprises a plurality of high-reflection coatings.

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