Semiconductor packaging structure

Abstract

Some embodiments of the present application provide a semiconductor package structure comprising: a first die; a second die on the first die; a first pillar on the first die; a second pillar on the second die; a molding compound covering the first pillar and the second pillar, and top surfaces of the first pillar and the second pillar being flush with a top surface of the molding compound; the sloped structure is located on the side face of the second tube core, the outer side face of the sloped structure is not parallel to the side face of the second tube core, and the sloped structure has a gradually-shrinking shape in the direction away from the first tube core. The semiconductor packaging structure with good electrical performance is provided by using the slowdown structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package structure. Background Art

[0002] For the package structures in the prior art, 3D packages with multiple columns of different heights for I / O (input / output) formation are required. Refer to Figure 1A , Figure 1A which shows a package structure 10'. In this package structure 10', a second die 12 (i.e., the first electronic component) is stacked on a first die 11 (i.e., the second electronic component), and only columns 13A such as copper columns for the first die 11 are formed for corresponding input / output. After that, the columns 13A are encapsulated in an encapsulation layer 14, and then corresponding connectors 15 etc. are formed on the columns 13A.

[0003] Refer to Figure 1B , for further I / O use, corresponding columns 13B also need to be formed on the second die 12. Specifically, refer to Figure 1B the package structure 10-1 of. Its forming process is as follows: (1) First, an encapsulation layer 14 (such as PI) is formed by coating or laminating, sputtering, etc.; after that (2), columns 13B such as copper columns are formed by plating. It can be seen that this method requires two masks, and the challenges of this method are that the consistency and homogeneity of the encapsulation layer 14 are poor in the topography of this package structure 10-1, where the minimum distance between the bottoms of the columns 13A and 13B is about 20 μm, resulting in poor coplanarity of the final columns 13A and 13B.

[0004] Refer to Figure 1C which shows the corresponding package structure 10-2. Specifically, in the package structure 10-2, (1) First, a part of the encapsulation layer 14 (such as PI) is formed by coating or laminating, sputtering, etc.; (2) A redistribution structure 13A-1 (with a thickness of about 15 μm or 20 μm in the vertical direction) is formed above the first die 11 by plating; (3) Another part of the encapsulation layer 14 is formed by coating or laminating, sputtering, etc.; and (4) Columns 13A-2 and 13B are formed by processes such as plating. Therefore, in this embodiment, 4 masks are required, the process is relatively complex, and the challenges of this method are that the consistency and homogeneity of the encapsulation layer 14 also need to be improved, and the difference between the first die 11 and the second die 12 is also about 20 μm.

[0005] After that, refer to Figure 1D and Figure 1E, which shows the corresponding package structure 10-3. For this package structure 10-3, the forming method is as follows: (1) First, form bottom columns 13A-1 and 13B-1 on the first die 11 and the second die 12 respectively through a growth process, form a package layer 14 through processes such as coating, lamination, sputtering or molding, and then perform grinding so that the columns 13A-1 and 13B-1 are exposed from the package layer 14; (2) Plate top columns 13A-2 and 3B-2 on the bottom columns 13A-1 and 13B-1 respectively. In this process, two masks are required, and the performance of the molded die of this package structure 10-3 may have low-k performance. The challenge of this package structure 10-3 lies in: how to grow the bottom columns 13A-1 and 13B-1, and a package layer 14 is required to smooth the topography of this package structure 10-3.

[0006] Next, refer to Figure 1F , in the existing 3D structure 10, columns 13A and 13B need to be formed on different first die 11 and second die 12. Specifically, refer to Figure 1F-1 , for manufacturing the Figure 1F shown package structure 10, it is usually necessary to fabricate the corresponding columns 13A and 13B on the first die 11 and the second die 12 and then stack them, and finally perform molding and grinding. The manufacturing process is relatively complex. Therefore, there is a need to simultaneously fabricate columns 13A and 13B as shown in Figure 1F-2 . However, as shown in Figure 1F-3 , simultaneously fabricating columns 13A and 13B by plating such as electroplating needs to be fabricated on the same seed layer 16. In a stacked die structure, since the angle between the upper and lower dies 11 and 12 is nearly a right angle and the slope is large, there is a very high risk of fracture P during the fabrication of the seed layer, thus affecting the formation of the corresponding columns 13A and 13B.

[0007] It can be seen that in the prior art, for 3D packages (such as package structures 10', 10, 10-1 to 10-3) having columns (such as columns 13A and 13B) with multiple heights for I / O formation, there are corresponding bump process problems, such as package layer coating, sputtering, and plating uniformity of the corresponding columns. Therefore, it is necessary to provide a 3D package with better performance. Summary of the Utility Model

[0008] This application provides a semiconductor package structure with better electrical performance by using a slope reduction structure. In addition, through the semiconductor package structure provided by this application, the problem that multiple columns cannot be plated simultaneously due to the discontinuity of the seed layer caused by the nearly right angle between the upper and lower dies is further solved.

[0009] Some embodiments of the present application provide a semiconductor package structure, including: a first die; a second die located on the first die; a first pillar located on the first die; a second pillar located on the second die; a molding compound covering the first pillar and the second pillar, and the top surfaces of the first pillar and the second pillar being flush with the top surface of the molding compound; and a slope reduction structure located on a side surface of the second die, wherein an outer side surface of the slope reduction structure is not parallel to the side surface of the second die and has a tapered shape in a direction away from the first die.

[0010] In some embodiments, an angle between the outer side surface of the slope reduction structure and the top surface of the first die is an obtuse angle.

[0011] In some embodiments, the slope reduction structure extends from a bottom of the second die to a top of the second die.

[0012] In some embodiments, the semiconductor package structure further includes: a first seed layer disposed between the first pillar and the first die; and a second seed layer disposed between the second pillar and the second die.

[0013] In some embodiments, the semiconductor package structure further includes: a first dielectric layer located between the first die and the second die and between the first die and the first seed layer and having a groove, wherein the second die is disposed in the groove.

[0014] In some embodiments, the slope reduction structure extends into the groove.

[0015] In some embodiments, the slope reduction structure is spaced apart from the first pillar.

[0016] In some embodiments, a bottom of the first pillar is lower than a bottom of the second pillar.

[0017] In some embodiments, the first pillar is disposed around the second die.

[0018] In some embodiments, a side surface of the molding compound is aligned with a side surface of the first die.

[0019] In some embodiments, the molding compound further covers a side surface of the first dielectric layer.

[0020] In some embodiments, the semiconductor package structure further includes: metal bumps embedded in the first dielectric layer, wherein the second die is attached to the first die through the metal bumps.

[0021] In some embodiments, the second die is disposed within a lateral range of the first die.

[0022] In some embodiments, the semiconductor package structure further includes: a second dielectric layer located on the second die and between the second die and the second seed layer.

[0023] In some embodiments, the slope reduction structure further extends along the side surface of the second dielectric layer.

[0024] In some embodiments, the semiconductor package structure further includes: solder bumps disposed on the first pillars, the second pillars, and the molding compound.

[0025] In some embodiments, the first die is an application specific integrated circuit die and the second die is a memory die.

[0026] Some other embodiments of the present application provide a semiconductor package structure including: a first die, a first pillar disposed on the first die; a second die disposed on the first die and between the first pillars; a second pillar disposed on the second die; a slope reduction structure located on the side surface of the second die, wherein an angle between an outer side surface of the slope reduction structure and a top surface of the first die is an obtuse angle.

[0027] In some embodiments, the semiconductor package structure further includes: a molding compound covering the first pillars and the second pillars, and top surfaces of the first pillars and the second pillars are flush with a top surface of the molding compound.

[0028] In some embodiments, the slope reduction structure has a tapered shape in a direction away from the first die.

[0029] The present application provides a semiconductor package structure with better electrical performance by using a slope reduction structure, and due to the slope reduction structure, voids in the semiconductor package structure are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0031] Figures 1A to 1F And Figures 1F-1 to 1F-3 shows a package structure in the prior art.

[0032] Figure 2 And Figures 3 to 10 shows the semiconductor package structure provided by the present application and its corresponding formation process. DETAILED DESCRIPTION

[0033] The following disclosure provides many different embodiments or examples for implementing different features of the present utility model. Specific examples of components and arrangements are described below to simplify the present utility model. Of course, these are merely examples and are not intended to limit the present utility model. In addition, when a numerical value or a numerical range is described by terms such as "substantially", "about", "substantially", "essentially", etc., unless otherwise specified, the term is intended to cover numerical values within ±10% of the described numerical value. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0034] This application provides a semiconductor package structure with better electrical performance by using a slope reduction structure. Furthermore, with the semiconductor package structure provided by this application, the problem of being unable to simultaneously plate multiple pillars due to discontinuity of the seed layer caused by an almost right angle between the upper and lower die chips is further solved. In a further embodiment, due to the addition of the microstructure of the slope reduction structure between the upper and lower die chips and being retained in the final product, it is beneficial to the continuous sputtering of the corresponding seed layer, and the processes such as electroplating of the corresponding pillars of the upper and lower die chips can be completed simultaneously through the continuous seed layer.

[0035] In addition, the microstructure can reduce the generation of voids at the corresponding slopes (such as at the corners) during thickness molding, thereby reducing the voids in the corresponding semiconductor package structure.

[0036] Specifically, referring to Figure 2 , some embodiments of this application provide a semiconductor package structure 100, including: a first die chip 101; a second die chip 102 located on the first die chip 101; a first pillar 103A located on the first die chip 101; a second pillar 103B located on the second die chip 102. In some embodiments, the second die chip 102 is disposed within the lateral range of the first die chip 101, that is, in the cross-sectional view shown in Figure 2 , the width of the second die chip 102 is less than the width of the first die chip 101. In some specific embodiments, the first die chip 101 is an application specific integrated circuit (ASIC) die chip, and the second die chip 102 is a memory die chip. In some embodiments, the first pillar 103A and the second pillar 103B are conductive pillars, and in some embodiments, they may include, but are not limited to, metals or metal alloys such as copper, gold, silver, etc.

[0037] In some embodiments, the semiconductor package structure 100 further includes a molding compound 104 that encapsulates the first pillar 103A and the second pillar 103B, and the top surface 103At of the first pillar 103A and the top surface 103Bt of the second pillar 103B are flush with the top surface 104t of the molding compound 104, but the bottom 103Ad of the first pillar 103A is lower than the bottom 103Bd of the second pillar 103B. Further, the semiconductor package structure 100 further includes a slope reduction structure 106 located on the side surface 102s of the second die 102. Specifically, the outer side surface 106s of the slope reduction structure 106 is not parallel to the side surface 102s of the second die 102 and has a tapered shape in the direction D away from the first die 101, that is, in the plan view as shown in Figure 2 , the width of the slope reduction structure 106 gradually decreases in the direction D. In some embodiments, the molding compound 104 includes molding compound, underfill, etc. In some embodiments, the slope reduction structure 106 may include a conductive material and a non-conductive material. The conductive material includes metals or metal alloys such as copper, gold, silver, etc., and the non-conductive material includes epoxy resin glue, other suitable non-conductive materials, etc.

[0038] In addition, as can be seen from Figure 2 , the angle α between the outer side surface 106s of the slope reduction structure 106 and the top surface 101t of the first die 101 is an obtuse angle, and the slope reduction structure 106 extends from the bottom 102d of the second die 102 to the top 102t of the second die 102. As shown in Figure 2 , the slope reduction structure 106 is spaced apart from the first pillar 103A. In addition, the first pillar 103A is disposed around the second die 102.

[0039] Further, as can be seen from Figure 2 , the semiconductor package structure 100 further includes a first seed layer 103As located between the first pillar 103A and the first die 101, and a second seed layer 103Bs disposed between the second pillar 103B and the second die 102. Further, the semiconductor package structure 100 further includes a first dielectric layer 107 that is located between the first die 101 and the second die 102 and between the first die 101 and the first seed layer 103As, and the first dielectric layer 107 has a groove R, and the second die 102 is disposed in the groove R. In a further embodiment, the slope reduction structure 106 extends into the groove R, that is, the slope reduction structure 106 further extends into the first dielectric layer 107. In some embodiments, the first seed layer 103As and the second seed layer 103Bs may include, but are not limited to, metals or metal alloys such as copper, gold, silver, etc.

[0040] Continuing to refer toFigure 2 , in the semiconductor package structure 100, the side surface 104s of the molding compound 104 is aligned with the side surface 101s of the first die 101. In some other embodiments, the molding compound 104 further covers the side surface 107s of the first dielectric layer 107. However, in some other embodiments, the side surface 104s of the molding compound 104 is aligned with the side surface 107s of the first dielectric layer 107.

[0041] Furthermore, the semiconductor package structure 100 further includes: metal bumps 109, embedded in the first dielectric layer 107, Figure 2 In the semiconductor package structure 100 shown, the second die 102 is attached to the first die 101 through the metal bumps 109. In the present application, the semiconductor package structure 100 further includes: a second dielectric layer 108, located on top of the top surface 102t of the second die 102 and between the second die 102 and the second seed layer 103Bs. In addition, the slope reduction structure 106 further extends along the side surface 108s of the second dielectric layer 108. In the above embodiments, the first dielectric layer 107 and the second dielectric layer 108 include, but are not limited to, polyimide (PI), imide, or other suitable dielectric materials.

[0042] In some other embodiments of the present application, the semiconductor package structure 100 further includes solder bumps 105, disposed on top of the first pillar 103A, the second pillar 103B, and the molding compound 104, specifically, disposed on the top surface 103At of the first pillar 103A, the top surface 103Bt of the second pillar 103B, and the top surface 104t of the molding compound 104. In some other embodiments of the present application, the semiconductor package structure 100 further includes pads 101P disposed below the bottom 103Ad of the first pillar 103A and pads 102P disposed below the bottom 103Bd of the second pillar 103B. The first pillar 103A and the second pillar 103B are respectively connected to the corresponding first die 101 and second die 102 through the pads 101P and 102P. In the above embodiments, the metal bumps 109, the pads 101P and 102P include, but are not limited to, metals or metal alloys such as copper, gold, silver, etc., and the solder bumps 105 include, but are not limited to, solder, etc.

[0043] In the above-mentioned semiconductor packaging structure 100 provided by the present application, adding a slope reduction structure 106 between the first die 101 and the second die 102 is beneficial to the sputtering of the first seed layer 103As and the second seed layer 103Bs, enabling the simultaneous fabrication of the first pillar 103A and the second pillar 103B. This is because by forming the slope reduction structure 106, and the angle α between the outer side surface 106s of the slope reduction structure 106 and the top surface 101t of the first die 101 is an obtuse angle, the first seed layer 103As and the second seed layer 103Bs can be formed into a continuous seed layer without the risk of breakage, thereby enabling the simultaneous electroplating of the first pillar 103A and the second pillar 103B using the continuous seed layer. In addition, the slope reduction structure 106 can reduce the voids in the molding compound 104. When the angle α is a right angle, there is a greater possibility that the molding compound 104 does not flow easily at the corresponding right angle, resulting in voids. However, with the structure provided by the present application, by using the slope reduction structure 106 to make the corresponding angle α an obtuse angle, the molding compound 104 can flow more easily and fill up, thereby reducing the voids in the molding compound 106.

[0044] Referring to Figure 2 , some other embodiments of the present application also provide a semiconductor packaging structure 100, including: a first die 101; a first pillar 103A disposed on the first die 101; a second die 102 disposed on the first die 101 and between the first pillars 103A; a second pillar 103B disposed on the second die 102; a slope reduction structure 106 located on the side surface 102s of the second die 102, wherein the angle α between the outer side surface 106s of the slope reduction structure 106 and the top surface 101t of the first die 101 is an obtuse angle. In some embodiments, the semiconductor packaging structure 100 further includes: a molding compound 104 covering the first pillar 103A and the second pillar 103B, and the top surface 103At of the first pillar 103A and the top surface 103Bt of the second pillar 103B are flush with the top surface 104t of the molding compound 104. In some embodiments, the slope reduction structure 106 has a tapered shape in the direction D away from the first die 101.

[0045] The following takes Figures 3 to 10 to describe Figure 2 the formation process of the semiconductor packaging structure 100 shown.

[0046] Referring to Figure 3 , the second wafer 102 is bonded to the first wafer 101 through a hybrid structure. In some embodiments, the hybrid bonding is metal-to-metal direct bonding. Further, the second wafer 102 is bonded to the first wafer 101 through metal bumps 109. In addition, as Figure 3As shown, the metal bump 109 is disposed in the first dielectric layer 107 such as PI, and there is a groove R in the first dielectric layer 107. The second wafer 102 is disposed in the groove R. In some embodiments, pads 101P are disposed on the top surface 101t of the first wafer 101. Further, the bottom 102d of the second wafer 102 is bonded to the first wafer 101, and a second dielectric layer 108 is disposed on the top 102t of the second wafer 102, and pads 102P on the second wafer 102 are disposed in the second dielectric layer 108.

[0047] Referring to Figure 4 , a slope reduction structure 106 is formed by sputtering and dispensing a non-conductive material such as epoxy resin glue. The outer side surface 106s of the slope reduction structure 106 is non-parallel to the side surface 102s of the second wafer 102, and the included angle α between the slope reduction structure 106 and the top surface 101t of the first wafer 101 is an obtuse angle. As Figure 4 shown, the slope reduction structure 106 further extends along the side surface 108s of the second dielectric layer 108.

[0048] Referring to Figure 5 , a seed layer 1003 such as copper is formed by sputtering above the structure shown in Figure 4 . Since the angle α between the first die 101 and the second die 102 is an obtuse angle, there will be no problem of discontinuity of the sputtered seed layer 1003, and the seed layer 1003 is a continuous seed layer on the entire structure.

[0049] After that, referring to Figure 6 , on Figure 5 the structure shown, a photoresist 1001 is formed. The top surface 1001t of the photoresist 1001 is a non-flat surface. Next, as Figure 7 shown, a plurality of openings 1001 are formed in the photoresist 1001 by photolithography and development. The openings 1001 expose the pads 101P and 102P.

[0050] Referring to Figure 8 , a first column 103A and a second column 103B are grown / formed by a plating process such as electroplating. In Figure 8 the structure shown, the top surface 103Bt' of the second column 103B is higher than the top surface 103At' of the first column 103A. After that, the photoresist 1001 is removed by a process such as stripping. Further, after removing the photoresist 1001, the exposed portion of the seed layer 1003 is removed by an etching process commonly used in the art such as wet etching or dry etching, so as to form a first seed layer 103As under the first column 103A and a second seed layer 103Bs under the second column 103B.

[0051] Next, referring to Figure 9, through processes such as molding or coating, a molding compound is used to form an encapsulation layer 104 that encapsulates the first pillar 103A and the second pillar 103B above the first pillar 103A and the second pillar 103B. In Figure 9 In the structure shown, the top surface 104t of the encapsulation layer 104 is higher than the top surface 103Bt' of the second pillar 103B and the top surface 103At' of the first pillar 103A, and seals the first pillar 103A and the second pillar 103B therein.

[0052] Referring to Figure 10 , through a grinding process, parts of the encapsulation layer 104, the first pillar 103A, and the second pillar 103B are removed, so that the first pillar 103A and the second pillar 103B are exposed through the encapsulation layer 104, and a flat top surface 104t of the encapsulation layer 104, a top surface 103At of the first pillar 103A, and a top surface 103Bt of the second pillar 103B are formed. In Figure 10 In the structure shown, the top surface 104t of the encapsulation layer 104, the top surface 103At of the first pillar 103A, and the top surface 103Bt of the second pillar 103B are flush.

[0053] Finally, through a ball planting process, solder bumps 105 are respectively formed on the top surface 103At of the first pillar 103A and the top surface 103Bt of the second pillar 103B using solder, thereby forming Figure 2 the semiconductor package structure 100 shown.

[0054] In summary, through the slope reduction structure 106 provided by the present application, the formed semiconductor package structure 100 can have better electrical performance. In addition, the bump process problem is solved, that is, the problem that it is impossible to electroplate multiple pillars simultaneously due to the discontinuity of the seed layer caused by the angle between the upper and lower dies being nearly right-angled. Specifically, by forming the microstructured slope reduction structure 106, the sputtering of the seed layer 1003 is made continuous, thereby forming a continuous seed layer 1003, and through the continuous seed layer 1003, the electroplating processes of the first pillar 103A and the second pillar 103B on the first die 101 and the second die 102 can be completed simultaneously, and the uniformity of the corresponding pillars of the formed semiconductor package structure 100 is improved, and a semiconductor package structure 100 with pillars of multiple heights can be formed. In addition, by controlling the selection of the encapsulation layer 104, the warpage of the semiconductor package structure 100 can be controlled. Further, the microstructured slope reduction structure 106 can reduce the occurrence of voids generated when forming the encapsulation layer 104 by thickness molding, thereby reducing the voids in the semiconductor package structure 100.

[0055] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present utility model. Those skilled in the art should understand that they can readily use the present utility model as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments illustrated herein. Those skilled in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the present utility model, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present utility model.

Claims

1. A semiconductor package structure, characterized in that, Comprising: A first die; A second die, located on the first die; A first pillar, located on the first die; A second pillar, located on the second die; A molding compound, encapsulating the first pillar and the second pillar, and the top surfaces of the first pillar and the second pillar being flush with the top surface of the molding compound; And A slope reduction structure, located on the side surface of the second die, wherein, the outer side surface of the slope reduction structure is not parallel to the side surface of the second die and has a tapered shape in a direction away from the first die.

2. The semiconductor package structure according to claim 1, wherein The included angle between the outer side surface of the slope reduction structure and the top surface of the first die is an obtuse angle.

3. The semiconductor package structure according to claim 1, wherein, The slope reduction structure extends from the bottom of the second die to the top of the second die.

4. The semiconductor package structure according to claim 1, wherein Further comprising: A first seed layer, disposed between the first pillar and the first die; And A second seed layer, disposed between the second pillar and the second die.

5. The semiconductor package structure according to claim 4, wherein, Further comprising: A first dielectric layer, located between the first die and the second die and between the first die and the first seed layer and having a groove, wherein, the second die is disposed in the groove.

6. The semiconductor package structure according to claim 5, wherein, The slope reduction structure extends into the groove.

7. The semiconductor package structure according to claim 1, wherein, The bottom of the first pillar is lower than the bottom of the second pillar.

8. The semiconductor package structure according to claim 5, wherein, The molding compound further encapsulates the side surface of the first dielectric layer.

9. The semiconductor package structure according to claim 5, wherein, Further comprising: Metal bumps, embedded in the first dielectric layer, wherein, the second die is attached to the first die through the metal bumps.

10. The semiconductor package structure according to claim 4, wherein, Further comprising: A second dielectric layer, located on the second die and between the second die and the second seed layer.

Images