Semiconductor packaging structure

Abstract

The utility model provides a semiconductor packaging structure. The semiconductor packaging structure comprises a circuit layer which comprises an upper surface, a lower surface and a cavity; the electronic element is arranged in the cavity and comprises an active surface close to the lower surface and a back surface close to the upper surface, the active surface comprises a lower welding pad, and the back surface comprises an upper welding pad; the first dielectric layer is arranged above the circuit layer and covers the electronic element; and the first via hole is arranged in the first dielectric layer and is connected with the upper welding pad. According to the structure provided by the invention, the electronic component is firstly mounted and then thinned, so that the electronic component can be prevented from cracking due to overlarge taking and placing force; the electronic element is coated, protected and reinforced by the first dielectric layer, so that the electronic element can be prevented from being deformed and cracked in the subsequent process, test or application process; a via hole is formed above the electronic component and is used as a vertical electrical channel, thereby being beneficial to shortening an electrical transmission path and improving electrical transmission efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly to a semiconductor packaging structure. Background Art

[0002] For some semiconductor products, such as a fan-out package structure with bonding multi-chips that involves multi-chip docking, chips with double-sided I / O (input / output) are used. These chips usually use through-silicon vias (TSVs) as the up-and-down conduction channels. Considering the impact of the TSV path length on electrical performance, the die is thinned to shorten the TSV path to improve the electrical transmission efficiency. However, after the die is thinned, its strength will decrease. When flip chip bonding (FCB) is performed on a substrate, problems such as cracking of the die may occur due to the operating force when picking or placing the die.

[0003] Reference Figure 1 , shows a packaging structure, including a substrate 101 and a thinned chip 102. The chip 102 has a TSV 103 inside. During the manufacturing process, when the thinned chip 102 is flip chip bonded (i.e., flip-chip soldered) to the substrate 101, the chip 102 may not be able to withstand the operating force of picking or placing and may have problems such as cracking, for example, forming a crack 104 or completely splitting. Summary of the Utility Model

[0004] This application proposes a semiconductor packaging structure and a semiconductor packaging device.

[0005] In a first aspect, this application discloses a semiconductor packaging structure, including:

[0006] A circuit layer, including an upper surface, a lower surface, and a cavity;

[0007] An electronic component, disposed in the cavity, including an active surface close to the lower surface and a back surface close to the upper surface. The active surface includes a lower solder pad, and the back surface includes an upper solder pad;

[0008] A first dielectric layer, disposed above the circuit layer, covering the electronic component;

[0009] A first via hole, disposed in the first dielectric layer, connecting the upper solder pad.

[0010] In some alternative embodiments, the thickness of the electronic component is less than the thickness of the circuit layer.

[0011] In some alternative embodiments, the semiconductor package structure further includes: a second via hole disposed in the first dielectric layer and connecting the circuit layer; the depth of the second via hole is less than the depth of the first via hole.

[0012] In some alternative embodiments, the semiconductor package structure further includes: a second dielectric layer disposed under the circuit layer; a third via hole disposed in the second dielectric layer and connecting the lower solder pad; the aperture of the third via hole is less than the aperture of the first via hole, and the depth of the third via hole is less than the depth of the first via hole.

[0013] In some alternative embodiments, the back surface of the electronic component includes a plurality of concave portions in a curved shape.

[0014] In some alternative embodiments, the depths of the plurality of concave portions are different from each other and the widths are different from each other.

[0015] In some alternative embodiments, the first dielectric layer is filled in the concave portions.

[0016] In some alternative embodiments, the first dielectric layer is filled in the cavity and contacts the side surface of the electronic component.

[0017] In some alternative embodiments, there are pores between the side wall of the cavity and the first dielectric layer.

[0018] In some alternative embodiments, the electronic component has a through-silicon via connecting the active surface and the back surface of the electronic component.

[0019] In some alternative embodiments, the materials of the first dielectric layer and the second dielectric layer are different.

[0020] In some alternative embodiments, the Young's modulus of the first dielectric layer is greater than that of the second dielectric layer, and the thermal expansion coefficient of the first dielectric layer is greater than that of the second dielectric layer.

[0021] In some alternative embodiments, the circuit layer includes a circuit dielectric layer, the Young's modulus of the circuit dielectric layer is between that of the first dielectric layer and the second dielectric layer, and the thermal expansion coefficient of the circuit dielectric layer is between that of the first dielectric layer and the second dielectric layer.

[0022] In some alternative embodiments, the cavity penetrates the circuit layer, and the lower surface of the circuit layer is substantially flush with the active surface of the electronic component.

[0023] In some alternative embodiments, the electronic component is closer to the edge of the circuit layer relative to the center of the circuit layer.

[0024] In some alternative embodiments, there are multiple cavities and multiple electronic components respectively. One electronic component is disposed alone in one cavity.

[0025] In some alternative embodiments, the bottom surface of the semiconductor package structure includes a plurality of bottom connection pads, and / or the top surface of the semiconductor package structure includes a plurality of top connection pads.

[0026] In a second aspect, the present application discloses a semiconductor packaging device, including a plurality of stacked packages, and at least one of the plurality of packages is the semiconductor package structure as described in the first aspect.

[0027] In some alternative embodiments, the plurality of packages include an adjacent first package and a second package, and both the first package and the second package are the semiconductor package structures as described in the first aspect; wherein, the bottom connection pads of the first package are opposite to and electrically connected to each other with the bottom connection pads of the second package, or the bottom connection pads of the first package are opposite to and electrically connected to each other with the top connection pads of the second package, or the top connection pads of the first package are opposite to and electrically connected to each other with the top connection pads of the second package; the electrical connection is direct bonding or bonding through microbumps.

[0028] In some alternative embodiments, the semiconductor packaging device includes opposite top and bottom surfaces, a system component is disposed on the top surface, and solder balls are disposed on the bottom surface.

[0029] As described above, in order to solve the problem that the chip is prone to cracking due to stress during the FCB operation after thinning, the present application proposes a semiconductor package structure, which is formed by first mounting an electronic component (such as a chip) and then thinning the electronic component. The structure includes a circuit layer, an electronic component buried in the circuit layer, a first dielectric layer covering the electronic component, and a via hole passing through the first dielectric layer. The via hole is electrically connected to the back surface of the electronic component. The electronic component is an electronic component that is mounted first and then thinned, that is, first FCB on the substrate and then thinned, so as to avoid cracking of the electronic component due to its too thin thickness and inability to withstand a large force during the operation process. In addition, the electronic component is coated, protected, and strengthened by the first dielectric layer, and can be prevented from deforming and cracking during subsequent processes, tests, or applications. In addition, a via hole is formed above the electronic component, which is used as a vertical electrical channel, helps to shorten the electrical transmission path, and improves the electrical transmission efficiency. The present application also proposes a semiconductor packaging device including the above semiconductor package structure. Description of the Drawings

[0030] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments read in conjunction with the accompanying drawings:

[0031] Figure 1 is a schematic longitudinal cross-sectional structure diagram of an existing packaging structure;

[0032] Figure 2 is a schematic longitudinal cross-sectional structure diagram of an embodiment 2a of a semiconductor packaging structure according to the present application;

[0033] Figure 3 is Figure 2 a partially enlarged structure schematic diagram;

[0034] Figure 4 is a schematic longitudinal cross-sectional structure diagram of an embodiment 4a of a semiconductor packaging structure according to the present application;

[0035] Figure 5 is a schematic longitudinal cross-sectional structure diagram of an embodiment 5a of a semiconductor packaging structure according to the present application;

[0036] Figure 6 is a schematic longitudinal cross-sectional structure diagram of an embodiment 6a of a semiconductor packaging device according to the present application;

[0037] Figure 7 is Figure 6 a dimensional schematic diagram of the semiconductor packaging device shown;

[0038] Figure 8 is a schematic longitudinal cross-sectional structure diagram of an embodiment 8a of a semiconductor packaging device according to the present application;

[0039] Figure 9 is a schematic longitudinal cross-sectional structure diagram of an embodiment 9a of a semiconductor packaging device according to the present application;

[0040] Figure 10 is a schematic longitudinal cross-sectional structure diagram of an embodiment 10a of a semiconductor packaging device according to the present application;

[0041] Figure 11 is a schematic longitudinal cross-sectional structure diagram of an embodiment 11a of a semiconductor packaging device according to the present application;

[0042] Figure 12 is a schematic longitudinal cross-sectional structure diagram of an embodiment 12a of a semiconductor packaging device according to the present application;

[0043] Figure 13 is a schematic longitudinal cross-sectional structure diagram of an embodiment 13a of a semiconductor packaging device according to the present application;

[0044] Figure 14 It is a schematic longitudinal cross-sectional structure diagram of an embodiment 14a of a semiconductor packaging device according to the present application;

[0045] Figures 15 - 19 It is a schematic diagram of the manufacturing steps of an embodiment of the semiconductor packaging device of the present application.

[0046] Reference numerals / symbol description:

[0047] 101 - Substrate; 102 - Chip; 103 - TSV (Through - Silicon Via); 104 - Crack;

[0048] 201 - Circuit layer; 2011 - Upper surface; 2012 - Lower surface; 2013 - Cavity; 2014 - Circuit dielectric layer; 2015 - Circuit conductive layer; 2016 - Blind via; 2017 - Seed layer;

[0049] 202 - Electronic component; 2021 - Back surface; 2022 - Active surface; 2023 - Upper pad; 2024 - Lower pad; 2025 - Side surface; 2026 - Recess;

[0050] 203 - First dielectric layer; 204 - First via; 205 - Second via; 206 - Second dielectric layer; 207 - Third via; 208 - Porosity; 209 - Through - Silicon Via; 210 - Bottom connection pad; 211 - Top connection pad; 212 - Micro - bump; 213 - System component; 214 - Third dielectric layer; 215 - Solder ball;

[0051] 200 - First package; 200a - First region; 200b - Second region; 200c - Third region;

[0052] 300 - Second package; 400 - Adhesive layer; 500 - Third package; 600 - Carrier board; 601 - Photoresist. Detailed implementation manners

[0053] The following combines the drawings and embodiments to illustrate the specific implementation manners of the present application. Those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced through the content recorded in this specification. It can be understood that the specific embodiments described herein are only used to explain the relevant invention creations and do not limit the invention creations. In addition, for the convenience of description, only the parts related to the relevant invention creations are shown in the drawings.

[0054] It should be easily understood that the meanings of "on...", "above...", and "over..." in the present application should be interpreted in the broadest sense, such that "on..." not only means "directly on something", but also means "on something" including intermediate components or layers between the two.

[0055] In addition, for ease of description, spatially relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component shown in the drawings. In addition to the orientation described in the figures, the spatially relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0056] The term "layer" as used herein refers to a portion of material that includes a region having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent less than that of the underlying or overlying structure. In addition, the layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below it. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers and may have the same or different materials.

[0057] The term "substrate" as used herein refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer, etc. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0058] It should be noted that the structures, ratios, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present application can be implemented. Therefore, they do not have technical substance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the efficacy and purpose that the present application can achieve, should still fall within the scope that can be covered by the technical content disclosed in the present application. At the same time, the terms such as "upper", "first", "second", and "one" cited in this specification are only for the convenience of clear narration and are not used to limit the scope under which the present application can be implemented. The change or adjustment of their relative relationships, without substantial change in the technical content, should also be regarded as the scope under which the present application can be implemented.

[0059] It should also be noted that the longitudinal section corresponding to the embodiment of the present application can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0060] In addition, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0061] Reference Figures 2 - 3 , Figure 2 is a schematic longitudinal sectional structure diagram of an embodiment 2a of a semiconductor packaging structure according to the present application, Figure 3 is Figure 2 a partially enlarged structural schematic diagram.

[0062] As Figures 2 - 3 shown, the semiconductor packaging structure 2a of the present application includes:

[0063] A circuit layer 201, including an upper surface 2011, a lower surface 2012, and a cavity 2013;

[0064] An electronic component 202, disposed in the cavity 2013, including an active surface 2022 close to the lower surface 2012 and a back surface 2021 close to the upper surface 2011. The active surface 2022 includes a lower solder pad 2024, and the back surface 2021 includes an upper solder pad 2023;

[0065] A first dielectric layer 203, disposed above the circuit layer 201 and covering the electronic component 202;

[0066] A first via 204, disposed in the first dielectric layer 203 and connecting the upper solder pad 2023.

[0067] Here, the wiring layer 201 can be composed of dielectric materials and conductive materials, including but not limited to various substrates, redistribution layers (RDLs). Here, the dielectric materials can include organic and / or inorganic materials. The organic materials can be, for example, polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive materials can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or their alloys.

[0068] Here, the cavity 2013 is formed by being recessed from the upper surface 2011 of the wiring layer 201 towards its lower surface 2012. The cavity 2013 can penetrate or not penetrate the wiring layer 201. By providing the cavity 2013 to accommodate the electronic component 202, the structure is more balanced compared to arranging the electronic component on one side of the wiring layer 201, which helps to reduce the warping of the overall structure.

[0069] Here, the electronic component 202 can be various types of bare chips (i.e., Dies). For example, it can include logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, bare dies or chip-scale packages, inserts, or combinations thereof. Here, the electronic component 202 is arranged in the cavity 2013 with its active surface facing down. Here, the electronic component 202 is first bonded in the cavity 2013 by, for example, FCB (flip chip bonding or flip-chip soldering), and then thinned as a whole to reduce the thickness. Exemplarily, the thickness of the electronic component 202 is as low as between 0.5 micrometers and 5 micrometers, for example, 1 micrometer, 2 micrometers, 3 micrometers, or 4 micrometers.

[0070] Here, the first dielectric layer 203 is a dielectric material. Here, the dielectric material may include organic and / or inorganic substances. For example, the organic substances may be: polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg), ABF (Ajinomoto Build-up Film), etc. And the inorganic substances may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0071] Here, the first via 204 may be a via that passes through the first dielectric layer 203 and reaches and is electrically connected to the upper pad 2023 at the bottom. Here, the first via 204 includes but is not limited to being a PTH (Plating Through Hole) or an NPTH (Non Plating Through Hole). The first via 204 may provide a signal transmission path or a power transmission path (such as a power supply path) for the electronic component 202.

[0072] In some alternative embodiments, the thickness of the electronic component 202 is less than the thickness of the circuit layer 201. Here, after the electronic component 202 is disposed in the cavity 2013 of the circuit layer, it undergoes a thinning process, so its thickness is relatively thin and can be smaller than the thickness of the circuit layer 201. Before the thinning process, the original thickness of the electronic component 202 may be greater than, equal to, or less than the thickness of the circuit layer 201, which is not limited herein.

[0073] In some alternative embodiments, the semiconductor package structure 2a of the present application further includes a second via 205. The second via 205 may be disposed in the first dielectric layer 203 and is used to connect the circuit layer 201. That is, the position of the second via 205 in the top view direction may be outside the cavity 2013. Therefore, the depth of the second via 205 is less than the depth of the first via 204. The second via 205 may be used to provide a signal transmission path for the circuit layer 201.

[0074] In some alternative embodiments, the semiconductor package structure 2a of the present application further includes a second dielectric layer 206 disposed under the circuit layer 201. The second dielectric layer 206 is a dielectric material, and its material may be the same as or different from that of the first dielectric layer 203. The second dielectric layer 206 includes a portion under the cavity 2013 and can be used to carry the electronic component 202.

[0075] In some alternative embodiments, the semiconductor package structure 2a of the present application further includes a third via 207. The third via 207 is disposed within the second dielectric layer 206 and reaches and electrically connects to the lower solder pad 2024 at the bottom. Here, the third via 207 includes, but is not limited to, being a PTH or NPTH. The third via 207 can provide a signal transmission path or a power transmission path (such as a power supply path) for the electronic component 202. Here, since the thickness of the second dielectric layer 206 can be smaller than the thickness of the first dielectric layer 203, correspondingly, the depth of the third via 207 can be less than the depth of the first via 204, and optionally, the aperture of the third via 207 can be smaller than the aperture of the first via 204.

[0076] In some alternative embodiments, such as Figure 3 shown, the back surface 2021 of the electronic component 202 includes a plurality of concave portions 2026 in a curved surface shape. In the manufacturing process, the thinning of the electronic component 202 can be achieved, for example, by an etching process. After etching, a plurality of concave portions 2026 are formed on the back surface 2021 of the electronic component 202, and the longitudinal interface of the concave portions 2026 is substantially in a curved surface shape.

[0077] In some alternative embodiments, such as Figure 3 shown, since the etching is not completely uniform, the depths of the plurality of concave portions 2026 may be different from each other and the widths may be different from each other. Of course, it is also possible that the depths of the plurality of concave portions 2026 are the same as each other and / or the widths are the same as each other.

[0078] In some alternative embodiments, such as Figure 3 shown, the first dielectric layer 203 is filled within the concave portions 2026.

[0079] In some alternative embodiments, such as Figure 3 shown, the first dielectric layer 203 is filled within the cavity 2013 and contacts the side surface of the electronic component 202. There is a gap between the side surface of the electronic component 202 and the side wall of the cavity 2013, and this gap is filled with the first dielectric layer 203.

[0080] In some alternative embodiments, such as Figure 3 shown, there are pores 208 between the side wall of the cavity 2013 and the first dielectric layer 203. In the manufacturing process, if the air within the cavity 2013 is not completely removed when the first dielectric layer 203 is provided, pores 208 as shown in Figure 3 shown are usually formed at the side wall of the cavity 2013. The pores 208 do not affect the function and quality of the product.

[0081] In some alternative embodiments, such as Figure 3As shown, the through-silicon via 209 is provided inside the electronic component 202. The through-silicon via 209 connects the active surface 2022 and the back surface 2021 of the electronic component 202, serving as a path for vertical conduction.

[0082] In some alternative embodiments, referring to Figure 2 , the materials of the first dielectric layer 203 and the second dielectric layer 206 are different to provide different characteristics, which can contribute to improving the performance of the product, such as suppressing warping.

[0083] In some alternative embodiments, referring to Figure 2 , the Young's modulus of the first dielectric layer 203 is greater than that of the second dielectric layer 206, and the thermal expansion coefficient of the first dielectric layer 203 is greater than that of the second dielectric layer 206. In this way, the structural balance can be maintained and warping during temperature changes can be suppressed.

[0084] In some alternative embodiments, referring to Figure 2 , the circuit layer 201 includes at least one circuit dielectric layer 2014 and at least one circuit conductive layer 2015, and according to the process requirements, a seed layer is also provided between the circuit dielectric layer 2014 and the circuit conductive layer 2015.

[0085] In some alternative embodiments, the Young's modulus of the circuit dielectric layer 2014 is between that of the first dielectric layer 203 and the second dielectric layer 206, and the thermal expansion coefficient of the circuit dielectric layer 2014 is between that of the first dielectric layer 203 and the second dielectric layer 206. In this way, from top to bottom, the Young's modulus changes in sequence and the thermal expansion coefficient changes in sequence, which can suppress warping caused by mismatches in thermal expansion coefficients, etc.

[0086] In some alternative embodiments, referring to Figure 2 and Figure 3 , the cavity 2013 penetrates the circuit layer 201, and the lower surface 2012 of the circuit layer 201 and the active surface 2022 of the electronic component 202 are substantially flush.

[0087] In some alternative embodiments, in the top view direction, the electronic component 202 is closer to the edge of the circuit layer 201 relative to the center of the circuit layer 201. The area near the center of the circuit layer 201 is the area with the maximum stress, and the stress near the edge is relatively small. Making the electronic component 202 closer to the edge of the circuit layer 201 can reduce the stress on the electronic component 202, which helps to protect the electronic component 202, such as preventing the electronic component 202 from cracking or breaking due to excessive stress.

[0088] In some alternative embodiments, the bottom surface of the semiconductor package structure 2a of the present application includes a plurality of bottom connection pads 210, and / or the top surface of the semiconductor package structure 2a includes a plurality of top connection pads 211. The bottom connection pads 210 and the top connection pads 211 are configured to achieve external electrical connections.

[0089] Here, by configuring the first vias 204, the second vias 205, the third vias 207, as well as the top connection pads 211 and the bottom connection pads 210, it is supported to achieve external electrical connections in a low-cost manner.

[0090] Reference Figure 4 , Figure 4 is a schematic longitudinal cross-sectional structure diagram of an embodiment 4a of the semiconductor package structure according to the present application. As Figure 4 shown, the semiconductor package structure 4a is similar to Figure 2 the semiconductor package structure 2a shown, with the difference that:

[0091] The semiconductor package structure 4a further includes a connector 212 disposed on the bottom connection pads 210, and the bottom connection pads 210 can be externally electrically connected through the connector 212. Here, the connector 212 includes but is not limited to being a bump or a micro-bump (μbump).

[0092] In some alternative embodiments, the semiconductor package structure 4a further includes a third dielectric layer 214 disposed above the first dielectric layer 203. Correspondingly, the top connection pads 211 can be disposed above the third dielectric layer 214. The third dielectric layer 214 is a dielectric material, and its material can be the same as or different from that of the first dielectric layer 203. Adapted to the structural requirements, the coefficient of thermal expansion of the third dielectric layer 214 can be less than, equal to, or greater than that of the first dielectric layer 203, and the Young's modulus of the third dielectric layer 214 can be less than, equal to, or greater than that of the first dielectric layer 203.

[0093] Reference Figure 5 , Figure 5 is a schematic longitudinal cross-sectional structure diagram of an embodiment 5a of the semiconductor package structure according to the present application. As Figure 5 shown, the semiconductor package structure 5a is similar to Figure 2 the semiconductor package structure 2a shown, with the difference that:

[0094] For the semiconductor package structure 5a, there are a plurality of cavities 2013 and electronic components 202 respectively. One electronic component 202 is separately disposed in one cavity 2013. Here, the plurality of cavities 2013 can be arranged side by side. The sizes of the plurality of cavities 2013 can be the same or different. The types, sizes, and thicknesses of the electronic components 202 disposed in each cavity 2013 can be the same or different from each other.

[0095] Reference Figure 6 , Figure 6 is a schematic longitudinal sectional structure diagram of an embodiment 6a of a semiconductor packaging device according to the present application. As Figure 6 shown, the semiconductor packaging device 6a of the present application includes a plurality of stacked packages, and at least one of the plurality of packages is a semiconductor packaging structure as described in any one of Figures 2 to 6 .

[0096] In some alternative embodiments, the plurality of packages include adjacent first package 200 and second package 300, and both the first package 200 and the second package 300 are semiconductor packaging structures as described in any one of Figures 2 to 6 . The second package 300 is stacked on the first package 200.

[0097] In some alternative embodiments, the bottom connection pads 210 of the first package 200 are opposite to and electrically connected to the bottom connection pads 210 of the second package 300. Optionally, the bottom connection pads 210 of the first package 200 and the bottom connection pads 210 of the second package 300 are electrically connected through a connector 212. Optionally, an adhesive layer 400 is further filled in the gap between the first package 200 and the second package 300. The adhesive layer 400 is mainly used for adhesively fixing the first package 200 and the second package 300, and the adhesive layer 400 is also used for covering and protecting the connector 212 and the bottom connection pads 210.

[0098] Reference Figure 7 , Figure 7 is Figure 6 a schematic diagram of the dimensions of the semiconductor packaging device 6a shown in

[0099] As Figure 7 shown in the semiconductor packaging device 6a, the dimensions of each main component are as follows:

[0100] Electronic component 202: The horizontal dimension (width / length) is approximately between several tens of micrometers and several hundreds of mm; the vertical dimension (thickness CT) is approximately between 0.5 micrometers and 5 micrometers;

[0101] The thickness (BLT) of the adhesive layer 400: is approximately between 5 micrometers and 30 micrometers;

[0102] The dimension (CED) from the back surface of the electronic component 202 to the opening of the cavity 2013, that is, the value obtained by subtracting the thickness of the electronic component 202 from the depth of the cavity 2013, is approximately between 0.5 micrometers and 5 micrometers;

[0103] The thickness (RDT) of the circuit dielectric layer 2014: is approximately between 2 micrometers and 10 micrometers;

[0104] The thickness of the circuit conductive layer 2015 (RDL) is between 1 μm and 10 μm, the line width is between 1 μm and 10 μm, the line pitch is between 1 μm and 10 μm, and the thickness of the seed layer is between 0.1 μm and 1 μm;

[0105] The diameter of the connector 212 is between 3 μm and 20 μm, and the pitch is between 5 μm and 50 μm.

[0106] Further, as Figure 7 shown, the first package 200 can be divided into three parts according to the distance from the adhesive layer 400 at the center, that is, first, the first region 200a closest to the adhesive layer 400, second, the second region 200b, and finally, the third region 200c far from the adhesive layer 400.

[0107] Similarly, the second package 300 can be divided into the same three parts, that is, first, the first region 200a closest to the adhesive layer 400, second, the second region 200b, and finally, the third region 200c far from the adhesive layer 400.

[0108] Exemplarily, the first region 200a includes, for example, the second dielectric layer 206, the second region 200b includes, for example, the circuit layer 201, and the third region 200c includes, for example, the first dielectric layer 203 (excluding the part filled in the cavity 2013).

[0109] In some alternative embodiments, in order to improve the overall structural stability, the Young's modulus (representing the structural strength) and the coefficient of thermal expansion of the above three parts satisfy the following relationships:

[0110] In terms of Young's modulus, the first region 200a (10 MPa to 30 MPa) < the second region 200b (20 MPa to 40 MPa) < the third region 200c (30 MPa to 60 MPa);

[0111] In terms of the coefficient of thermal expansion (CTE), the first region 200a (20 ppm to 50 ppm) < the second region 200b (40 ppm to 80 ppm) < the third region 200c (60 ppm to 100 ppm).

[0112] Following the above relationships, there are: the Young's modulus of the first dielectric layer 203 > the Young's modulus of the circuit dielectric layer 2014 the Young's modulus of the second dielectric layer 206 of the circuit dielectric layer 2014, the coefficient of thermal expansion of the first dielectric layer 203 the coefficient of thermal expansion of the circuit dielectric layer 2014 the coefficient of thermal expansion of the circuit dielectric layer 2014 the coefficient of thermal expansion of the second dielectric layer 206 of the circuit dielectric layer 2014.

[0113] In the above manner, the closer a part of the semiconductor packaging device is to the center, the smaller its Young's modulus and coefficient of thermal expansion. The farther a part is from the center, the larger its Young's modulus and coefficient of thermal expansion. In this way, warping of the device during temperature changes can be effectively suppressed, the structural balance inside the device can be maintained, the structural stress inside the device can be reduced, and the stress borne by the internal electronic component 202 can be decreased.

[0114] In addition, the materials of each part in this application are described as follows:

[0115] (1) For the dielectric materials of each dielectric layer and the material of the adhesive layer 400, non-metallic materials such as PI (polyimide), epoxy resin, ABF (Ajinomoto Build-up Film), pp (prepreg), or / and acrylic acid can be used, for example.

[0116] (2) For each conductive layer, connection pad, etc., metallic materials such as copper, gold, silver, aluminum, palladium, platinum, and nickel and their alloys can be used, for example. For the seed layer, metallic materials such as titanium, nickel, tungsten, palladium, platinum, and their alloys can be used, for example. The connector 212 can be made of solder, conductive adhesive (ACP / ACF), etc., and the manufacturing processes include but are not limited to PVD (physical vapor deposition), electroplating, electroless plating, printing, and potting.

[0117] Reference Figure 8 , Figure 8 is a schematic longitudinal cross-sectional structure diagram of an embodiment 8a of the semiconductor packaging device according to this application. Figure 8 The shown semiconductor packaging device 8a is similar to Figure 6 the shown semiconductor packaging device 6a, with the differences being:

[0118] For the semiconductor packaging device 6a, when viewed from the top-down direction, relative to the center of the semiconductor packaging device 6a, the electronic component 202 is closer to the edge of the semiconductor packaging device 6a; the area near the center is the area with the maximum stress, and the stress near the edge is relatively small. Making the electronic component 202 closer to the edge can reduce the stress borne by the electronic component 202, which helps to protect the electronic component 202, for example, preventing the electronic component 202 from cracking or breaking due to excessive stress.

[0119] For the semiconductor packaging device 8a, when viewed from the top-down direction, relative to the edge of the semiconductor packaging device 8a, the electronic component 202 is closer to the center of the semiconductor packaging device 8a.

[0120] Reference Figure 9 , Figure 9 is a schematic longitudinal cross-sectional structure diagram of an embodiment 9a of the semiconductor packaging device according to this application. Figure 9 The shown semiconductor packaging device 9a is similar to Figure 6The semiconductor packaging device 6a shown is different in that:

[0121] In the semiconductor packaging device 9a, the bottom connection pads 210 of the first package body 200 face the bottom connection pads 210 of the second package body 300 and are electrically connected to each other in a direct bonding manner without the need for Figure 6 the connector 212 shown in. Direct Bonding is a method of joining two clean and flat surfaces through physical contact, including but not limited to copper-to-copper direct bonding. This bonding relies on the microscopic mechanical forces on the material surface, such as van der Waals forces, and possibly chemical bonding.

[0122] Refer to Figure 10 , Figure 10 is a schematic longitudinal cross-sectional structure diagram of an embodiment 10a of the semiconductor packaging device according to the present application. Figure 10 The semiconductor packaging device 10a shown is similar to Figure 6 the semiconductor packaging device 6a shown, different in that:

[0123] In the semiconductor packaging device 10a, the second package body 300 is any of the semiconductor packaging structures described in Figures 2 to 5 , where the electronic component 202 is a double-sided IO and has been thinned; while the electronic component 202 in the first package body 200 can be a single-sided IO and / or has not been thinned.

[0124] Refer to Figure 11 , Figure 11 is a schematic longitudinal cross-sectional structure diagram of an embodiment 11a of the semiconductor packaging device according to the present application. Figure 11 The semiconductor packaging device 11a shown is similar to Figure 6 the semiconductor packaging device 6a shown, different in that:

[0125] The semiconductor packaging device 11a includes opposite top and bottom surfaces, and its top surface can be provided with system components 213, and / or its bottom surface can be provided with solder balls 215.

[0126] Here, the system component 213 can be various electronic components, which can include active devices such as bare chips (Dies), and can also include passive devices such as resistors, capacitors, inductors, etc.

[0127] Here, the solder ball 215 is a spherical connector, and its material can include tin for realizing external connection.

[0128] Refer to Figure 12 , Figure 12 is a schematic longitudinal cross-sectional structure diagram of an embodiment 12a of the semiconductor packaging device according to the present application. Figure 12The semiconductor packaging device 12a shown is similar to Figure 6 the semiconductor packaging device 6a shown, except that:

[0129] In the semiconductor packaging device 12a, the top connection pads 211 of the first package 200 are opposite to and electrically connected to each other with the top connection pads 211 of the second package 300.

[0130] Combined Figure 6 with Figure 12 it can be understood that in some other alternative embodiments, it can also be that the bottom connection pads 210 of the first package 200 are opposite to and electrically connected to each other with the top connection pads 211 of the second package 300, or the top connection pads 211 of the first package 200 are opposite to and electrically connected to each other with the bottom connection pads 210 of the second package 300. Among them, the so-called electrical connection can be a direct bonding or can be bonded through a connector 212 (such as a micro-bump).

[0131] Referring to Figure 13 , Figure 13 is a schematic longitudinal cross-sectional structure diagram of an embodiment 13a of a semiconductor packaging device according to the present application. Figure 13 The semiconductor packaging device 13a shown is similar to Figure 6 the semiconductor packaging device 6a shown, except that:

[0132] In the semiconductor packaging device 13a, the second package 300 includes a plurality of cavities 2013, and a plurality of electronic components 202 are respectively arranged in the plurality of cavities 2013.

[0133] Referring to Figure 14 , Figure 14 is a schematic longitudinal cross-sectional structure diagram of an embodiment 14a of a semiconductor packaging device according to the present application. Figure 14 The semiconductor packaging device 14a shown is similar to Figure 6 the semiconductor packaging device 6a shown, except that:

[0134] In the semiconductor packaging device 14a, the number of packages is more than two. In addition to the first package 200 and the second package 300, it can also include at least one third package 500. These packages are stacked in sequence to form the semiconductor packaging device 14a of the present application.

[0135] Above, combined Figures 2 to 14, this application discloses a semiconductor packaging structure and a semiconductor packaging device stacked based on this semiconductor packaging structure. To solve the problem that the chip is prone to cracking under stress during the FCB operation after thinning, this application first mounts the electronic component 202 in the cavity 2013 of the circuit layer 201, then thins the electronic component 202 as a whole, and then forms a first dielectric layer 203 and a second dielectric layer 206 above and below the circuit layer 201 respectively, and fabricates the first vias 204, the second vias 205 and the third vias 207. In this way, it can be avoided that the electronic component 202 cracks due to its too thin thickness during the operation process and cannot withstand a large force when being picked up and placed. In addition, the first vias 204 are formed above the electronic component 202 and used as vertical electrical channels, which helps to shorten the electrical transmission path and improve the electrical transmission efficiency. In addition, the surrounding (top, edge and bottom) of the electronic component 202 is coated and protected with dielectric materials (the first dielectric layer 203 and the second dielectric layer 206), such as PI (polyimide) / epoxy resin, etc., and its strength is supported, which can further prevent the embedded ultra-thin electronic component 202 from deforming and cracking during subsequent processes, tests or applications.

[0136] In this application, thinning the electronic component 202 is also beneficial to reducing the overall thickness of the product and facilitating the miniaturization of the product.

[0137] This application supports thinning the electronic component 202 as a whole after placing the electronic component 202 into the cavity 2013 and fabricating fine lines on the circuit layer 201, such as lines with a line width not exceeding 2 microns and a line pitch not exceeding 2 microns.

[0138] This application supports combining multiple semiconductor packaging structures together in a stacked manner (through connectors such as micro-bumps or direct bonding) to form a semiconductor packaging device, supports power supply to the back of the electronic component, supports more IOs, and supports high production capacity.

[0139] This application supports using panel-level or wafer-level manufacturing processes to improve manufacturing efficiency.

[0140] This application helps to integrate various different types and functions of chips, such as EIC (electronic integrated chip), deep trench capacitor (DTC) and integrated voltage regulator (IVR), etc., into the semiconductor packaging structure / device, provides an excellent solution for this, and can achieve good performance.

[0141] Reference Figures 15 - 19 , Figures 15 - 19 is a schematic diagram of the manufacturing steps of an embodiment of the semiconductor packaging device of this application. As Figures 15 - 19 shown, the manufacturing steps of the semiconductor packaging device of this application may include:

[0142] Step S1, on a carrier board 600, a dielectric layer and a conductive layer are formed by conventional techniques as the first layer of circuit dielectric layer 2014 and the first layer of circuit conductive layer 2015. Among them, cavities 2013 penetrating to the surface of the carrier board 600 are formed on the first layer of circuit dielectric layer 2014 and the first layer of circuit conductive layer 2015. Optionally, the first layer of circuit conductive layer 2015 is an RDL (redistribution layer). Optionally, a plurality of conductive vias may be formed in the first layer of circuit dielectric layer 2015.

[0143] Step S2, an electronic component 202 is placed into the cavity 2013, and the active surface of the electronic component 202 faces downward (i.e., towards the carrier board 600).

[0144] Step S3, on the first layer of circuit conductive layer 2015, a second layer of circuit dielectric layer 2014 is provided, for example, by coating or lamination, and photolithography is performed. Optionally, the second layer of circuit dielectric layer 2014 may be filled in the cavity 2013, that is, in the interval between the side wall of the cavity 2013 and the electronic component 202.

[0145] Step S4, the second layer of circuit dielectric layer 2014 after photolithography is developed to form the required conductive vias, and the back surface of the electronic component 202 is thinned by an etching process.

[0146] Step S5 shows the thinned electronic component 202, whose thickness is reduced to the required size.

[0147] Step S6, above the second layer of circuit dielectric layer 2014 and the electronic component 202, a layer of metal is deposited as a seed layer 2017 by, for example, physical vapor deposition (PVD) process.

[0148] Step S7, a layer of photoresist 601 is provided above the seed layer 2017, for example, by coating, and photolithography is performed.

[0149] Step S8, the photoresist 601 is developed to form the defined pattern. Based on the pattern defined by the photoresist 601, a conductive layer is fabricated on the seed layer 2017 as the second layer of circuit conductive layer 2015 by electroplating process.

[0150] Step S9, the photoresist 601 is removed, and the excess seed layer 2017 is removed by etching. Thus, the circuit layer 201 is fabricated.

[0151] Step S10, above the circuit layer 201, a layer of dielectric is provided as the first dielectric layer 203, for example, by coating or lamination. The material of the first dielectric layer 203 may be the same as or different from that of the circuit dielectric layer 2014.

[0152] Optionally, after step S10, more conductive layers and dielectric layers can be added by repeating some or all of the above steps S6 - S10.

[0153] Step S11: Form a plurality of holes in the first dielectric layer 203, for example, by photolithography and development. And define a pattern by setting a photoresist and performing photolithography and development on the photoresist. Electroplate based on the defined pattern to metallize the plurality of holes, forming a first via hole 204 that electrically connects to the back surface of the electronic component 202 and a second via hole 205 that electrically connects to the circuit layer 201, and forming a plurality of top connection pads 211 above the first dielectric layer 203.

[0154] Step S12: Remove the carrier plate 600 to expose the lower surface 2012 of the circuit layer 201.

[0155] Step S13: Flip the structure obtained in the previous step so that the lower surface 2012 of the circuit layer 201 faces upward.

[0156] Step S14: On the lower surface 2012 of the circuit layer 201, set a dielectric layer as the second dielectric layer 206 by coating or laminating, etc. The material of the second dielectric layer 206 can be the same as or different from the material of the first dielectric layer 203. And after performing photolithography and development on the second dielectric layer 206 to form the required holes, deposit a layer of metal as a seed layer 2017 through PVD process.

[0157] Step S15: Set a layer of photoresist 601 on the seed layer 2017 and perform photolithography.

[0158] Step S16: Make the pattern defined by the photoresist 601 take shape through development. Electroplate based on the pattern defined by the photoresist 601 to metallize the holes formed in step S14, forming a third via hole 207 that electrically connects to the active surface of the electronic component 202, and forming bottom connection pads 210 on the second dielectric layer 206. Optionally, micro - bumps can be further set on the bottom connection pads 210 as connectors 212.

[0159] Step S17: Remove the photoresist 601.

[0160] So far, through the above steps S1 - S17, combined with methods such as photolithography, electroplating, and etching, a semiconductor package structure of the present application can be fabricated by a panel - level or wafer - level process as the first package body 200. The circuit structure therein is a fine circuit, for example, the line width does not exceed 2 microns or even 1 micron, and the line pitch does not exceed 2 microns or even 1 micron.

[0161] Step S18: Provide a second package body 300. The manufacturing steps of the second package body 300 are similar to the aforementioned steps S1 - S17 and will not be elaborated here.

[0162] Step S19: Stack the second encapsulation body 300 above the first encapsulation body 200, and electrically connect the two through the connector 212 and bond them through the adhesive layer 400.

[0163] Step S20: Perform singulation (i.e., cut into individual units).

[0164] Thus, the semiconductor encapsulation device of the present application is obtained.

[0165] Above, although the present application has been described and illustrated with reference to specific embodiments of the present application, these descriptions and illustrations do not limit the present application. Those skilled in the art can clearly understand that various changes can be made, and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The drawings may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction and the actual implementation in the present application. There may be other embodiments of the present application that are not specifically described. The specification and the drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present application. All such modifications fall within the scope of the appended claims herein. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present application to form equivalent methods. Therefore, unless specifically indicated herein, the order and grouping of the operations do not limit the present application.

Claims

1. A semiconductor package structure, characterized in that, Comprising: A circuit layer, including an upper surface, a lower surface, and a cavity; An electronic component, disposed within the cavity, including an active surface near the lower surface and a back surface near the upper surface, the active surface including a lower solder pad, and the back surface including an upper solder pad; A first dielectric layer, disposed above the circuit layer and covering the electronic component; A first via hole, disposed within the first dielectric layer and connecting the upper solder pad.

2. The semiconductor package structure according to claim 1, wherein, The thickness of the electronic component is less than the thickness of the circuit layer.

3. The semiconductor package structure according to claim 2, wherein Further comprising: A second via hole, disposed within the first dielectric layer and connecting the circuit layer; The depth of the second via hole is less than the depth of the first via hole.

4. The semiconductor package structure according to claim 1, wherein Further comprising: A second dielectric layer, disposed below the circuit layer; A third via hole, disposed within the second dielectric layer and connecting the lower solder pad; The aperture of the third via hole is less than the aperture of the first via hole, and the depth of the third via hole is less than the depth of the first via hole.

5. The semiconductor package structure according to claim 1, wherein The back surface of the electronic component includes a plurality of concave portions having a curved surface shape.

6. The semiconductor package structure according to claim 5, wherein The depths of the plurality of concave portions are different from each other and the widths are different from each other.

7. The semiconductor package structure according to claim 5, wherein, The first dielectric layer fills the concave portions.

8. The semiconductor package structure according to claim 1, wherein, The first dielectric layer fills the cavity and contacts the side surface of the electronic component.

9. The semiconductor package structure according to claim 8, wherein There is a pore between the side wall of the cavity and the first dielectric layer.

10. The semiconductor package structure according to claim 1, wherein The cavity penetrates the circuit layer, and the lower surface of the circuit layer and the active surface of the electronic component are substantially flush.

Images