Semiconductor package device

Abstract

The utility model provides a semiconductor packaging device. The semiconductor packaging device comprises a first substrate; the wafer is electrically connected to the first substrate; the heat dissipation structure is made of a non-conductive material, surrounds the peripheral side of the wafer and is located on the first substrate, the top surface of the heat dissipation structure is higher than the top surface of the wafer, the heat dissipation structure comprises a heat dissipation channel and cooling fluid arranged in the heat dissipation channel, and the heat dissipation channel penetrates through the heat dissipation structure. The heat dissipation structure is arranged on the peripheral side of the wafer, the heat dissipation structure is arranged to be of a hollow structure, cooling liquid is guided into the heat dissipation channels, and therefore the heat dissipation efficiency can be improved without changing materials and the original manufacturing process.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and particularly to a semiconductor packaging device. Background Art

[0002] With the improvement of the computing power of electronic products, the waste heat generated during their operation will also increase. High temperatures will not only affect the performance of electronic products, but also reduce the service life of products, and even cause system failures, affecting the reliability and safety of products.

[0003] Traditional heat dissipation solutions generally improve the heat dissipation ability of products by changing materials when encountering high heat problems. For example, replacing solder paste with sintered silver. However, improving materials takes a long time, and the original manufacturing process needs to be modified. Summary of the Utility Model

[0004] This application proposes a semiconductor packaging device.

[0005] In a first aspect, the semiconductor packaging device provided by this application includes: a first substrate; a wafer disposed electrically connected to the first substrate; a heat dissipation structure made of a non-conductive material, surrounding the circumference of the wafer and located on the first substrate, the top surface of the heat dissipation structure being higher than the top surface of the wafer, the heat dissipation structure including a heat dissipation channel and a cooling fluid disposed in the heat dissipation channel, the heat dissipation channel penetrating through the heat dissipation structure.

[0006] In some alternative embodiments, the heat dissipation structure is disposed along the circumference of the wafer.

[0007] In some alternative embodiments, the heat dissipation channel is conformal to the circumference of the wafer.

[0008] In some alternative embodiments, the diameters of the open end and the outlet end of the heat dissipation channel are the same.

[0009] In some alternative embodiments, the material of the heat dissipation structure is aluminum nitride ceramic.

[0010] In some alternative embodiments, the wafer is electrically connected to the first substrate through solder balls.

[0011] In some alternative embodiments, the bottom surface of the heat dissipation structure directly contacts the first substrate.

[0012] In some alternative embodiments, it further includes a molding member configured to fill the space between the top surface of the wafer and the heat dissipation structure.

[0013] In some alternative embodiments, the top surface of the heat dissipation channel is higher than the top surface of the wafer.

[0014] In some alternative embodiments, the bottom surface of the heat dissipation channel is lower than the bottom surface of the wafer.

[0015] To solve the problems of the need to improve the heat dissipation capacity of products by changing materials and the need to modify the original manufacturing process when changing materials, the present application proposes a semiconductor packaging device. By arranging a heat dissipation structure on the periphery of the wafer and setting the heat dissipation structure as a hollow structure, cooling liquid can be introduced between the heat dissipation channels, so as to improve the heat dissipation efficiency without changing materials and the original manufacturing process. Description of the Drawings

[0016] By reading the following detailed description of the non-restrictive embodiments with reference to the accompanying drawings, other features, objects, and advantages of the present application will become more apparent:

[0017] Figure 1 is a schematic structural diagram of an existing electronic product;

[0018] Figure 2 is a schematic structural diagram of an embodiment 2a of the semiconductor packaging device according to the present application;

[0019] Figure 3 is Figure 2 a top view of;

[0020] Figure 4 is a schematic structural diagram of an embodiment of the heat dissipation structure according to the present application;

[0021] Figure 5 Schematic structural diagram of a side view of an embodiment 3a of the semiconductor packaging device according to the present application;

[0022] Figure 6 is a schematic structural diagram of a side view of an embodiment 4a of the semiconductor packaging device according to the present application.

[0023] Description of the Reference Numerals / Symbols:

[0024] 101 - First substrate; 102 - Second substrate; 103 - Solder ball; 104 - Bare chip; 105 - Diode; 106 - Insulated gate bipolar transistor; 201 - First substrate; 202 - Wafer; 203 - Heat dissipation structure; 204 - Solder ball; 205 - Molded package; 206 - Second substrate; 2021 - Wafer top surface; 2022 - Wafer bottom surface; 2031 - Heat dissipation channel; 2032 - Heat dissipation structure top surface; 20311 - Open end; 20312 - Outlet end; 20313 - Heat dissipation channel top surface; 20314 - Heat dissipation channel bottom surface. Detailed Embodiments

[0025] The following describes the specific implementation manners of the present application in conjunction with the accompanying drawings and embodiments. Those skilled in the art can easily understand the technical problems solved by the present application and the technical effects produced through the content recorded in this specification. It can be understood that the specific embodiments described herein are only used to explain the relevant invention and are not intended to limit the invention. Additionally, for ease of description, only the parts related to the relevant invention are shown in the drawings.

[0026] It should be easily understood that the meanings of "on", "above", and "over" in the present application should be interpreted in the broadest sense, such that "on" not only means "directly on something", but also means "on something" including intermediate components or layers therebetween.

[0027] In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0028] The term "layer" as used herein refers to a portion of a material including a region having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent less than that of the underlying or overlying structure. Additionally, the layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above, and / or below it. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers and may have the same or different materials.

[0029] The term "substrate" as used herein refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include various semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer, etc. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0030] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present application, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the effects and purposes that can be achieved by the present application, should still fall within the scope of the technical content disclosed in the present application. At the same time, the terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of narration, and are not used to limit the scope of the implementation of the present application. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present application without substantially changing the technical content.

[0031] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0032] In addition, the embodiments and features in the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] refer to Figure 1 , Figure 1 It is a structural schematic diagram based on an existing electronic product.

[0034] like Figure 1 The electronic product structure shown includes a first substrate 101 , a second substrate 102 , solder balls 103 , a bare chip 104 , a diode 105 , and an insulated gate bipolar transistor 106 .

[0035] In this structure, a bare chip 104, a diode 105 and an insulated gate bipolar transistor 106 are arranged between the first substrate 101 and the second substrate 102, and the bare chip 104, the diode 105 and the insulated gate bipolar transistor 106 are electrically connected to the first substrate 101 and the second substrate 102 through the solder ball 103, wherein the bare chip 104, the diode 105 and the insulated gate bipolar transistor 106 exist in the same power module.

[0036] As the computing power of electronic products increases, the number of various chips in the same power module will gradually increase, and the waste heat generated during operation will also increase. If the heat dissipation capacity of the module is insufficient, it will affect the performance of the electronic product and reduce the product's service life.

[0037] Traditional heat dissipation solutions generally improve the heat dissipation capacity of products by changing materials when encountering high heat problems. For example, changing the solder balls 103 to sintered silver. However, improving the material takes a long time and requires modification of the original manufacturing process.

[0038] Reference Figure 2 and Figure 3 , Figure 2 FIG. 9 is a schematic structural diagram of an embodiment 2a of a semiconductor packaging device according to the present application. Figure 3 is Figure 2 a top view of FIG. 9.

[0039] As Figure 2 and Figure 3 shown in FIGS. 18 and 19, the semiconductor packaging device 2a of the present application includes: a first substrate 201; a wafer 202 disposed to be electrically connected to the first substrate 201; a heat dissipation structure 203 made of a non-conductive material, surrounding the peripheral side of the wafer 202 and located on the first substrate 201, the top surface 2032 of the heat dissipation structure 203 being higher than the top surface 2021 of the wafer 202, the heat dissipation structure 203 including a heat dissipation channel 2031 and a cooling fluid disposed in the heat dissipation channel 2031, and the heat dissipation channel 2031 penetrating through the heat dissipation structure 203.

[0040] Here, the first substrate 201 may be a substrate composed of a conductive material and a dielectric material. Here, the conductive material may include a seed layer and a metal layer. The seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. Here, the dielectric material may include organic substances and / or inorganic substances. The organic substances may be, for example: polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylenebenzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg), ABF (Ajinomoto Build-up Film), etc. The inorganic substances may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. Here, the substrate 201 may also be a PCB (Printed Circuit Board).

[0041] Here, the wafer 202 can be various types of dies. This application does not make specific limitations in this regard. For example, the wafer 202 can include logic function chips, memory chips, communication chips, microprocessor chips, graphics chips, micro-electro-mechanical system (MEMS) chips, radio frequency chips, dies or chip scale packages, inserts, or combinations thereof, etc.

[0042] In some alternative embodiments, the wafer 202 can be electrically connected to the first substrate 201 through a solder joint such as a solder ball 204, and the solder ball 204 can be disposed between the wafer 202 and the first substrate 201.

[0043] Here, the heat dissipation structure 203 can be made of a rigid material to effectively control the total thickness of the overall packaging device, such that it is not affected by the wafer 202.

[0044] In some alternative embodiments, the material of the heat dissipation structure 203 can be ceramics such as aluminum nitride ceramics.

[0045] Aluminum nitride ceramics are heat-conducting but non-conductive materials. They not only have excellent electrical insulation performance, good heat resistance, but also have excellent heat dissipation ability, and will not cause short circuits due to the mutual flow of current. Moreover, aluminum nitride ceramics can still maintain structural stability at high temperatures.

[0046] Here, the heat dissipation structure 203 surrounds the peripheral side of the wafer 202 and is located on the first substrate 201. The top surface of the heat dissipation structure 203 is higher than the top surface 2032 of the wafer 202. In this way, the heat exchange area between the heat dissipation structure 203 and the wafer 202 can be increased, the heat dissipation efficiency can be improved, and at the same time, the wafer 202 can be positioned. Here, the heat dissipation structure 203 surrounding the peripheral side of the wafer 202 can be that the heat dissipation structure 203 surrounds the four sides of the wafer 202 and contacts one or more of the four side surfaces of the wafer 202.

[0047] Here, the heat dissipation structure 203 can include a heat dissipation channel 2031 and a cooling fluid disposed in the heat dissipation channel 2031. The heat dissipation channel 2031 penetrates through the heat dissipation structure 203. In this way, the heat dissipation structure 203 is set as a hollow structure. By introducing the cooling fluid into the heat dissipation channel 2031, the heat dissipation rate can be accelerated, and the heat dissipation ability of the product can be improved without the need to improve the materials and the original manufacturing process.

[0048] Continuing to refer to Figure 2 and Figure 3 , in some alternative embodiments, the heat dissipation structure 203 is disposed along the perimeter of the wafer 202.

[0049] The heat dissipation structure 203 contacts the peripheral side of the chip 202, which can increase the contact area between the heat dissipation structure 203 and the chip 202, enabling the heat dissipation structure 203 to extract the heat generated by the chip 202 more effectively and improving the heat dissipation efficiency.

[0050] In some alternative embodiments, the heat dissipation channel 2031 is conformal with the peripheral edge of the chip 202.

[0051] By setting the heat dissipation channel 2031 to be conformal with the peripheral edge of the chip 202 and introducing the cooling fluid into the heat dissipation channel 2031, the cooling fluid can be made conformal with the peripheral edge of the chip 202, accelerating the heat dissipation rate of the chip and improving the heat dissipation effect.

[0052] In some alternative embodiments, the diameters of the open end 20311 and the outlet end 20312 of the heat dissipation channel 2031 are the same.

[0053] Here, when the diameters of the open end 20311 and the outlet end 20312 of the heat dissipation channel 2031 are the same, it can ensure that the coolant flows more smoothly in the heat dissipation channel, reducing the fluid resistance. At the same time, it can make the heat dissipation around the chip 202 more uniform, ensuring the stable operation of the heat dissipation structure 203.

[0054] In some alternative embodiments, the cooling fluid flows into the heat dissipation channel 2031 from the open end 20311 and flows out from the outlet end 20312 of the heat dissipation channel 2031.

[0055] Here, the heat dissipation channel 2031 can be provided with multiple open ends 20311 and multiple outlet ends 20312, and the specific numbers of the open ends 20311 and the outlet ends 20312 can be designed according to the actual product.

[0056] The cooling fluid can flow into the heat dissipation channel 2031 from the open end 20311 and flow out from the outlet end 20312, and the heat can be removed through the cooling fluid.

[0057] In some alternative embodiments, the numbers of the open ends 20311 and the outlet ends 20312 of the heat dissipation channel 2031 are the same.

[0058] By setting the number of the open ends 20311 of the heat dissipation channel 2031 to be the same as the number of the outlet ends 20312, the cooling liquid passing through the heat dissipation structure 203 can be more effectively balanced, enabling each part of the heat dissipation channel 2031 to receive a cooling liquid with a nearly identical flow rate, which helps to maintain a uniform temperature distribution throughout the heat dissipation structure 203 and avoid local overheating.

[0059] Continue to refer to Figure 1 , in some alternative embodiments, the top surface 20313 of the heat dissipation channel 2031 is higher than the top surface 2021 of the chip 202.

[0060] In some alternative embodiments, the bottom surface 20314 of the heat dissipation channel 2031 is lower than the bottom surface 2022 of the wafer 202.

[0061] In this way, the heat dissipation channel 2031 can completely surround the circumferential side of the wafer 202, and further improve the heat dissipation effect.

[0062] In some alternative embodiments, the bottom surface of the heat dissipation structure 203 is in direct contact with the first substrate 201.

[0063] In some alternative embodiments, the heat dissipation structure 203 further includes an adhesive layer disposed between the heat dissipation structure 203 and the first substrate 201. In this way, the heat dissipation structure 203 can be fixed to the first substrate 201 through the adhesive layer, which can play a positioning role for the wafer 202 and ensure that the wafer is disposed at the correct position.

[0064] In some alternative embodiments, the projection of the heat dissipation structure 203 in the vertical direction falls within the first substrate 201, that is, the heat dissipation structure 203 can be completely disposed above the first substrate 201.

[0065] Reference Figure 4 , Figure 4 is a schematic structural diagram of an embodiment of the heat dissipation structure according to the present application.

[0066] As Figure 4 shown, the heat dissipation structure 203 can be integrally formed. In this way, the heat dissipation structure 203 has no additional welds or joints, which can make its overall structure more solid and not easily deformed or damaged due to thermal expansion and contraction or mechanical vibration, improving the durability and reliability of the heat dissipation structure 203. At the same time, the risk of coolant leakage can also be reduced.

[0067] Above, an embodiment 2a of the packaging structure according to the present application has been introduced.

[0068] Reference Figure 5 , Figure 5 is a schematic structural diagram of a side view of an embodiment 3a of the semiconductor packaging device according to the present application.

[0069] As Figure 5 shown, in some alternative embodiments, the semiconductor packaging device 3a further includes a second substrate 206 disposed on the top surface 2032 of the heat dissipation structure 203.

[0070] Above, an embodiment 3a of the packaging structure according to the present application has been introduced.

[0071] Reference Figure 6 , Figure 6It is a schematic structural diagram of a side view of an embodiment 4a of a semiconductor packaging device according to the present application.

[0072] As Figure 6 shown, the semiconductor packaging device 4a further includes a molding member 205.

[0073] In some alternative embodiments, the molding member 205 is arranged to fill the space between the top surface 2021 of the wafer 202 and the heat dissipation structure 203.

[0074] In some alternative embodiments, the top surface 2021 of the molding member 205 is flush with the top surface 2032 of the heat dissipation structure 203.

[0075] Here, the molding member 205 can be formed of various molding compounds. Exemplarily, the molding compound can be a combination of one or more of epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0076] The molding member 205 is filled in the space formed by the top surface of the wafer 202, the heat dissipation structure 203 and the second substrate 206, which can play a role in fixing and protecting the wafer 202, and can also play a heat conduction role to conduct the heat on the top surface of the wafer 202.

[0077] Above, an embodiment 4a of the packaging structure of the present application has been introduced.

[0078] The manufacturing steps of an embodiment 2a of the semiconductor packaging device of the present application will be described below.

[0079] (1) Fabricate the heat dissipation structure 203.

[0080] Here, the heat dissipation structure 203 can be integrally formed, and the side of the heat dissipation structure is hollowed out to form a heat dissipation channel 2031.

[0081] The heat dissipation channel 2031 can penetrate the heat dissipation structure 203. Among them, the heat dissipation structure 203 can have a plurality of open ends 20311 and a plurality of outlet ends 20312 according to the actual product design of the heat dissipation structure 203.

[0082] The diameters of the open end 20311 and the outlet end 20312 of the heat dissipation channel 2031 are the same. The cooling fluid can flow into the heat dissipation channel 2031 from the open end 20311 and flow out from the outlet end 20312 of the heat dissipation channel 2031.

[0083] Setting the diameters of the open end 20311 and the outlet end 20312 of the heat dissipation channel 2031 to be the same can ensure that the coolant flows more smoothly in the heat dissipation channel, reduce the fluid resistance. At the same time, it can make the heat dissipation around the wafer 202 more uniform, ensuring the stable operation of the heat dissipation structure 203.

[0084] The heat dissipation structure 203 can be made of a non-conductive rigid material to effectively control the total thickness of the overall packaging device, so that it is not affected by the subsequent solder paste printing process and the wafer 202.

[0085] For example, the material of the heat dissipation structure can be aluminum nitride ceramic. Aluminum nitride ceramic is a heat-conducting but non-conductive material. It not only has excellent electrical insulation performance, good heat resistance, but also has excellent heat dissipation ability. It will not cause short circuits due to the mutual flow of current. Moreover, aluminum nitride ceramic can still maintain structural stability at high temperatures.

[0086] (2) Solder paste printing process.

[0087] After the heat dissipation structure 203 is made, solder paste can be printed on the first substrate 201.

[0088] (3) Fix the heat dissipation structure 203 on the first substrate 201.

[0089] Here, the made heat dissipation structure 203 can be fixed on the first substrate 201 through solder paste to provide a positioning effect for the subsequent placement of the wafer 202 and ensure the placement position of the wafer 202.

[0090] (4) Place the wafer 202 on the first substrate 201.

[0091] Here, the wafer 202 can be placed on the first substrate 201. Specifically, solder balls 204 can be provided between the wafer 202 and the first substrate 201 to make the wafer 202 electrically connected to the first substrate 201.

[0092] (5) Complete the production of the semiconductor packaging device.

[0093] Here, the space between the top surface 2021 of the wafer 202 and the heat dissipation structure 203 can be filled with a molding compound 205, and then the second substrate 206 can be set on the top surface 2032 of the heat dissipation structure 203.

[0094] Although the present application has been described and illustrated with reference to specific embodiments thereof, such description and illustration do not limit the present application. Those skilled in the art will clearly understand that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The drawings may not necessarily be drawn to scale. There may be differences between the technical reproduction and the actual implementation in the present application due to variables in the manufacturing process and so on. There may be other embodiments of the present application that are not specifically described. The specification and the drawings should be regarded as illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method, or process to the objectives, spirit, and scope of the present application. All such modifications fall within the scope of the appended claims herein. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered without departing from the teachings of the present application to form equivalent methods. Therefore, unless specifically indicated herein, the order and grouping of the operations do not limit the present application.

Claims

1. A semiconductor packaging device, characterized in that, Comprising: A first substrate; A wafer, arranged to be electrically connected to the first substrate; A heat dissipation structure, made of a non-conductive material, surrounding the circumferential side of the wafer and located on the first substrate, the top surface of the heat dissipation structure being higher than the top surface of the wafer, the heat dissipation structure including heat dissipation channels and a cooling fluid disposed in the heat dissipation channels, the heat dissipation channels penetrating through the heat dissipation structure.

2. The semiconductor packaging device according to claim 1, wherein The heat dissipation structure is arranged along the circumference of the wafer.

3. The semiconductor packaging device according to claim 2, wherein, The heat dissipation channels are conformal with the wafer circumference.

4. The semiconductor packaging device according to claim 1, wherein, The diameters of the open ends and the outlet ends of the heat dissipation channels are the same.

5. The semiconductor packaging device according to claim 1, wherein, The material of the heat dissipation structure is aluminum nitride ceramic.

6. The semiconductor packaging device according to claim 1, wherein, The wafer is electrically connected to the first substrate through solder balls.

7. The semiconductor package device according to claim 1, wherein, The bottom surface of the heat dissipation structure directly contacts the first substrate.

8. The semiconductor packaging device according to claim 1, wherein, It further includes a potting member, arranged to fill the space between the top surface of the wafer and the heat dissipation structure.

9. The semiconductor packaging device according to claim 1, wherein The top surface of the heat dissipation channels is higher than the top surface of the wafer.

10. The semiconductor packaging device according to claim 9, characterized in that, The bottom surface of the heat dissipation channels is lower than the bottom surface of the wafer.

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