Integrated circuit substrate

Abstract

The utility model provides an integrated circuit substrate. The integrated circuit substrate comprises a main circuit area, a to-be-cut area and a forming gate part. The main circuit area is arranged at the central position of the integrated circuit substrate. The to-be-cut area surrounds the main circuit area. The forming gate part comprises a first part arranged in the main circuit area and a second part arranged in the to-be-cut area, wherein the second part comprises a first solder mask layer, a first conductive layer, a second conductive layer and a core layer. The first solder resist layer includes a notch configured to act as a molding gate. The first conductive layer is arranged at the bottom of the gap. The second conductive layer is disposed below the first conductive layer. The core layer is formed in the second conductive layer. According to the integrated circuit substrate provided by the invention, the binding force between the molded gate part and other structures of the substrate can be effectively enhanced, and the binding force between the copper layer and the solder mask layer in the molded gate part is increased.

Description

Technical Field

[0001] This application relates to the field of semiconductors. Specifically, it relates to an integrated circuit substrate. Background Art

[0002] In the ball grid array packaging technology, plastic ball grid array is a relatively inexpensive and fast packaging technology, which can efficiently install semiconductor chips on a printed circuit board. In the existing plastic ball grid array packaging substrate, due to the small contact area between the copper layer of the forming gate part and the solder mask layer, and the copper layer of the forming gate part is not connected to other structures, cracks are likely to occur between the copper layer of the forming gate part and the core layer (such as resin or glass core board) during the cutting of the substrate, thus causing the copper layer to separate and peel off from the core layer, reducing the product yield. Summary of the Utility Model

[0003] In view of this, one of the purposes of this application is to provide an integrated circuit substrate to solve the above problems.

[0004] According to an embodiment of this application, an integrated circuit substrate is provided. The integrated circuit substrate includes: a main circuit area, a cutting area to be cut, and a forming gate part. The main circuit area is disposed at the central position of the integrated circuit substrate. The cutting area to be cut surrounds the main circuit area. The forming gate part includes a first part disposed in the main circuit area and a second part disposed in the cutting area to be cut, wherein the second part includes: a first solder mask layer, a first conductive layer, a second conductive layer, and a core layer. The first solder mask layer includes a notch configured as a forming gate. The first conductive layer is disposed at the bottom of the notch. The second conductive layer is disposed below the first conductive layer. The core layer is formed in the second conductive layer.

[0005] According to an embodiment of this application, the bottom surface of the first solder mask layer and the upper surface of the second conductive layer are coplanar.

[0006] According to an embodiment of this application, the integrated circuit substrate further includes: a plurality of plated vias. The plurality of plated vias penetrate through the second conductive layer and are disposed on both sides of the core layer.

[0007] According to an embodiment of this application, the plated vias are filled with resin material.

[0008] According to an embodiment of this application, the integrated circuit substrate further includes: a second solder mask layer. The second solder mask layer is disposed below the second conductive layer.

[0009] According to an embodiment of this application, the plated vias are connected between the first solder mask layer and the second solder mask layer.

[0010] According to an embodiment of the present application, the formed gate portion is disposed at a corner of the integrated circuit substrate.

[0011] According to an embodiment of the present application, the integrated circuit substrate is a plastic ball grid array (PBGA) package substrate.

[0012] The integrated circuit substrate proposed by the present application can effectively enhance the bonding force between the formed gate portion and other structures of the substrate, increase the bonding force between the copper layer and the solder resist layer in the formed gate portion, increase the bonding force between the copper layer of the formed gate portion and the core layer, reduce the risk of structural detachment of the formed gate portion, and improve the product yield. Description of the Drawings

[0013] The drawings are used to provide a further understanding of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application, but do not constitute a limitation to the present application. In the drawings:

[0014] Figure 1A Demonstration of a partially enlarged schematic view of an integrated circuit substrate according to an embodiment of the present application.

[0015] Figure 1B Demonstration of a cross-sectional view observed along line A-A'.

[0016] Figure 2A Demonstration of a partially enlarged schematic view of an integrated circuit substrate according to another embodiment of the present application.

[0017] Figure 2B Demonstration of a cross-sectional view observed along line B-B'. Detailed Description of the Embodiments

[0018] The following disclosure provides various embodiments or illustrations that can be used to implement different features of the present disclosure. Specific examples of components and configurations described below are used to simplify the present disclosure. It is conceivable that these descriptions are only illustrative and are not intended to limit the present disclosure. For example, in the following description, forming a first feature on or above a second feature may include, in some embodiments, the first and second features being in direct contact with each other; and may also include some embodiments in which additional components are formed between the above first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may reuse component symbols and / or reference numerals in multiple embodiments. Such reuse is for the purpose of simplicity and clarity, and does not itself represent the relationship between different embodiments and / or configurations discussed.

[0019] Furthermore, the use of spatially relative terms herein, such as "under", "below", "lower", "above", "upper" and the like, may be for convenience in describing the relationship of one component or feature shown in the figures to another or other components or features. These spatially relative terms are intended to cover not only the orientation shown in the figures but also various different orientations in which the device may be used or operated. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and these spatially relative descriptive terms should be interpreted accordingly.

[0020] Although the numerical ranges and parameters used to define the broader scope of the present application are approximate values, the relevant values in the specific embodiments have been presented as precisely as possible herein. However, any numerical value inherently and inevitably contains standard deviations due to individual testing methods. Herein, "about" generally means that the actual value is within plus or minus 10%, 5%, 1% or 0.5% of a particular value or range. Alternatively, the term "about" represents that the actual value falls within the acceptable standard error of the mean value, depending on the consideration of those of ordinary skill in the art to which the present application pertains. It will be understood that, except for experimental examples or unless otherwise clearly stated, all ranges, amounts, numerical values and percentages (such as those used to describe material amounts, time lengths, temperatures, operating conditions, quantity ratios and others similar) used herein are modified by "about". Therefore, unless otherwise stated to the contrary, the numerical parameters disclosed in this specification and the appended claims are approximate values and may be varied as required. At least these numerical parameters should be understood as the values indicated by the significant digits and obtained by applying the general rounding method. Herein, a numerical range is expressed as from one endpoint to the other endpoint or between two endpoints; unless otherwise stated, the numerical ranges described herein include the endpoints.

[0021] Figure 1A A partially enlarged schematic view of an integrated circuit substrate 1 according to an embodiment of the present application is shown, wherein Figure 1A is a perspective view of one corner of the integrated circuit substrate 1 observed from a top-down perspective. In some embodiments, the integrated circuit substrate 1 may be a plastic ball grid array package substrate. In other embodiments, the integrated circuit substrate 1 may also be applied to other ball grid array packaging technologies. In some embodiments, the integrated circuit substrate 1 includes a main circuit area 11 and a cutting area 12. The main circuit area 11 is located at the center of the integrated circuit substrate 1, and the cutting area 12 is located around the integrated circuit substrate 1, and the cutting area 12 surrounds the main circuit area 11. A semiconductor chip is mounted on the main circuit area 11.

[0022] In some embodiments, before encapsulating the semiconductor chip, the integrated circuit substrate 1 can be cut along the cutting line L to cut open the main circuit region 11 and the region to be cut 12, and the main circuit region 11 is retained.

[0023] In some embodiments, the integrated circuit substrate 1 further includes a molding gate portion 13. The molding gate portion 13 is configured to provide an injection gate. When encapsulating the semiconductor chip, the mold injects the encapsulant through the molding gate portion 13 to encapsulate the semiconductor chip in the main circuit region 11. In some embodiments, the molding gate portion 13 includes a first portion 131 and a second portion 132, where the first portion is located in the main circuit region 11 and the second portion 132 is located in the region to be cut 12.

[0024] Referring simultaneously to Figure 1B , Figure 1B a cross-sectional view demonstrated according to the observation along line A-A'. In some embodiments, the second portion 132 includes a first solder resist layer 21, a first conductive layer 22, a second conductive layer 23, a core layer 24, and a second solder resist layer 25. In some embodiments, the first solder resist layer 21 includes a notch A21. In some embodiments, the first conductive layer 22 is disposed at the bottom of the notch A21. In some embodiments, there is a height difference between the upper surface of the first conductive layer 22 and the upper surface of the first solder resist layer 21, and this height difference forms an injection gate for the encapsulant to pass through to encapsulate the semiconductor chip.

[0025] In some embodiments, the second conductive layer 23 is disposed below the first solder resist layer 21 and the first conductive layer 22. In some embodiments, the bottom surface of the first solder resist layer 21 and the upper surface of the second conductive layer 23 are coplanar, thereby increasing the contact area between the bottom surface of the first solder resist layer 21 and the upper surface of the second conductive layer 23, and further increasing the bonding force between the first solder resist layer 21 and the second conductive layer 23. In some embodiments, the first conductive layer 22 and the second conductive layer 23 are formed of different materials respectively. For example, the first conductive layer 22 may include gold or an alloy containing gold, and the second conductive layer 23 may include copper or an alloy containing copper. In other embodiments, the first conductive layer 22 and the second conductive layer 23 may also be formed of the same material.

[0026] In some embodiments, the core layer 24 is formed in the second conductive layer 23. In some embodiments, the core layer 24 may include a resin core board or a glass core board. By forming the core layer 24 in the second conductive layer 23, the contact area between the core layer 24 and the second conductive layer 23 is increased, thereby increasing the bonding force between the core layer 24 and the second conductive layer 23.

[0027] In some embodiments, the second conductive layer 23 is disposed above the second solder resist layer 25. It should be noted that the second portion 132 may further include other layers, butFigure 1B Only depict the parts related to the spirit of this application.

[0028] In some embodiments, the width W22 at the widest part of the first conductive layer 22 is approximately 3.34 mm, and the width W23 at the widest part of the second conductive layer 23 is approximately 4.24 mm.

[0029] The integrated circuit substrate 1 proposed in this application can effectively enhance the bonding force between the forming gate portion 13 and other structures in the substrate, increase the bonding force between the second conductive layer 23 and the first solder mask layer 21 in the forming gate portion 13, increase the bonding force between the second conductive layer 23 and the core layer 24 in the forming gate portion 13, reduce the risk of structural detachment of the forming gate portion 13, and improve the product yield.

[0030] Figure 2A Partial enlarged schematic diagram demonstrating the integrated circuit substrate 1' according to another embodiment of this application. It should be noted that the same reference numerals in the integrated circuit substrate 1' and the integrated circuit substrate 1 represent the same components. Therefore, the same parts of the integrated circuit substrate 1' and the integrated circuit substrate 1 will not be described again. The difference between the integrated circuit substrate 1' and the integrated circuit substrate 1 is only that the second part 132' of the forming gate portion 13' further includes a plurality of plating vias 26'. Also refer to Figure 2B , where Figure 2B Demonstrating a cross-sectional view observed along line B-B'. In some embodiments, the plating vias 26' are formed in the second conductive layer 23'. In some embodiments, the plating vias 26' penetrate through the second conductive layer 23' and are disposed on both sides of the core layer 24. In some embodiments, the plating vias 26' are connected between the first solder mask layer 21 and the second solder mask layer 25. In some embodiments, the plating vias 26' are filled with a resin material. In some embodiments, the diameter W26' of the plating vias 26' is approximately 0.2 mm.

[0031] The integrated circuit substrate 1' proposed in this application can effectively enhance the bonding force between the forming gate portion 13' and other structures in the substrate, increase the bonding force between the second conductive layer 23' and the first solder mask layer 21 in the forming gate portion 13', increase the bonding force between the second conductive layer 23' and the core layer 24 in the forming gate portion, reduce the risk of structural detachment of the forming gate portion 13', and improve the product yield.

[0032] As used herein, the terms "approximately", "substantially", "essentially" and "about" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs very nearly. As used herein with respect to a given value or range, the term "about" generally means within ±10%, ±5%, ±1% or ±0.5% of the given value or range. Ranges can be expressed herein as from one endpoint to the other endpoint or between two endpoints. Unless otherwise specified, all ranges disclosed herein include the endpoints. The term "substantially coplanar" can refer to two surfaces that are positioned within a few micrometers (μm) of each other along the same plane, e.g., within 10 μm, within 5 μm, within 1 μm or within 0.5 μm of each other along the same plane. When referring to "substantially" the same numerical value or property, the term can refer to a value that is within ±10%, ±5%, ±1% or ±0.5% of the average of that value.

[0033] As used herein, the terms "approximately", "substantially", "essentially" and "about" are used to describe and account for small variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely as well as instances where the event or circumstance occurs very nearly. For example, when used in connection with a numerical value, the term can refer to a range of variation that is less than or equal to ±10% of that numerical value, e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values is less than or equal to ±10% (e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%) of the average of that value, then the two numerical values can be considered to be "substantially" or "about" the same. For example, "substantially" parallel can refer to a range of angular variation that is less than or equal to ±10° relative to 0°, e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°. For example, "substantially" perpendicular can refer to a range of angular variation that is less than or equal to ±10° relative to 90°, e.g., less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1%, or less than or equal to ±0.05°.

[0034] For example, if the displacement between two surfaces is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm, then the two surfaces can be considered coplanar or substantially coplanar. If the displacement between any two points on a surface relative to a plane is equal to or less than 5 μm, equal to or less than 2 μm, equal to or less than 1 μm, or equal to or less than 0.5 μm, then the surface can be considered planar or substantially planar.

[0035] As used herein, the terms “conductive,” “electrically conductive,” and “conductivity” refer to the ability to transfer current. Conductive materials generally denote those materials that present little or no opposition to the flow of current. A measure of conductivity is Siemens per meter (S / m). Generally, a conductive material is a material having a conductivity greater than approximately 104 S / m (e.g., at least 105 S / m or at least 106 S / m). The conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the conductivity of a material is measured at room temperature.

[0036] As used herein, unless the context clearly dictates otherwise, the singular terms “a / an” and “the” may include plural referents. In the description of some embodiments, a component provided “on” or “above” another component may cover the case where the former component is directly on the latter component (e.g., in physical contact with the latter component), as well as the case where one or more intermediate components are located between the former component and the latter component.

[0037] As used herein, to facilitate description, spatial relative terms such as “below,” “beneath,” “lower,” “above,” “upper,” “under,” “left,” “right,” etc. may be used to describe the relationship of one component or feature to another component or feature as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it can be directly connected or coupled to the other component, or intervening components may be present.

[0038] The foregoing outlines several embodiments and features in detail of the present disclosure. The embodiments described in the present disclosure can be readily used as a basis for designing or modifying other processes and for performing the same or similar purposes and / or obtaining the same or similar advantages as the embodiments introduced herein. These equivalent constructs do not depart from the spirit and scope of the present disclosure and can be made with various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit substrate, characterized in that, Comprising: A main circuit area, disposed at the central position of the integrated circuit substrate; A to-be-cut area, surrounding the main circuit area; And A forming gate portion, including a first portion disposed in the main circuit area and a second portion disposed in the to-be-cut area, wherein the second portion includes: A first solder mask layer, including a notch configured as a forming gate; A first conductive layer, disposed at the bottom of the notch; A second conductive layer, disposed below the first conductive layer; and A core layer, formed within the second conductive layer.

2. The integrated circuit substrate according to claim 1, wherein The bottom surface of the first solder mask layer is coplanar with the upper surface of the second conductive layer.

3. The integrated circuit substrate according to claim 1, wherein Further comprising: A plurality of plated vias, the plurality of plated vias penetrating through the second conductive layer and disposed on both sides of the core layer.

4. The integrated circuit substrate according to claim 3, wherein, The plated vias are filled with a resin material.

5. The integrated circuit substrate according to claim 3, characterized in that, Further comprising: A second solder mask layer, disposed below the second conductive layer.

6. The integrated circuit substrate according to claim 5, wherein, The plated vias are connected between the first solder mask layer and the second solder mask layer.

7. The integrated circuit substrate according to claim 1, wherein The forming gate portion is disposed at the corner of the integrated circuit substrate.

8. The integrated circuit substrate according to claim 1, wherein The integrated circuit substrate is a plastic ball grid array package substrate.

Images