Semiconductor structure
By setting the alignment marks in the first metal layer and the second metal layer, the laser adjustment position offset caused by the alignment error between layers is solved, the adjustment accuracy and stability are improved, and the yield of the semiconductor chip is improved.
Patent Information
- Application Number
- CN202422355133.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-07-18
- Estimated Expiration
- 2034-09-25
AI Technical Summary
On the 0.18um BCD process platform, during the laser fuse production process of the metal layer, the position offset during laser adjustment due to the interlayer alignment error, which affects the adjustment yield.
Alignment marks are provided in both the first metal layer and the second metal layer, and the alignment accuracy is improved and the interlayer alignment deviation is reduced by interlacing arrangement and designing the central distance.
It improves the accuracy and stability of laser adjustment, enhances the reliability of the product, and improves the yield of semiconductor chips.
Smart Images
Figure CN223123907U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of semiconductor structures, and more specifically, to a semiconductor structure with alignment marks. Background Art
[0002] Laser fuse trimming technology has a wide range of applications in the semiconductor industry. Its unique advantages make it an indispensable important technology in the field of modern electronics manufacturing. Currently, in the 0.18um BCD (Bipolar-CMOS-DMOS) process platform, for the laser fuse manufacturing process of the metal layer, the industry generally adopts a specific technical route. This process involves opening a window in the topmost metal layer of the semiconductor, that is, removing the passivation layer or protective layer above the metal layer to be trimmed to expose the metal fuse to be trimmed. At the same time, for the subsequent laser trimming alignment requirements, engineers will also fabricate an L-shaped alignment mark in the scribe area at the upper right corner of the chip on the topmost metal layer through etching process.
[0003] However, due to manufacturing process deviations, especially the interlayer alignment error: there is an alignment error during the manufacturing process between the topmost metal and the metal layer to be trimmed. This deviation will directly affect the accuracy of laser alignment. Even if the L-shaped alignment mark on the topmost metal is fabricated precisely, its actual position relative to the metal fuse on the metal layer to be trimmed may still have a deviation, resulting in a position shift during laser trimming, which may lead to inaccurate alignment during laser trimming, and further cause problems such as trimming position shift and metal explosion and sputtering, affecting the trimming yield. Summary of the Utility Model
[0004] In order to solve the above problems, improve the accuracy and stability of metal laser trimming, and reduce the influence of interlayer alignment deviation on trimming accuracy by optimizing the design and layout of alignment marks, the utility model provides a semiconductor structure. The semiconductor structure has a device area and a scribe area located between the device areas. The semiconductor structure includes:
[0005] A substrate, in the substrate area corresponding to the device area, semiconductor devices are formed;
[0006] A metal layer, the metal layer at least includes a first metal layer and a second metal layer stacked in sequence from the substrate. The first metal layer includes a first scribe area located in the scribe area and a trimming area located in the device area. The second metal layer includes a second scribe area located in the scribe area;
[0007] Alignment marks, including a first alignment mark and a second alignment mark. The first alignment mark is located in the first scribe area, and the second alignment mark is located in the second scribe area.
[0008] Optionally, in the projection on the plane where the substrate surface is located, the first alignment mark and the second alignment mark are staggered.
[0009] Optionally, in the projection on the plane where the substrate is located, the first alignment mark and the second alignment mark are arranged in parallel and spaced apart in the scribing area on the side close to the trimming area, and the first alignment mark is disposed below the second alignment mark.
[0010] Optionally, there is a first distance between the center position of the alignment mark and the boundary of the scribing area on the side close to the trimming area, and a second distance between the geometric center of the alignment mark and the boundary of the scribing area on the side far from the trimming area, and the first distance is less than the second distance.
[0011] Optionally, the first alignment mark and the second alignment mark have the same shape and / or the same size, or the first alignment mark and the second alignment mark have different shapes and / or different sizes.
[0012] Optionally, the first alignment mark and the second alignment mark are any one or two of a T-shaped structure, a cross-shaped structure, and an L-shaped structure.
[0013] Optionally, the width of the alignment mark is greater than or equal to 1 / 2 of the width of the scribing area and less than or equal to 9 / 10 of the width of the scribing area.
[0014] Optionally, the thickness of the first alignment mark is the same as the thickness of the first metal layer, and the thickness of the second alignment mark is the same as the thickness of the second metal layer.
[0015] Optionally, in the substrate projection, the first alignment mark and the second alignment mark are staggered.
[0016] Optionally, it further includes a dielectric layer, and the dielectric layer is located between the first metal layer and the second metal layer.
[0017] Optionally, the semiconductor device includes a combination of one or more of a device layer, a device metal layer, and an insulating layer.
[0018] Compared with the prior art, the beneficial effects of the present utility model include:
[0019] The precision of trimming is improved. First, through the alignment marks on the topmost metal layer, preliminary alignment is performed to quickly determine the approximate trimming position. Then, the alignment marks defined by the metal layer to be trimmed are used for the second alignment, reducing the trimming position offset problem caused by interlayer alignment deviation and improving the precision of laser trimming. The reliability of the product is enhanced. The independently set alignment marks of the trimming metal layer make the laser trimming alignment more direct and stable, reducing the instability during the trimming process. In addition, the design is flexible and can adapt to different types of semiconductor manufacturing processes. It can not only be used for laser trimming but also be extended to other microfabrication fields that require precise alignment. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 It shows a schematic diagram of the semiconductor structure provided by the present invention.
[0021] Figure 2 Shown as Figure 1 A schematic diagram of a top view of the first metal layer in the semiconductor structure shown.
[0022] Figure 3 Shown as Figure 1 A schematic diagram of a top view of the second metal layer in the semiconductor structure shown.
[0023] Figure 4 It shows a schematic diagram of a projection view of the semiconductor structure of the present invention on a substrate.
[0024] REFERENCE NUMERALS
[0025] 1, device area; 2, dicing area.
[0026] 10, substrate; 11, first metal layer; 12, dielectric layer; 13, second metal layer; 14, first alignment mark; 15, trimming area; 16, second alignment mark; 17, PAD window; 21, first dicing area; 22, second dicing area.
[0027] a1, first distance; a2, second distance. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0028] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0029] It should be noted that the illustrations provided in this embodiment only schematically illustrate the basic concept of the present utility model. Although only the components related to the present utility model are shown in the illustrations, rather than being drawn according to the number, shape, and size of the components in actual implementation, the form, quantity, positional relationship, and ratio of each component in actual implementation can be arbitrarily changed on the premise of implementing the technical solution of the present invention, and the component layout form may also be more complex.
[0030] This embodiment provides a semiconductor structure, as Figure 1 shown, which is a schematic diagram of the semiconductor structure provided by the present utility model. The semiconductor structure includes a substrate 10, a first metal layer 11, a second metal layer 13, and alignment marks located on their respective metal layers. The alignment marks include a first alignment mark 14 and a second alignment mark 16. Specifically, as Figure 1 shown, the semiconductor structure includes a device region 1 and a dicing region 2. The dicing region 2 is located in the region between device regions. Along the positive X-axis direction, the left side of the dotted line is the device region 1, and the right side of the dotted line is the dicing region 2. The alignment marks are located in the dicing region 2. The dicing region 2 includes a first dicing region 21 and a second dicing region 22. As Figure 2 shown, which is a top view of the first metal layer 11 in the XY plane. As Figure 2 can be seen, the first metal layer 11 includes a first dicing region 21. The first alignment mark 14 is located in the first dicing region 21. The device region of the first metal layer 11 also includes a trimming region 15. As Figure 3 shown, which is a top view of the second metal layer 13 in the XY plane. As Figure 3 can be seen, the second metal layer 13 includes a second dicing region 22. The second alignment mark 16 is located in the second dicing region 22.
[0031] Specifically, semiconductor devices are formed on the substrate 10. The semiconductor devices may include one or more combinations of a device layer, a device metal layer, an insulating layer, a passivation layer, an interconnect layer, etc. Generally, as Figure 1 shown, the semiconductor structure further includes a dielectric layer 12. The dielectric layer 12 is located between the first metal layer 11 and the second metal layer 13. Generally, the first metal layer 11 and the second metal layer 13 are made of the same material, and the material can be: copper, nickel, stainless steel, aluminum, metal composite materials, etc.; the semiconductor devices can be: transistors (bipolar transistors, field effect transistors), diodes, integrated circuits, and other devices; the material of the dielectric layer 12 can be: SiO2, Al2O3, Si3N4, TiO2, and other insulating materials to isolate the first metal layer 11 and the second metal layer 13 to prevent electrical short circuits.
[0032] Generally, the shapes and sizes of the first alignment mark 14 and the second alignment mark 16 can be designed according to the actual situation. The first alignment mark 14 and the second alignment mark 16 have the same shape and / or the same size, or the first alignment mark 14 and the second alignment mark 16 have different shapes and / or different sizes. Optionally, the shape of the alignment mark can be any one or two of other structures such as a T-shaped structure, a cross-shaped structure, an I-shaped structure, an L-shaped structure, etc. Optionally, the size of the alignment mark can be designed according to the actual situation. Generally, the width of the first alignment mark 14 and the second alignment mark 16 in the X-axis direction is greater than or equal to 1 / 2 of the width of the scribe area 2 and less than or equal to 9 / 10 of the width of the scribe area 2, and the width of the alignment mark in the Y direction is greater than or equal to the width of the alignment mark in the X-axis direction. Generally, the alignment mark penetrates the metal layer where it is located, and the thickness of the alignment mark in the stacking direction of the first metal layer 11 and the second metal layer 13 is the same as the thickness of the metal layer where the alignment mark is located.
[0033] Specifically, as Figure 2 and 3 shown, in this embodiment, the shapes and sizes of the first alignment mark 14 and the second alignment mark 16 are the same, and both are T-shaped. The width of the scribe area 2 in the X-axis direction is 60 μm, the width of the first alignment mark 14 and the second alignment mark 16 in the X-axis direction is less than 50 μm, and the width of the first alignment mark 14 and the second alignment mark 16 in the Y-axis direction is 60 μm. Specifically, the thickness of the first alignment mark 14 is the same as the thickness of the first metal layer 11, and the thickness of the second alignment mark 16 is the same as the thickness of the second metal layer 13.
[0034] As Figure 4 shown, it shows a schematic diagram of the projection of the semiconductor structure of the present invention on the substrate. From Figure 4 it can be seen that on the projection of the substrate 10, the first alignment mark 14 and the second alignment mark 16 are arranged in a staggered manner. Generally, the positions of the first alignment mark 14 and the second alignment mark 16 in the Y-axis direction can be set according to the actual situation. From Figure 4 it can be seen that on the projection of the plane where the substrate is located, the first alignment mark 14 and the second alignment mark 16 are arranged in parallel and spaced in the scribe area 2 of the semiconductor structure, and the alignment marks are located in the scribe area 2 close to the trimming area 15. Further, the geometric center of the alignment mark has a first distance a1 from the boundary of the scribe area 2 close to the trimming area 15, and the geometric center of the alignment mark has a second distance a2 from the boundary of the scribe area 2 far from the trimming area 15. Further, a1 is greater than or equal to 1 / 4 of a2 and less than or equal to 3 / 4 of a2. Further, a1 is greater than 9 / 20 of a2 and less than or equal to 11 / 20 of a2.
[0035] Specifically, in this embodiment, the first distance a1 between the geometric center of the alignment mark and the boundary of the scribing area 2 on the side close to the trimming area 15 is 5 μm, and the second distance a2 between the geometric center of the alignment mark and the boundary of the scribing area 2 on the side far from the trimming area 15 is 10 μm. Moreover, the first alignment mark 14 and the second alignment mark 16 are staggered in the stacking direction of the first metal layer 11 and the second metal layer 13. In this embodiment, the first alignment mark 14 and the second alignment mark 16 are staggered in the Z-axis direction. In the XY plane, the first alignment mark 14 and the second alignment mark 16 can be arranged horizontally or vertically. In this embodiment, in the Y-axis direction, the first alignment mark 14 is above the second alignment mark 16.
[0036] In the prior art, alignment marks are only provided on the second metal layer 13. When laser repairing the trimming area 15 on the first metal layer 11, alignment is only performed relying on the second alignment mark 16 on the second metal layer 13. Due to the layer spacing between the first metal layer 11 and the second metal layer 13, the trimming position is offset. The semiconductor structure provided by the present utility model has alignment marks provided on both the first metal layer 11 and the second metal layer 13. When laser repairing the trimming area 15 in the first metal layer 11, as Figure 3 shown, first, rough alignment is performed using the second alignment mark 16 in the second metal layer 13 to quickly determine the approximate trimming position. Then, as Figure 4 shown, fine alignment is performed using the first alignment mark 14 of the first metal layer 11, which can effectively improve the alignment accuracy and reduce the trimming error caused by misalignment due to the layer spacing.
[0037] Secondly, the thicknesses of the first alignment mark 14 and the second alignment mark 16 are the same as the thicknesses of the corresponding metal layers, so the alignment accuracy is higher. In addition, when the semiconductor structure provided by the present utility model performs the PAD window opening 17 process step, the accuracy of the PAD window 17 can be improved, providing accuracy and reliability for the subsequent packaging process. In summary, the semiconductor structure provided by the present utility model can effectively improve the accuracy and stability during laser trimming alignment, and further effectively improve the yield of semiconductor chip products.
[0038] The above embodiments are only illustrative of the principles and effects of the present utility model, and are not used to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present utility model should still be covered by the claims of the present utility model.
Claims
1. A semiconductor structure having a device region and a dicing region located between the device regions, characterized in that, The semiconductor structure includes: a substrate, a semiconductor device being formed in a substrate region corresponding to the device region; a metal layer, the metal layer at least including a first metal layer and a second metal layer stacked in sequence from the substrate, the first metal layer including a first scribe region located in the scribe region and a trimming region located in the device region, and the second metal layer including a second scribe region located in the scribe region; alignment marks, including a first alignment mark and a second alignment mark, the first alignment mark being located in the first scribe region, and the second alignment mark being located in the second scribe region.
2. The semiconductor structure according to claim 1, wherein In a projection on a plane where the substrate surface is located, the first alignment mark and the second alignment mark are staggered.
3. The semiconductor structure according to claim 2, wherein In a plane projection where the substrate surface is located, the first alignment mark and the second alignment mark are arranged in parallel and spaced apart in the scribe region on a side close to the trimming region, and the first alignment mark is disposed below the second alignment mark.
4. The semiconductor structure according to claim 3, wherein, A first distance exists between the geometric center of the alignment mark and the boundary of the scribe region on a side close to the trimming region, and a second distance exists between the geometric center of the alignment mark and the boundary of the scribe region on a side far from the trimming region, and the first distance is less than the second distance.
5. The semiconductor structure according to claim 1, wherein The first alignment mark and the second alignment mark have the same shape and / or the same size, or the first alignment mark and the second alignment mark have different shapes and / or different sizes.
6. The semiconductor structure according to claim 5, wherein The first alignment mark and the second alignment mark are any one or two of a T-shaped structure, a cross-shaped structure, and an L-shaped structure.
7. The semiconductor structure according to claim 5, wherein The width of the alignment mark is greater than or equal to 1 / 2 of the width of the scribe region and less than or equal to 9 / 10 of the width of the scribe region.
8. The semiconductor structure according to claim 1, wherein The thickness of the first alignment mark is the same as the thickness of the first metal layer, and the thickness of the second alignment mark is the same as the thickness of the second metal layer.
9. The semiconductor structure according to claim 1, wherein It further includes a dielectric layer, and the dielectric layer is located between the first metal layer and the second metal layer.
10. The semiconductor structure according to claim 9, wherein, The semiconductor device includes a combination of one or more of a device layer, a device metal layer, and an insulating layer.