Semiconductor packaging structure

Abstract

The utility model discloses a semiconductor packaging structure. The semiconductor packaging structure comprises a bridging pipe core; a plurality of electronic elements located above the bridging die and communicating with each other through the bridging die; wherein the plurality of electronic components includes a first electronic component, a second electronic component, and a third electronic component, the second electronic component and the third electronic component are located on opposite sides of the first electronic component in the first direction at a depression angle in a plan view, and the second electronic component and the third electronic component are not aligned in the first direction, the bridging die provides a first transmission path through which the second electronic component and the third electronic component communicate with each other. According to the technical scheme, at least the number of the bridging pipe cores used in the semiconductor packaging structure can be reduced, and the problems of offset between the pipe cores and the like caused by the fact that a large number of bridging pipe cores are used are avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to a semiconductor packaging structure. Background Art

[0002] Reference Figure 1A , in the existing semiconductor packaging structure 10, the semiconductor packaging structure 10 can be a FOCoS (Fan-Out Chip on Substrate)-B (Bridge) structure. The semiconductor packaging structure 10 includes a plurality of dies 12, a bridge die 22 located below the plurality of dies 12, and an RDL (Redistribution Layer) 18 located between the plurality of dies 12 and the bridge die 22. The plurality of dies 12 mainly communicate and transmit through the bridge die 22. Figure 1B Shows a top view layout of a plurality of dies and a bridge die in the existing semiconductor packaging structure. Reference Figure 1B As shown, the plurality of dies located above the bridge die 22 include an ASIC (Application Specific Integrated Circuit) die 12A and an HBM (High Bandwidth Memory) die 12B. The ASIC die 12A communicates with the HBM die 12B mainly through the bridge die 22 for communication and transmission. A single bridge die 22 is only used for communication and transmission between two adjacent dies. Therefore, the number of bridge dies 22 must depend on the number of HBM dies 12B. When the number of HBM dies 12B increases, more bridge dies 22 are required. When the number of HBM dies 12B increases, it is also necessary to consider that the shift behavior of each bridge die 22 among the plurality of bridge dies 22 will affect the subsequent RDL alignment and cause wiring difficulties.

[0003] On the other hand, reference Figure 2 As shown, although the general 2.5D stacking structure 20 uses a bridge interposer 24 as a communication bridge between the dies 12 and the dies 12, however, when the bridge interposer 24 is used for communication among a relatively large number of dies 12, it will also increase the wiring difficulty of the RDL lines on the bridge interposer 24 and lead to a reduction in yield. Summary of the Utility Model

[0004] In view of the above problems, this application proposes a semiconductor packaging structure, which can reduce the number of bridge dies used in the semiconductor packaging structure and avoid problems such as die shift caused by using a relatively large number of bridge dies.

[0005] The technical solution of this application is realized as follows:

[0006] According to one aspect of the present application, a semiconductor package structure is provided. The semiconductor package structure may include: a bridge die; a plurality of electronic components located above the bridge die and communicating with each other through the bridge die; wherein, the plurality of electronic components include a first electronic component, a second electronic component, and a third electronic component. In a top-down view, the second electronic component and the third electronic component are located on opposite sides of the first electronic component in a first direction, and the second electronic component and the third electronic component are not aligned in the first direction. The bridge die provides a first transmission path for the second electronic component and the third electronic component to communicate with each other.

[0007] In some embodiments, in a top-down view, the second electronic component is adjacent to a first corner of the bridge die, and the third electronic component is adjacent to a second corner of the bridge die. The first corner and the second corner are opposite corners.

[0008] In some embodiments, in a top-down view, the bridge die straddles the first electronic component, and the first transmission path straddles the first electronic component.

[0009] In some embodiments, the plurality of electronic components further include a fourth electronic component. In a top-down view, the fourth electronic component is aligned with the second electronic component in a second direction perpendicular to the first direction. The bridge die further provides a second transmission path for the fourth electronic component and the second electronic component to communicate with each other.

[0010] In some embodiments, the fourth electronic component and the second electronic component are arranged along the same edge of the first electronic component.

[0011] In some embodiments, the bridge die includes active functional circuits for controlling a plurality of transmission paths for communication between the plurality of electronic components.

[0012] In some embodiments, in a top-down view, the bridge die at least partially overlaps with each of the plurality of electronic components.

[0013] In some embodiments, the bridge die further provides a third transmission path for the third electronic component and the fourth electronic component to communicate with each other.

[0014] In some embodiments, the plurality of electronic components further include a fifth electronic component. In a top-down view, the fifth electronic component and the second electronic component are located on opposite sides of the first electronic component in the first direction, and the fifth electronic component and the second electronic component are aligned in the first direction. The bridge die further provides a fourth transmission path for the fifth electronic component and the second electronic component to communicate with each other.

[0015] In some embodiments, the bridge die provides a transmission path for any two of the first electronic component to the fifth electronic component to communicate with each other.

[0016] In the above technical solution, by using a single bridge die to achieve communication between multiple electronic components, the number of bridge dies used in the semiconductor packaging structure can be reduced, thereby avoiding problems such as die offset that may be caused by using a larger number of bridge dies. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0018] Figure 1A and Figure 1B are respectively a cross-sectional view and a top view of an existing semiconductor packaging structure.

[0019] Figure 2 is a cross-sectional view of an existing 2.5D stacked structure.

[0020] Figure 3A is a cross-sectional view of a semiconductor packaging structure according to an embodiment of the present application.

[0021] Figure 3B are respectively top views of the semiconductor packaging structure according to the embodiments of the present application.

[0022] Figures 4A to 4Q is a cross-sectional view at multiple stages of a method for forming the semiconductor packaging structure according to the embodiment of the present application.

[0023] Figure 5 is a cross-sectional view of a semiconductor packaging structure according to another embodiment of the present application.

[0024] Figure 6 is a cross-sectional view of a semiconductor packaging structure according to still another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0026] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present utility model. Of course, these are merely examples and are not intended to limit the present utility model. For example, in the following description, forming the first component above or on the second component may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where additional components are formed between the first component and the second component such that the first component and the second component may not be in direct contact. Moreover, the present utility model may repeat reference numerals and / or letters in various examples. Such repetition is only for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0027] In addition, without conflict, the embodiments in this application and the features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0028] An embodiment of the present application provides a semiconductor package structure. Figure 3A is a cross-sectional schematic diagram of a semiconductor package structure 100 according to an embodiment of the present application. Referring to Figure 3A , the semiconductor package structure 100 may include a bridge die 110, and a plurality of electronic components 130 located above the bridge die 110. The bridge die 110 may be encapsulated by a first molding layer 181. The plurality of electronic components 130 may be encapsulated by a second molding layer 182. The plurality of electronic components 130 may communicate with each other through the bridge die 110. By using a single bridge die 110 to achieve communication between the plurality of electronic components 130, the number of bridge dies used in the semiconductor package structure 100 can be reduced, thereby avoiding problems such as die-to-die misalignment that may be caused by using a larger number of bridge dies, and making the process control easier.

[0029] In some embodiments, the plurality of electronic components 130 may include an ASIC, for example, may include any one of a CPU (Central Processing Unit), an NPU (Neural Processing Unit), and an FPGA (Field Programmable Gate Array). In some embodiments, the plurality of electronic components 130 may further include an NVM (non-volatile memory).

[0030] Figure 3B are respectively top view schematic diagrams of the semiconductor package structure 100 according to an embodiment of the present application. It should be understood that for clarity of illustration, Figure 3BOnly the layout of a plurality of electronic components 130 and the bridge die 110 in a top view is mainly shown. Specifically, referring to Figure 3B as shown, the plurality of electronic components 130 may include a first electronic component 130A, a second electronic component 130B, and a third electronic component 130C. In Figure 3B the top view, the second electronic component 130B and the third electronic component 130C are located on opposite sides of the first electronic component 130A in the first direction X, and the second electronic component 130B and the third electronic component 130C are not aligned in the first direction X. It should be understood that not being aligned means not overlapping in the first direction, that is, the second electronic component 130B and the third electronic component 130C do not overlap in the first direction X.

[0031] The second electronic component 130B may be adjacent to the first corner A1 of the bridge die 110. The bridge die 110 also has a second corner A2 that is the opposite corner to the first corner A1. The third electronic component 130C may be adjacent to the second corner A2 of the bridge die 110. The bridge die 110 may span the first electronic component 130A. Moreover, the first corner A1 of the bridge die 110 may overlap with the second electronic component 130B in the direction Z, and the second corner A2 of the bridge die 110 may overlap with the third electronic component 130C in the direction Z.

[0032] The bridge die 110 may be used to provide a first transmission path P1 for the second electronic component 130B and the third electronic component 130C to communicate with each other. The first transmission path P1 may span the first electronic component 130A to provide a communication transmission between the second electronic component 130B and the third electronic component 130C.

[0033] In addition, the plurality of electronic components 130 may further include a fourth electronic component 130D, and the fourth electronic component 130D is aligned with the second electronic component 130B in a second direction Y perpendicular to the first direction X. The fourth electronic component 130D and the second electronic component 130B are arranged along the same edge 131 of the first electronic component 130A that extends in the second direction Y. The bridge die 110 may also provide a second transmission path P2 for the fourth electronic component 130D and the second electronic component 130B to communicate with each other.

[0034] The third electronic component 130C and the fourth electronic component 130D may be aligned in the first direction X. The bridge die 110 may also provide a third transmission path P3 for the third electronic component 130C and the fourth electronic component 130D to communicate with each other.

[0035] In some embodiments, the plurality of electronic components 130 may further include a fifth electronic component 130E. The fifth electronic component 130E and the second electronic component 130B are located on opposite sides of the first electronic component 130A in the first direction X, and the fifth electronic component 130E and the second electronic component 130B may be aligned in the first direction X. The third electronic component 130C and the fifth electronic component 130E are disposed along another edge 132 of the first electronic component 130A extending in the second direction Y. The bridge die 110 may further provide a fourth transmission path P4 for the fifth electronic component 130E and the second electronic component 130B to communicate with each other.

[0036] The second electronic component 130B, the third electronic component 130C, the fourth electronic component 130D, and the fifth electronic component 130E are respectively located on opposite sides of the first electronic component 130A and are respectively adjacent to four corners of the bridge die 110. The bridge die 110 at least partially overlaps with the first electronic component 130A to the fifth electronic component 130E among the plurality of electronic components 130. Specifically, the bridge die 110 may span across the first electronic component 130A, and the four corners of the bridge die 110 may respectively overlap with the second electronic component 130B, the third electronic component 130C, the fourth electronic component 130D, and the fifth electronic component 130E.

[0037] The bridge die 110 may provide a transmission path for any two of the first electronic component 130A to the fifth electronic component 130E to communicate with each other. Specifically, the bridge die 110 may provide a transmission path for any two adjacent ones of the first electronic component 130A to the fifth electronic component 130E to communicate. For example, the bridge die 110 may provide transmission paths P5a, P5b, P5c, P5d between the first electronic component 130A and each adjacent second electronic component 130B to the fifth electronic component 130E, provide a second transmission path P2 between the second electronic component 130B and the fourth electronic component 130D adjacent to each other in the second direction Y beside the edge 131 of the first electronic component 130A, and provide a transmission path between the third electronic component 130C and the fifth electronic component 130E adjacent to each other in the second direction Y beside another edge 132 of the first electronic component 130A ( Figure 3B(not shown in the figure). The bridge die 110 can also provide a transmission path for communication between any two non-adjacent ones of the first electronic component 130A to the fifth electronic component 130E. For example, the bridge die 110 can provide a third transmission path P3 between the third electronic component 130C and the fourth electronic component 130D that are aligned in the first direction X on the opposite side of the first electronic component 130A, and provide a fourth transmission path P4 between the second electronic component 130B and the fifth electronic component 130E. As another example, the bridge die 110 can provide a first transmission path P1 between the second electronic component 130B and the third electronic component 130C at the diagonal position of the first electronic component 130A, and provide a transmission path between the fourth electronic component 130D and the fifth electronic component 130E ( Figure 3B (not shown in the figure). It should be understood that Figure 3B the specific routing of each transmission path shown in the figure is only schematic and is used to illustrate the die for transmission path communication.

[0038] In some embodiments, the bridge die 110 can include active functional circuits for controlling multiple transmission paths for communication between multiple electronic components 130. Since the bridge die 110 is used to provide communication transmission between any two of the multiple electronic components 130, the bridge die 110 including active functional circuits can achieve control of each transmission path, can provide better electrical performance, and can introduce fewer packaging formation factors.

[0039] Returning to the reference Figure 3A , the semiconductor package structure 100 can also include an RDL 160, which is located above the bridge die 110 and below the multiple electronic components 130. The multiple electronic components 130 can be connected to the RDL 160 through conductive connectors 137. The conductive connectors 137 of each electronic component 130 are respectively coated with corresponding underfills 188. The bridge die 110 can be connected to the multiple electronic components 130 via the RDL 160. As described above, since the number of bridge dies in the semiconductor package structure 100 is reduced, the problem of die-to-die misalignment caused by a large number of bridge dies is avoided, so the problem of difficult RDL wiring is avoided, and the RDL yield is improved.

[0040] The semiconductor package structure 100 may further include an interposer 220, which is located below the RDL 160. The interposer 220 may include a first encapsulation layer 181 and conductive vias 221 passing through the first encapsulation layer. The bridge die 110 is embedded in the interposer 220 and encapsulated by the first encapsulation layer 181. Another RDL 170 may be disposed below the interposer 220, and the RDL 170 is connected to the substrate 900 through an electrical connector 192. By integrating the bridge die 110 into the interposer 220, the interposer 220 has a bridging function and an active function.

[0041] According to the simulation verification results, the semiconductor package structure 100 provided in this application does not exacerbate the heat dissipation problem of the product compared with the semiconductor package structure in the prior art. For the semiconductor package structure 100 and Figure 2 the 2.5D stacked structure 20 in are simulated and verified. According to the simulation verification results, the semiconductor package structure 100 provided in this application does not cause the temperature of the product to increase too much.

[0042] An embodiment of this application also provides a method for forming a semiconductor package structure. Figures 4A to 4Q is a cross-sectional schematic view of the method for forming the semiconductor package structure of the embodiment of this application at multiple stages.

[0043] First, refer to Figure 4A as shown, a first carrier 801 is provided. A release layer may be coated on the first carrier 801. The release layer may be, for example, a thermal release layer for removing the first carrier 801 after being heated. In some embodiments, the first carrier 801 may be a glass carrier.

[0044] Refer to Figure 4B as shown, a PI (Polyimide) layer 804 is formed on the first carrier 801, for example, by a sputtering process.

[0045] Refer to Figure 4C as shown, a plurality of conductive vias 221 are formed on the first carrier 801 and the PI layer 804. The material of the conductive vias 221 may be a conductive material such as copper.

[0046] Refer to Figure 4D as shown, the bridge die 110 is placed on the first carrier 801 through an attachment layer 119. At this time, the active surface 110F of the bridge die 110 faces away from the first carrier 801. Conductive bumps 115 are provided on the active surface 110F of the bridge die 110.

[0047] Refer to Figure 4EAs shown, a plurality of conductive posts 221 and a bridge connecting die 110 are encapsulated with molding compound to form a first encapsulation layer 181. Then, a grinding process can be performed to make the top surfaces of the first encapsulation layer 181, the plurality of conductive posts 221, and the conductive bumps 115 of the bridge connecting die 110 flush.

[0048] Reference Figure 4F As shown, an RDL 160 is formed on the first encapsulation layer 181. As an example, Figure 4F it is shown in that the RDL 160 includes a layer of dielectric layer 162 and a layer of conductive lines 164 located in the dielectric layer 162. A plurality of pads 166 connected to the conductive lines 164 are also formed on the surface of the RDL 160.

[0049] Reference Figure 4G As shown, a plurality of electronic components 130 are bonded to the pads 166. Specifically, each active surface 130F of the electronic component 130 has a conductive bump 135, and the conductive bump 135 is bonded to the plurality of pads 166 through solder 169. The conductive bump 135, the solder 169, and the pads 166 can be collectively referred to as a conductive connection member 137. After bonding the plurality of electronic components 130, an underfill 188 covering the conductive connection member 137 of each electronic component 130 is formed.

[0050] Reference Figure 4H As shown, a second encapsulation layer 182 covering the plurality of electronic components 130 and the underfill 188 is formed of molding compound.

[0051] Reference Figure 4I As shown, a second carrier plate 802 is attached to the second encapsulation layer 182 through an attachment layer 810.

[0052] Reference Figure 4J As shown, remove Figure 4I the first carrier plate 801 and the PI layer 804 in.

[0053] Reference Figure 4K As shown, another RDL 170 is formed under the first encapsulation layer 181. The RDL 170 may include a dielectric layer 172 and an under-bump metal 174 connected to the corresponding conductive post 221.

[0054] Reference Figure 4L As shown, an electrical connection member 192 connected to the under-bump metal 174 is formed. In some embodiments, the electrical connection member 192 may be solder, such as a C4 bump.

[0055] Reference Figure 4M As shown, a protective tape 821 is formed under the first encapsulation layer 181 and the electrical connection member 192.

[0056] Reference Figure 4N As shown, removeFigure 4M the second carrier plate 802 and the attachment layer 810 therein.

[0057] Reference Figure 4O As shown, for example, by a grinding process, the top surface of the second encapsulation layer 182 is made flush with the top surfaces of the respective electronic components 130.

[0058] Reference Figure 4P As shown, a tape 824 is formed on the top surface of the second encapsulation layer 182 and the top surfaces of the respective electronic components 130. Also, the protective tape 821 under the first encapsulation layer 181 and the electrical connection member 192 is removed (see Figure 4O ).

[0059] Reference Figure 4Q As shown, then a singulation process can be performed, and then the tape 824 is removed (see Figure 4P ). Then the resulting structure is bonded to the substrate 900 through the electrical connection member 192. In this way, the final semiconductor package structure 200 is obtained. The semiconductor package structure 200 is similar to that described in the above references Figure 3A and Figure 3B , except that the number of electronic components 130 in the semiconductor package structure 200 is different from the number of electronic components 130 in the semiconductor package structure 100.

[0060] Figure 5 is a cross-sectional schematic view of a semiconductor package structure 300 according to another embodiment of the present application. Figure 5 Multiple aspects of the semiconductor package structure 300 shown can be similar to those of the semiconductor package structure 100 described in the above references Figure 3A and Figure 3B , except that each conductive connection member 137 between the multiple electronic components 130 and the RDL 160 can be covered by the same underfill 188.

[0061] Figure 6 is a cross-sectional schematic view of a semiconductor package structure 400 according to still another embodiment of the present application. Reference Figure 6 As shown, similar to the above semiconductor package structure 100, multiple electronic components 130 are located above the bridge die 110. The multiple electronic components 130 communicate with each other through the bridge die 110. The RDL 160 is located between the bridge die 110 and the multiple electronic components 130. The difference is that the bridge die 110 and at least one of the multiple electronic components 130 do not overlap in the Z direction.

[0062] In addition, the interposer layer 220 is horizontally disposed beside the bridge die 110. The bridge die 110 is not embedded in the interposer layer 220, but is horizontally spaced apart from the interposer layer 220. The interposer layer 220, the bridge die 110, the RDL 160, and the plurality of electronic components 130 may be encapsulated by the same molding layer 180.

[0063] In summary, the embodiments of the present application can achieve communication between multiple electronic components by using a single bridge die, which can reduce the number of bridge dies used in the semiconductor packaging structure, thereby avoiding problems such as die offset that may be caused by using a larger number of bridge dies. Therefore, the problem of difficult RDL routing can be avoided, and the RDL yield can be improved. Moreover, the semiconductor packaging structure provided by the present application does not cause excessive temperature increase of the product.

[0064] The foregoing are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor package structure, characterized in that, Comprising: A bridge pipe core; A plurality of electronic components, located above the bridge pipe core and communicating with each other through the bridge pipe core; Wherein, the plurality of electronic components include a first electronic component, a second electronic component, and a third electronic component. In a top-down view, the second electronic component and the third electronic component are located on opposite sides of the first electronic component in a first direction, and the second electronic component and the third electronic component are not aligned in the first direction. The bridge pipe core provides a first transmission path for the second electronic component and the third electronic component to communicate with each other.

2. The semiconductor package structure according to claim 1, wherein In a top-down view, the second electronic component is adjacent to a first corner of the bridge pipe core, and the third electronic component is adjacent to a second corner of the bridge pipe core. The first corner and the second corner are opposite corners.

3. The semiconductor package structure according to claim 1, wherein In a top-down view, the bridge pipe core straddles the first electronic component, and the first transmission path straddles the first electronic component.

4. The semiconductor package structure according to claim 1, wherein The plurality of electronic components further includes a fourth electronic component, In a top-down view, the fourth electronic component is aligned with the second electronic component in a second direction perpendicular to the first direction. The bridge pipe core also provides a second transmission path for the fourth electronic component and the second electronic component to communicate with each other.

5. The semiconductor package structure according to claim 4, wherein The fourth electronic component and the second electronic component are arranged along the same edge of the first electronic component.

6. The semiconductor package structure according to claim 1, wherein The bridge pipe core includes active functional circuits for controlling a plurality of transmission paths for communication between the plurality of electronic components.

7. The semiconductor package structure according to claim 1, wherein In a top-down view, the bridge pipe core at least partially overlaps with each of the plurality of electronic components.

8. The semiconductor package structure according to claim 4, wherein The bridge pipe core also provides a third transmission path for the third electronic component and the fourth electronic component to communicate with each other.

9. The semiconductor package structure according to claim 4, wherein The plurality of electronic components further includes a fifth electronic component, In a top-down view, the fifth electronic component and the second electronic component are located on opposite sides of the first electronic component in the first direction, and the fifth electronic component and the second electronic component are aligned in the first direction, The bridge pipe core also provides a fourth transmission path for the fifth electronic component and the second electronic component to communicate with each other.

10. The semiconductor package structure according to claim 9, wherein The bridge pipe core provides a transmission path for any two of the first electronic component to the fifth electronic component to communicate with each other.

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