Power access circuit and electronic equipment thereof

Abstract

The utility model provides a power supply access circuit and an electronic device thereof, and relates to the technical field of power supply access, the power supply access circuit is characterized in that a two-stage MOS tube control and resistor combined circuit is serially connected to the circuit, a resistor is used to limit current to charge an input capacitor, a group of RC is made to delay the on-off of a first-stage switch MOS, and the on-off of a second-stage switch MOS is delayed; a secondary power MOS (namely a main loop series connection MOS) is controlled through conduction of a primary switch MOS, the primary switch MOS is not in a main loop, so that the risk of burnout is avoided due to no current load, and the secondary power MOS is directly opened when a rear-end capacitor is almost fully charged, so that the secondary power MOS is not in a low Vg opening state for a long time. Therefore, the risk of burning the secondary MOS is avoided.

Description

Technical Field

[0001] The utility model relates to the technical field of power access, and particularly relates to a power access circuit and an electronic device thereof. Background Art

[0002] Currently, with the development of industry, more and more electronic products are flooding the market. However, even so, the products on the market are still of uneven quality. In particular, many products need to set large input capacitors on the main power loop for some needs. However, the existence of such capacitors may cause extremely large input inrush current and sparks during insertion when the power supply device is connected.

[0003] Specifically, there are many solutions for preventing inrush current in the current market. There are three commonly used solutions, but the defects are relatively obvious. They are: First, a thermistor is connected in series, but this solution increases current consumption and is not conducive to the device's demand for instantaneous current; Second, a MOS tube buffer circuit is directly connected in series in the main circuit. The principle is to make the Vgs of the inserted MOS tube increase slowly. When the Vgs of the MOS tube is small, Rds is large, so as to suppress large current. However, since the power of a general MOS tube is limited, it is easy to burn out the MOS tube when the capacitance at the back end is large; Third, a solution of connecting a resistor in parallel with the MOS tube on the basis of the second solution. The resistor and the MOS are used to charge the back-end capacitor together to alleviate the problem of excessive power consumption and burnout of the MOS tube. However, since the slowly turned-on MOS tube is directly connected in series in the power loop, the drawbacks existing in the second solution still cannot be completely solved, and the MOS tube is burned out.

[0004] In view of this, this application is proposed. Summary of the Utility Model

[0005] The utility model provides a power access circuit and an electronic device thereof, which can at least partially improve the above problems.

[0006] To achieve the above object, the utility model adopts the following technical solutions:

[0007] A power access circuit includes: a power access module, a delay circuit, a switching tube, a power switching tube, a charging power resistor, a back-end capacitor, and a fourth resistor;

[0008] Among them, the power supply access module is used to connect to a DC power supply. The input end of the power switch tube and the first end of the charging power resistor are simultaneously connected to the first output end of the power supply access module. The output end of the power switch tube and the second end of the charging power resistor are simultaneously connected to the first end of the backend capacitor. The second end of the backend capacitor is connected to the second output end of the power supply access module. The control end of the power switch tube is connected to the first output end of the power supply access module through the fourth resistor and is connected to the second output end of the power supply access module through the switch tube. The control end of the switch tube is connected to the first output end of the power supply access module through the delay circuit, and the delay circuit is configured to control the switch tube to conduct after a preset time delay after the power supply access module is connected to the DC power supply.

[0009] Preferably, the delay circuit includes a second resistor, a third resistor, and a first capacitor. Among them, one end of the second resistor is electrically connected to the first output end of the power supply access module. The other end of the second resistor is electrically connected to one end of the third resistor, one end of the first capacitor, and the control end of the switch tube. The other end of the third resistor and the other end of the first capacitor are electrically connected to the second output end of the power supply access module.

[0010] Preferably, the switch tube is an NMOS transistor.

[0011] Preferably, the control end of the switch tube is the gate of the NMOS transistor, the first end of the switch tube is the source of the NMOS transistor, and the second end of the switch tube is the drain of the NMOS transistor.

[0012] Preferably, the power switch tube is a PMOS transistor.

[0013] Preferably, the control end of the power switch tube is the gate of the PMOS transistor, the first end of the power switch tube is the drain of the PMOS transistor, and the second end of the power switch tube is the source of the PMOS transistor.

[0014] Preferably, it further includes a fifth resistor. The control end of the power switch tube is connected to the first end of the switch tube through the fifth resistor, and the first end of the switch tube is connected to the second output end of the power supply access module.

[0015] The present invention also provides an electronic device, including a power supply access circuit as described in any one of the above.

[0016] In summary, the power access circuit uses a circuit combining two-stage MOS transistor control and resistors in series. First, a resistor is used to limit the current to charge the input capacitor, and at the same time, a set of RC delays is used to turn on the first-stage switch MOS. Then, the conduction of the first-stage switch MOS is used to control the second-stage power MOS (i.e., the main circuit series MOS). Since the first-stage switch MOS is not in the main circuit, there is no current load and thus no risk of burning. The second-stage power MOS is directly turned on when the capacitor at the back end is almost fully charged, without a long-term low Vg turn-on state, so there is no risk of burning the second MOS either. Brief Description of the Drawings

[0017] Figure 1 It is a circuit schematic diagram of a power access circuit provided by an embodiment of the present invention. Detailed Embodiment

[0018] To make the purpose, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the present invention to be protected, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0019] The following will give a detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

[0020] Please refer to Figure 1 , the present invention discloses a power access circuit, including: a power access module CN1, a delay circuit, a switching transistor Q1, a power switching transistor Q2, a charging power resistor R1, a back-end capacitor C2, and a fourth resistor R4;

[0021] Among them, the power supply access module CN1 is used to connect to the DC power supply VSS. The input end of the power switch tube Q2 and the first end of the charging power resistor R1 are simultaneously connected to the first output end of the power supply access module CN1. The output end of the power switch tube Q2 and the second end of the charging power resistor R1 are simultaneously connected to the first end of the backend capacitor C2. The second end of the backend capacitor C2 is connected to the second output end of the power supply access module CN1. The control end of the power switch tube Q2 is connected to the first output end of the power supply access module CN1 through the fourth resistor R4 and is connected to the second output end of the power supply access module CN1 through the switch tube Q1. The control end of the switch tube Q1 is connected to the first output end of the power supply access module CN1 through the delay circuit, and the delay circuit is configured to control the switch tube Q1 to conduct after a preset time delay after the power supply access module CN1 is connected to the DC power supply.

[0022] In this embodiment, the power supply access circuit uses a circuit combining two-stage MOS tube control and resistors in series into the circuit. First, a resistor is used to limit the current to charge the input capacitor, and at the same time, a set of RC delays the opening of the first-stage switch MOS. Then, the conduction of the first-stage switch MOS is used to control the second-stage power MOS (i.e., the main circuit series MOS). Since the first-stage switch MOS is not in the main circuit, there is no current load and thus no risk of burning. And the second-stage power MOS is directly turned on when the backend capacitor is almost fully charged, without a long-term low Vg turn-on state, so there is no risk of burning the second-stage MOS.

[0023] Preferably, the delay circuit includes a second resistor R2, a third resistor R3, and a first capacitor C1. Among them, one end of the second resistor R2 is electrically connected to the output end of the power supply access module CN1, and the other end of the second resistor R2 is electrically connected to one end of the third resistor R3, one end of the first capacitor C1, and the control end of the switch tube Q1. The other end of the third resistor R3 and the other end of the first capacitor C1 are electrically connected to the second output end of the power supply access module CN1.

[0024] Preferably, the switch tube is an NMOS tube.

[0025] Preferably, the control end of the switch tube is the gate of the NMOS tube, the first end of the switch tube is the source of the NMOS tube, and the second end of the switch tube is the drain of the NMOS tube.

[0026] Preferably, the power switch tube is a PMOS tube.

[0027] Preferably, the control terminal of the power switch tube is the gate of the PMOS tube, the first terminal of the power switch tube is the drain of the PMOS tube, and the second terminal of the power switch tube is the source of the PMOS tube.

[0028] Preferably, it further includes a fifth resistor R5. The control terminal of the power switch tube Q2 is connected to the first terminal of the switch tube Q1 through the fifth resistor R5, and the first terminal of the switch tube Q1 is connected to the second output terminal of the power supply access module CN1.

[0029] In this embodiment, the power supply access circuit mainly consists of three parts: a charging power resistor R1, a switching MOS, and a power MOS. The logic of the circuit operation is as follows:

[0030] When the power supply is connected from the power supply access module CN1, since the switch tube Q1 is not turned on, the power switch tube Q2 is also in the off state. At this time, the charging power resistor R1 is inserted to charge the backend capacitor C2. However, due to the existence of the charging power resistor R1, the charging peak current will not be too large. Only the maximum peak current I that needs to be controlled according to the design requirements can be used to calculate the corresponding value of R according to Ohm's law R1min = Uin / I.

[0031] When the backend capacitor C2 is almost fully charged, the delay circuit composed of the second resistor R2, the third resistor R3, and the first capacitor C1 reaches the turn-on voltage of the switch tube Q1 to turn on the switch tube Q1. The ratio of the values of the second resistor R2 and the third resistor R3 can be calculated through the turn-on voltage of the switch tube Q1 and the required delay time T. Generally, the required delay time T is taken as 3 * R1 * C2 time (charging to 0.95Uin) for the power resistor to charge the large capacitor. For example, if the voltage value to turn on the switch tube Q1 is U, the voltage U is set as the voltage (0.63 * Uin * R3 / (R2 + R3)) when the switch MOS is driven with a delay of (R2 / / R3) * C1.

[0032] In this embodiment, the following example is used to illustrate the power supply access circuit: Assume that the backend capacitor C2 is a 1000uF electrolytic capacitor, the input voltage Uin is 24V, the insertion current I needs to be controlled within 8A, and the turn-on voltage U of the switch tube Q1 is 2V. Calculate the values of each parameter in the circuit as follows:

[0033] The charging power resistor R1min = Uin / I = 24 / 8 = 3Ω, and the charging power resistor R1 can be taken as 5Ω;

[0034] Calculate the required delay time T = 3 * R1 * C2 = 3 * 5 * 1000 * 0.000001 = 0.015S;

[0035] U = 0.63 * Uin * R3 / (R2 + R3),

[0036] That is, R3 / (R2 + R3) = 2 / 0.63 / 24 = 0.13. Taking R3 as 10 kΩ, then R2 = 67 kΩ;

[0037] T = (R2 / / R3)*C1,

[0038] That is, C1 = T / (R2 / / R3) = 0.015 / (10*67 / (10 + 67)*1000) = 0.0000017 F = 1.7 uF; the standard value of 2 uF can be taken.

[0039] After the switching transistor Q1 is turned on, a large Vgs is immediately generated by dividing the voltage through the fourth resistor R4 and the fifth resistor R5, thereby turning on the power switching transistor Q2. After the power switching transistor Q2 is turned on, the low-resistance requirement of the main power circuit is ensured, and the circuit is in a balanced state at this time.

[0040] In summary, the power supply access circuit uses resistance current limiting for charging first and then controls the conduction of the MOS transistor to provide the main current path; not only is the drive circuit simple and the logic clear, but it is also easy to control, as long as the charging resistor and RC delay are selected according to different requirements.

[0041] The present invention also discloses an electronic device, including a power supply access circuit as described in any one of the above.

[0042] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention.

Claims

1. A power access circuit, characterized in that, Comprising: A power access module, a delay circuit, a switching transistor, a power switching transistor, a charging power resistor, a backend capacitor, and a fourth resistor; Wherein, the power access module is used to connect to a DC power supply. The input end of the power switching transistor and the first end of the charging power resistor are simultaneously connected to the first output end of the power access module. The output end of the power switching transistor and the second end of the charging power resistor are simultaneously connected to the first end of the backend capacitor. The second end of the backend capacitor is connected to the second output end of the power access module. The control end of the power switching transistor is connected to the first output end of the power access module through the fourth resistor and is connected to the second output end of the power access module through the switching transistor. The control end of the switching transistor is connected to the first output end of the power access module through the delay circuit. The delay circuit is configured to control the switching transistor to conduct after a preset time delay after the power access module is connected to the DC power supply.

2. The power supply access circuit according to claim 1, characterized in that, The delay circuit includes a second resistor, a third resistor, and a first capacitor. Wherein, one end of the second resistor is electrically connected to the first output end of the power access module. The other end of the second resistor is electrically connected to one end of the third resistor, one end of the first capacitor, and the control end of the switching transistor. The other end of the third resistor and the other end of the first capacitor are electrically connected to the second output end of the power access module.

3. The power supply access circuit according to claim 1, wherein, The switching transistor is an NMOS transistor.

4. A power access circuit according to claim 3, characterized in that, The control end of the switching transistor is the gate of the NMOS transistor. The first end of the switching transistor is the source of the NMOS transistor. The second end of the switching transistor is the drain of the NMOS transistor.

5. A power access circuit according to claim 1, characterized in that, The power switching transistor is a PMOS transistor.

6. The power supply access circuit according to claim 5, wherein, The control end of the power switching transistor is the gate of the PMOS transistor. The first end of the power switching transistor is the drain of the PMOS transistor. The second end of the power switching transistor is the source of the PMOS transistor.

7. A power access circuit according to claim 1, wherein It further includes a fifth resistor. The control end of the power switching transistor is connected to the first end of the switching transistor through the fifth resistor. The first end of the switching transistor is connected to the second output end of the power access module.

8. An electronic device, characterized in that, Comprising a power access circuit according to any one of claims 1 to 7.

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