Display substrate and display device

Abstract

The embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a display area and a first frame area, the first frame area is provided with a plurality of first type data output lines, a plurality of first type multi-path selection circuits, a plurality of second type multi-path selection circuits and a plurality of second type data output lines at least partially located in the first frame area. The plurality of first-type multi-path selection circuits are located among the plurality of second-type multi-path selection circuits; one end, close to the display area, of each data output line of the first type is electrically connected with the corresponding multi-path selection circuit of the first type; at least part of line segments of the second type data output lines are located in the display area, one ends of the line segments are electrically connected with the corresponding second type multi-path selection circuits, and the other ends of the line segments are located in the first frame area and connected with the corresponding second type driving bonding pads. According to the technical scheme provided by the embodiment of the invention, the technical problem of high difficulty in narrowing the frame of the display substrate in the prior art is solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to, but are not limited to, the field of display technologies, and particularly relate to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-luminescence, wide viewing angle, high contrast ratio, low power consumption, extremely high response speed, light weight, flexibility, and low cost. With the continuous development of display technologies, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and controlled by Thin Film Transistors (TFT) have become the mainstream products in the current display field.

[0003] With the development of OLED display technology, consumers have higher and higher requirements for the display effect of display products, and extremely narrow bezels have become a new trend in the development of display products. Therefore, the narrowing of bezels or even borderless designs have received increasing attention in the design of OLED display products.

[0004] Currently, there is a technical problem that it is difficult to design a narrow bezel for a display device. Summary of the Utility Model

[0005] The problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the technical problem that it is difficult to narrow the bezel of the existing display substrate.

[0006] To solve the above technical problem, in a first aspect, embodiments of the present disclosure provide a display substrate, including a display area and a first bezel area located on one side of the display area;

[0007] A plurality of sub-pixels, located in the display area;

[0008] A plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels;

[0009] A plurality of data output lines, electrically connected to the plurality of data lines;

[0010] A plurality of multiplexing circuits, located in the first border area, each multiplexing circuit of the plurality of multiplexing circuits being electrically connected to one data output line of the plurality of data output lines and at least two data lines of the plurality of data lines, each multiplexing circuit being configured to time-divisionally provide the signal provided by the one data output line to the at least two data lines;

[0011] A plurality of driving pads, located in the first border area and on a side of the plurality of multiplexing circuits away from the display area, the plurality of driving pads including a plurality of first-type driving pads and a plurality of second-type driving pads, the plurality of second-type driving pads being located between the plurality of first-type driving pads;

[0012] Wherein, the plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines, the plurality of multiplexing circuits include a plurality of first-type multiplexing circuits and a plurality of second-type multiplexing circuits, in a first direction, the plurality of first-type multiplexing circuits are located between the plurality of second-type multiplexing circuits; the plurality of first-type data output lines are located in the first border area and extend along a second direction, the first direction and the second direction intersect; one end of each first-type data output line close to the display area is electrically connected to a corresponding first-type multiplexing circuit, and the end far from the display area is connected to a corresponding first-type driving pad; at least a partial segment of each second-type data output line is located in the display area, one end of each second-type data output line is electrically connected to a corresponding second-type multiplexing circuit, and the other end is located in the first border area and is connected to a corresponding second-type driving pad.

[0013] In an exemplary embodiment, the second-type data output line includes a first structural portion, a second structural portion, and a third structural portion that are electrically connected in sequence, the second structural portion being located between the first structural portion and the third structural portion;

[0014] The first structural portion extends along the second direction and extends from the first border area to the display area, one end of the first structural portion located in the display area away from the first border area is electrically connected to the second structural portion, and the end of the first structural portion located in the first border area away from the display area is located between two adjacent first-type data output lines in the first direction;

[0015] The second structural portion is located in the display area and extends along the first direction, and both ends of the second structural portion are electrically connected to the first structural portion and the third structural portion respectively;

[0016] The third structural part extends along the second direction and extends from the first border area to the display area. It is connected to the second structural part at one end of the display area away from the first border area, and is electrically connected to the corresponding second-type multiplexing circuit at one end of the first border area away from the display area.

[0017] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the second structural part and the data line are located in different conductive layers.

[0018] In an exemplary embodiment, the first structural part located in the display area, the third structural part located in the display area, and the data line are located in the same conductive layer or in different conductive layers.

[0019] In an exemplary embodiment, the display substrate includes a substrate. In a direction perpendicular to the plane of the display substrate, the plurality of sub-pixels are disposed on one side of the substrate. At least one of the plurality of sub-pixels includes a thin-film transistor, a planarization layer, and a light-emitting element. The planarization layer is located on a side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on a side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin-film transistor includes an active layer on the substrate, a gate on a side of the active layer away from the substrate, a source electrode and a drain electrode on a side of the gate away from the substrate, and a transfer electrode on a side of the source electrode and the drain electrode away from the substrate. One of the source electrode and the drain electrode is electrically connected to the transfer electrode through a via, and the transfer electrode is electrically connected to the light-emitting element through the first planarization layer via;

[0020] The second structural part is disposed on the same layer as the source electrode and the drain electrode, and the data line is disposed on the same layer as the transfer electrode, or the second structural part is disposed on the same layer as the transfer electrode, and the data line is disposed on the same layer as the source electrode and the drain electrode.

[0021] In an exemplary embodiment, in the structure where the second structural part is disposed on the same layer as the source electrode and the drain electrode, and the data line is disposed on the same layer as the transfer electrode: the first structural part located in the display area, the third structural part located in the display area are disposed on the same layer as the source electrode and the drain electrode and are connected to the second structural part; or, the first structural part located in the display area, the third structural part located in the display area are disposed on the same layer as the transfer electrode and are connected to the second structural part through a via.

[0022] In an exemplary embodiment, in a structure in which the second structural portion and the switching electrode are arranged on the same layer, and the data line and the source and the drain are arranged on the same layer: the first structural portion located in the display area and the third structural portion located in the display area are arranged on the same layer as the switching electrode and are connected to the second structural portion; or, the first structural portion located in the display area and the third structural portion located in the display area are arranged on the same layer as the source and the drain and are connected to the second structural portion through a via.

[0023] In an exemplary embodiment, the first border region includes a bend region;

[0024] In the first structural portion located in the first border area, in the first type of data output line, in the same data output line, it includes a first part, a second part and a third part that are electrically connected in sequence, wherein, in the plane where the display substrate is located, in the second direction, the second part is located in the bending area, the first part is located on the side of the bending area close to the display area, and the third part is located on the side of the bending area away from the display area.

[0025] In an exemplary embodiment, the first portion is disposed in the same layer as the source and the drain, the second portion is disposed in the same layer as the transfer electrode, and the third portion is disposed in the same layer as the gate or in the same layer as the source and the drain; in the same data output line, the second portion is electrically connected to the first portion through a second via hole, and the second portion is electrically connected to the third portion through a third via hole.

[0026] In an exemplary embodiment, in the direction from the display area to the first border area, the first border area includes a multiplexing circuit area, the bending area, and a binding area which are arranged in sequence; the multiple multi-way selection circuits are located in the multiplexing circuit area, and the multiple driving pads are located in the binding area; the first part extends from the multiplexing circuit area to the bending area, and the third part extends from the bending area to the binding area.

[0027] In an exemplary embodiment, the second structure portion is located on a side of the display area close to the first frame area.

[0028] In an exemplary embodiment, the plurality of sub-pixels form a plurality of rows, and the second structural portion is located in at least one sub-pixel row on a side of the display area close to the first border area; or the second structural portion is located in at least one first spacing area on a side of the display area close to the first border area, and the first spacing area is an area between two adjacent rows of sub-pixels.

[0029] In an exemplary embodiment, in the first direction and on the same side of the first median line, the second type of multiplexing circuit is located on the side away from the first median line of the first type of multiplexing circuit, and the first median line is the median line extending along the second direction of the display area.

[0030] In an exemplary embodiment, in the first direction and on the same side of the first median line, in the direction from the second type of multiplexing circuit to the first type of multiplexing circuit, the first structural parts corresponding to the first to the last second type of multiplexing circuits are arranged in sequence, and the third structural parts corresponding to the first to the last second type of multiplexing circuits are arranged in sequence.

[0031] In an exemplary embodiment, in the first direction and on the same side of the first median line, in the direction from the second type of multiplexing circuit to the first type of multiplexing circuit, the second structural parts corresponding to the first to the last second type of multiplexing circuits are arranged in sequence along the direction from the first border area to the display area, or are arranged in sequence along the direction from the display area to the first border area;

[0032] In the first direction and on the same side of the first median line, in the direction from the display area to the first border area, the third structural part corresponding to the second structural part away from the first border area and the positive projection of the second structural part close to the first border area on the substrate at least partially overlap, and the second structural part and the third structural part are located in different conductive layers.

[0033] In an exemplary embodiment, in the first direction and on the same side of the first median line, in the direction from the second type of multiplexing circuit to the first type of multiplexing circuit, the first structural parts corresponding to the last to the first second type of multiplexing circuits are arranged in sequence, and the third structural parts corresponding to the first to the last second type of multiplexing circuits are arranged in sequence.

[0034] In an exemplary embodiment, in the first direction and on the same side of the first median line, in the direction from the second type of multiplexing circuit to the first type of multiplexing circuit, the second structural parts corresponding to the last to the first second type of multiplexing circuits are arranged in sequence along the direction from the first border area to the display area;

[0035] On the same side of the first center line in the first direction, in the direction pointing from the display area to the first border area, the third structural part corresponding to the second structural part away from the first border area does not overlap with the positive projection of the second structural part close to the first border area on the substrate, and the second structural part and the third structural part are located in different conductive layers or the same conductive layer.

[0036] In an exemplary embodiment, the display substrate further includes:

[0037] At least two data selection lines: located in the first border area;

[0038] Wherein, the multiplexing circuit is electrically connected to the at least two data selection lines, and each multiplexing circuit is configured to provide the signal of one data output line to the at least two data lines in a time-division manner under the control of the at least two data selection lines.

[0039] In an exemplary embodiment, the display substrate includes a substrate, the plurality of data lines and the data selection lines are located on one side of the substrate, and the at least two data selection lines extend along the first direction and are arranged at intervals along the second direction;

[0040] The third structural part and the data selection line are located in different conductive layers, and the positive projection of the third structural part and the at least two data selection lines on the substrate overlaps.

[0041] In an exemplary embodiment, the number of the data lines is M, the number of the data output lines is k, the number of the data selection lines is z, k = M / z, both M and k are positive integers, and z is an integer greater than or equal to 2;

[0042] Each multiplexing circuit is electrically connected to adjacent z data lines, and is configured to provide the signal of the one data output line to the corresponding z data lines in a time-division manner under the control of z data selection lines.

[0043] In an exemplary embodiment, the plurality of sub-pixels form N columns of sub-pixels, the M data lines include N pairs of data lines, at least one pair of data lines includes a first data line and a second data line, k = 2N / z, N is a positive integer, and M = 2N;

[0044] Among the plurality of sub-pixels in the same column of sub-pixels, two adjacent sub-pixels are electrically connected to the first data line and the second data line in a pair of data lines respectively.

[0045] In an exemplary embodiment, z is 4, and each of the multiplexing circuits is electrically connected to four data lines in two adjacent pairs of data lines, and is configured to time-divisionally provide the signal of one data output line to the corresponding four data lines under the control of four data selection lines.

[0046] In an exemplary embodiment, the multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; in the same multiplexing circuit, the first multiplexing sub-circuit is electrically connected to one pair of data lines, and the second multiplexing sub-circuit is electrically connected to another adjacent pair of data lines.

[0047] In an exemplary embodiment, the four data selection lines include a first data selection line, a second data selection line, a third data selection line, and a fourth data selection line. The first multiplexing sub-circuit includes a first multiplexing transistor, a third multiplexing transistor, and a fifth multiplexing transistor. The second multiplexing sub-circuit includes a second multiplexing transistor, a fourth multiplexing transistor, and a sixth multiplexing transistor.

[0048] The first poles of the first multiplexing transistor and the second multiplexing transistor are electrically connected to one data output line. The second pole of the first multiplexing transistor is electrically connected to the first poles of the third multiplexing transistor and the fifth multiplexing transistor. The second pole of the second multiplexing transistor is electrically connected to the first poles of the fourth multiplexing transistor and the sixth multiplexing transistor. The second poles of the third multiplexing transistor, the fourth multiplexing transistor, the fifth multiplexing transistor, and the sixth multiplexing transistor are electrically connected to four adjacent data lines in the display area. The control pole of the first multiplexing transistor is electrically connected to the first data selection line. The control pole of the second multiplexing transistor is electrically connected to the second data selection line. The control poles of the third multiplexing transistor and the fourth multiplexing transistor are electrically connected to the third data selection line. The control poles of the fifth multiplexing transistor and the sixth multiplexing transistor are electrically connected to the fourth data selection line.

[0049] In an exemplary embodiment, z is 2, and each of the multiplexing circuits is electrically connected to two data lines in one pair of data lines, and is configured to time-divisionally provide the signal of one data output line to the corresponding two data lines under the control of two data selection lines.

[0050] In an exemplary embodiment, the plurality of sub-pixels form M columns of sub-pixels, and the plurality of sub-pixels in the same column of sub-pixels are electrically connected to one of the data lines.

[0051] In an exemplary embodiment, z has a value of 2, and each of the multiplexing circuits is electrically connected to two adjacent data lines, and is configured to provide the signal of one data output line to the corresponding two data lines in a time-division manner under the control of two data selection lines.

[0052] In an exemplary embodiment, the two data selection lines include a first data selection line and a second data selection line, and the multiplexing circuit includes a first multiplexing transistor and a second multiplexing transistor;

[0053] A first pole of the first multiplexing transistor and a first pole of the second multiplexing transistor are electrically connected to one of the data output lines, and a second pole of the first multiplexing transistor and a second pole of the second multiplexing transistor are respectively electrically connected to two adjacent data lines in the display area; a control pole of the first multiplexing transistor is electrically connected to the first data selection line, and a control pole of the second multiplexing transistor is electrically connected to the second data selection line.

[0054] In an exemplary embodiment, z has a value of 4, and each of the multiplexing circuits is electrically connected to four adjacent data lines, and is configured to provide the signal of the one data output line to the corresponding four data lines in a time-division manner under the control of four data selection lines.

[0055] In a second aspect, the present disclosure also provides a display device including the display substrate according to any one of the above embodiments.

[0056] The display substrate and the display device provided by the embodiments of the present disclosure, the display substrate includes a display area and a first border area on one side of the display area, the display area includes a plurality of sub-pixels and a plurality of data lines, the first border area includes a plurality of multiplexing circuits and a plurality of driving pads, the display substrate further includes a plurality of data output lines, wherein the plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines, the plurality of multiplexing circuits include a plurality of first-type multiplexing circuits and a plurality of second-type multiplexing circuits, in a first direction, the plurality of first-type multiplexing circuits are located between the plurality of second-type multiplexing circuits; the plurality of first-type data output lines are located in the first border area and extend along a second direction; one end of each first-type data output line close to the display area is electrically connected to the corresponding first-type multiplexing circuit, and the other end far from the display area is connected to the corresponding first-type driving pad; at least a partial line segment of each second-type data output line is located in the display area, one end of each second-type data output line is electrically connected to the corresponding second-type multiplexing circuit, and the other end is located in the first border area and is connected to the corresponding second-type driving pad. The display substrate provided by the embodiments of the present disclosure can reduce the size of the first border area in the column direction and can overcome the technical problem of great difficulty in narrowing the border of the display substrate.

[0057] Other aspects will be apparent upon reading and understanding the accompanying drawings and the detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The accompanying drawings are provided to further understand the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure, and do not constitute a limitation to the technical solutions of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual scale, and the purpose is only to schematically illustrate the content of the present disclosure.

[0059] Figure 1 Shown is a schematic structural diagram of a display device;

[0060] Figure 2 Shown is a schematic structural diagram of a display substrate;

[0061] Figure 3 Shown is an enlarged schematic structural diagram of a first border region;

[0062] Figure 4 Described is a schematic structural diagram of a display substrate;

[0063] Figure 5 Described is a schematic plan view structural diagram of a display substrate;

[0064] Figure 6 Shown is a schematic structural diagram of a display substrate;

[0065] Figure 7a Shown is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0066] Figure 7b Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0067] Figure 8a Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0068] Figure 8b Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0069] Figure 8c Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0070] Figure 8d Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0071] Figure 9a Shown is a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0072] Figure 9b The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0073] Figure 9c The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0074] Figure 9d The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0075] Figure 10a The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0076] Figure 10b The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0077] Figure 10c The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0078] Figure 10d The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0079] Figure 11a The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0080] Figure 11b The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0081] Figure 11c The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0082] Figure 12 The figure shows a schematic structural diagram of a display substrate provided by an exemplary embodiment of the present disclosure;

[0083] Figure 13a The figure shows a schematic planar structure diagram of a multiplexing circuit provided by an exemplary embodiment of the present disclosure;

[0084] Figure 13b The figure shows a schematic planar structure diagram of a multiplexing circuit provided by an exemplary embodiment of the present disclosure;

[0085] Figure 14a Shown as Figure 13a a schematic cross-sectional structure diagram at the A1 - A2 position in;

[0086] Figure 14b Shown as Figure 13a a schematic cross-sectional structure diagram at the W1 - W2 position in;

[0087] Figure 15 The figure shows a schematic cross-sectional structure diagram of the position of the second structural part of the display area provided by an exemplary embodiment of the present disclosure;

[0088] Figure 16 The figure shows a schematic cross-sectional structure diagram of the position of the second structural part of the display area provided by an exemplary embodiment of the present disclosure;

[0089] Figure 17 The figure shows a schematic cross-sectional structure diagram of the position of the second structural part of the display area provided by an exemplary embodiment of the present disclosure;

[0090] Figure 18 The figure shows a schematic cross-sectional structure diagram of the position of the second structural part of the display area provided by an exemplary embodiment of the present disclosure;

[0091] Figure 19a The figure shows a schematic plan structure diagram of the active layer of the multiplexing circuit provided by an exemplary embodiment of the present disclosure;

[0092] Figure 19b The figure shows a schematic plan structure diagram of the multiplexing circuit after forming the first conductive layer provided by an exemplary embodiment of the present disclosure;

[0093] Figure 19c The figure shows a schematic plan structure diagram of the multiplexing circuit provided by an exemplary embodiment of the present disclosure;

[0094] Figure 19d The figure shows a schematic plan structure diagram of the multiplexing circuit provided by an exemplary embodiment of the present disclosure;

[0095] Figure 20 The figure shows a schematic cross-sectional structure diagram of a display area provided by an exemplary embodiment of the present disclosure;

[0096] Figure 21 The figure shows a schematic structure diagram of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0097] The implementation manners in the present disclosure can be implemented in multiple different forms. Those of ordinary skill in the art can easily understand the fact that the implementation manners and content can be transformed into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the content described in the following implementation manners. Without conflict, the embodiments and features in the embodiments of the present disclosure can be combined arbitrarily with each other.

[0098] In the drawings, for clarity, the sizes of components, the thicknesses of layers, or regions may sometimes be exaggerated. Therefore, any implementation of the present disclosure is not necessarily limited to the dimensions shown in the figures, and the shapes and sizes of components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and any implementation of the present disclosure is not limited to the shapes or values shown in the drawings, etc.

[0099] The ordinal numbers such as "first", "second", "third", etc. in the present disclosure are provided to avoid confusion of components and are not intended to limit the quantity.

[0100] In the present disclosure, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of components with reference to the drawings. This is only for the convenience of describing the embodiments and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of the present disclosure. The positional relationships of components can be appropriately changed according to the directions of the described components. Therefore, it is not limited to the terms described in the text and can be appropriately replaced according to the circumstances.

[0101] In the present disclosure, unless otherwise clearly specified and limited, the terms "mounted", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the communication inside two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0102] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (or drain electrode terminal, drain connection region, or drain electrode) and the source electrode (or source electrode terminal, source connection region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to the region where current mainly flows.

[0103] In the present disclosure, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" can sometimes be interchanged. Therefore, in the present disclosure, the "source electrode" and "drain electrode" can be interchanged. In the present disclosure, the control pole can be the gate electrode.

[0104] In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it can transfer electrical signals between the constituent elements to be connected. The "element having a certain electrical function" can be, for example, an electrode or a wiring, or a switching element such as a transistor, or other functional elements such as a resistor, an inductor, or a capacitor.

[0105] Figure 1The following is a schematic structural diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is respectively connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is respectively connected to a plurality of data signal lines (D1 to Dn), the scan signal driving circuit is respectively connected to a plurality of scan signal lines (G1 to Gm), and the light emission signal driving circuit is respectively connected to a plurality of light emission signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scan signal line, the light emission signal line, and the data signal line (which may be referred to as a data line). In an exemplary embodiment, the timing controller may provide a gray value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, may provide a clock signal, a scan start signal, etc. suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and may provide a clock signal, an emission stop signal, etc. suitable for the specification of the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit may use the gray value and the control signal received from the timing controller to generate data voltages that will be provided to the data signal lines D1, D2, D3,..., and Dn. For example, the data signal driving circuit may sample the gray value using a clock signal and apply the data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driving circuit may generate scan signals that will be provided to the scan signal lines G1, G2, G3,..., and Gm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan signal driving circuit may sequentially provide scan signals having conductive level pulses to the scan signal lines G1 to Gm. For example, the scan signal driving circuit may be configured in the form of a shift register and may generate scan signals in such a way that the scan start signal provided in the form of a conductive level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, where m may be a natural number. The light emission signal driving circuit may generate emission signals that will be provided to the light emission signal lines E1, E2, E3,..., and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emission signal driving circuit may sequentially provide emission signals having cut-off level pulses to the light emission signal lines E1 to Eo. For example, the light emission driver may be configured in the form of a shift register and may generate emission signals in such a way that the emission stop signal provided in the form of a cut-off level pulse is sequentially transmitted to the next-stage circuit under the control of a clock signal, where o may be a natural number.

[0106] Figure 2The following shows a schematic structural diagram of a display panel. As Figure 2 shown, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the peripheral area BB may include: a first border (lower border) B1 and a second border (upper border) B2 oppositely arranged in the second direction Y, and a third border (left border) B3 and a fourth border (right border) B4 oppositely arranged in the first direction X. The first border B1 is connected to the third border B3 and the fourth border B4, and the second border B2 is connected to the third border B3 and the fourth border B4. In some examples, the display area AA may include a first edge (lower edge) and a second edge (upper edge) oppositely arranged in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) oppositely arranged in the first direction X. The display area AA may include a plurality of regularly arranged sub-pixels Pxij. The sub-pixel may include a pixel driving circuit and a light-emitting device. The first border B1 may include a bonding circuit for connecting a signal line to an external driving device. The third border B3 and the fourth border B4 may include a gate driving circuit and a second power supply line VSS for transmitting a voltage signal to the plurality of sub-pixels.

[0107] Figure 3 The following shows a schematic plan view of the first border area B1. In a plane parallel to the display substrate, the first border area B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged in sequence along the direction away from the display area AA; wherein, the bonding area 14 may include a driving chip area 141 and a bonding electrode area 142 arranged in sequence along the direction of the second fan-out area 13 away from the bending area 12. The first fan-out area 11 may include data fan-out lines, a first power supply line, and a second power supply line VSS. The data fan-out lines are located in the middle of the first fan-out area 11 and include a plurality of data connection lines. The plurality of data connection lines are configured to connect the data lines (Data Line) of the display area AA in a fan-out (Fanout) routing manner. The first power supply line is configured to connect the high-voltage power supply line (VDD) of the display area AA, and the second power supply line is the low-voltage power supply line (VSS) located in the third border area B3 and the fourth border area B4. The bending area 12 may include a composite insulating layer provided with a groove and is configured to bend the bonding area 14 to the back of the display area AA (such as Figure 4As shown). The second fan-out region 13 includes a plurality of data connection lines led out in a fan-out wiring manner. The driving chip region 141 may be provided with an integrated circuit (IC) 20, which is configured to be connected to the plurality of data connection lines. The bonding electrode region 142 includes a plurality of bonding pads, which are configured to be bonded and connected to a flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded and connected to the driving chip region 141, and the flexible printed circuit (FPC) 30 may be bonded and connected to the bonding electrode region 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit) may generate driving signals required for driving sub-pixels and may provide the driving signals to the sub-pixels Pxij located in the display area AA. For example, the driving signal may be a data signal for controlling the light-emitting brightness of the sub-pixels. In an exemplary embodiment, the bonding electrode region 142 may be provided with pads (PADs) including a plurality of pins (PINs), and the flexible circuit board 30 may be bonded and connected to the pads.

[0108] In an exemplary embodiment, as Figure 4 shown, the bending region 12 may invert the surface of the bonding region 14, that is, the surface of the bonding region 14 facing upward may be converted to face downward through the bending of the bending region 12. In an exemplary embodiment, when the bending region 12 is bent, the bonding region 14 may overlap with the display area AA in the thickness direction of the display panel.

[0109] In an exemplary embodiment, for a large-sized display substrate, a plurality of data driving ICs (which may be referred to as driving ICs, that is, driving integrated circuits) and a plurality of FPCs may be provided. The plurality of FPCs are respectively bonded and connected to the plurality of data driving ICs. For example, four data driving ICs may be provided and respectively bonded and connected to four FPCs. The embodiments of the present disclosure are not limited to four ICs and four FPCs. For example, two data driving ICs and two FPCs may be provided; for a small-sized display substrate, one data driving IC or two data driving ICs may be provided. In the embodiments of the present disclosure, the number of data driving ICs and FPCs may be set according to the size and function requirements of the display substrate, and the present disclosure does not make a limitation here.

[0110] With the development of display technology, people's requirements for high refresh rate and narrow bezel are getting higher and higher. In the case of existing display substrates meeting the high refresh rate, it is very difficult to further narrow the bezel, and there is a problem of great difficulty in bezel narrowing design. In order to improve the refresh rate of the display substrate and at the same time meet the threshold voltage (Vth) compensation ability of the display substrate, a dual data line (Dual Source) structure can be adopted. The dual data line structure can be called dual data link (English: Dual Data Link, abbreviated: DDL) technology to increase the compensation time of the threshold voltage and improve the display quality. As Figure 5 shown, it is a schematic structural diagram of a display panel with dual data lines. The display panel includes M×N display units arranged in an array defined by the intersection of M gate lines and N pairs of data lines. M and N are integers greater than or equal to 2. Each pair of data lines includes a first data line DA and a second data line DB, which are respectively arranged on both sides of the corresponding display column. For the m-th display row, m = 1, 2,..., M, the N display units in the m-th display row are all connected to the m-th gate line G(m). For the n-th display column, n = 1, 2,..., N, the two data lines in the n-th data line D(n) are respectively connected to the display units of odd display rows and even display rows, that is, the display units of odd display rows in the n-th display column are connected to the first data line DA, and the display units of even display rows are connected to the second data line DB; or the display units of even display rows are connected to the first data line DA, and the display units of odd display rows are connected to the second data line DB. During the operation of the display panel, within one row period when the m-th gate line G(m) outputs a scan signal, all the second data lines DB write display data to all the display units in the m-th display row. Within one row period when the m + 1-th gate line G(m + 1) outputs a scan signal, all the first data lines DA write display data to all the display units in the m + 1-th display row.

[0111] In Figure 5 the shown display panel, the dual data line structure increases the number of data lines, resulting in an increase in the size of the first bezel B1 of the display substrate along the second direction Y. In the case of achieving high refresh rate and high display quality, there is a problem of great difficulty in bezel narrowing design. Adopting the dual data line structure (DDL technology) leads to an increase in the number of data lines, and the number of pins of the driving IC is limited. A data selector (abbreviated as MUX, English name is multiplexer, and can be called MUX technology) can be adopted, which can reduce the number of pins of the driving IC and, in some cases, reduce the number of driving ICs and lower the cost. As Figure 6As shown, in the case of using the MUX technology, additional space for setting the data selector (MUX) 40 is required in the first border area B1, which will increase the size of the first border B1 along the second direction Y. To reduce the width of the lower border, some display substrates adopt the FIAA (Fanout in AA, where the data fan-out lines are located in the display area) or FIP (Fanout In Panel) technology, that is, new signal traces are added in the display area AA, and the data signals of some data lines are transmitted by the newly added signal traces, reducing the size of the first fan-out area 11 along the second direction Y, thereby reducing the width of the first border B1 (i.e., the size of the first border B1 along the second direction Y). However, in the double data line structure, the number of data lines in the display area AA is relatively dense, and it is difficult to add too many new signal traces in the display area AA, that is, FIAA or FIP cannot be used to reduce the border in the double data line structure. In the single data line (single Source) structure, in the high PPI structure, the line density of the display area AA is also very large, and it is difficult to add too many new signal traces in the display area AA, and there is also the technical problem that FIAA or FIP cannot be used to reduce the border. In addition, in the structure using FIAA or FIP, the line density of the display area AA increases and the light transmittance decreases.

[0112] As can be seen from the above, in the display substrate, there is a technical problem of great difficulty in narrowing the border.

[0113] Embodiments of the present disclosure provide a display substrate, which may include a display area and a first border area located on one side of the display area;

[0114] A plurality of sub-pixels, located in the display area;

[0115] A plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels;

[0116] A plurality of data output lines, electrically connected to the plurality of data lines;

[0117] A plurality of multiplexing circuits, located in the first border area, each multiplexing circuit in the plurality of multiplexing circuits is electrically connected to one data output line among the plurality of data output lines and at least two data lines among the plurality of data lines, and each of the multiplexing circuits is configured to time-divisionally provide the signal provided by the one data output line to the at least two data lines;

[0118] A plurality of driving pads are located in the first border region and on a side of the plurality of multiplexing circuits away from the display region. The plurality of driving pads include a plurality of first-type driving pads and a plurality of second-type driving pads, and the plurality of second-type driving pads are located between the plurality of first-type driving pads;

[0119] Wherein, the plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines, and the plurality of multiplexing circuits include a plurality of first-type multiplexing circuits and a plurality of second-type multiplexing circuits. In a first direction, the plurality of first-type multiplexing circuits are located between the plurality of second-type multiplexing circuits; the plurality of first-type data output lines are located in the first border region and extend along a second direction, and the first direction intersects with the second direction; one end of each first-type data output line close to the display region is electrically connected to a corresponding first-type multiplexing circuit, and the other end away from the display region is connected to a corresponding first-type driving pad; at least a partial segment of each second-type data output line is located in the display region, one end of each second-type data output line is electrically connected to a corresponding second-type multiplexing circuit, and the other end is located in the first border region and is connected to a corresponding second-type driving pad.

[0120] In the display substrate provided by an embodiment of the present disclosure, it includes a display region and a first border region on one side of the display region. The display region includes a plurality of sub-pixels and a plurality of data lines, and the first border region includes a plurality of multiplexing circuits and a plurality of driving pads. The display substrate further includes a plurality of data output lines. Wherein, the plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines, and the plurality of multiplexing circuits include a plurality of first-type multiplexing circuits and a plurality of second-type multiplexing circuits. In a first direction, the plurality of first-type multiplexing circuits are located between the plurality of second-type multiplexing circuits; the plurality of first-type data output lines are located in the first border region and extend along a second direction; one end of each first-type data output line close to the display region is electrically connected to a corresponding first-type multiplexing circuit, and the other end away from the display region is connected to a corresponding first-type driving pad; at least a partial segment of each second-type data output line is located in the display region, one end of each second-type data output line is electrically connected to a corresponding second-type multiplexing circuit, and the other end is located in the first border region and is connected to a corresponding second-type driving pad. The display substrate provided by the embodiment of the present disclosure can reduce the size of the first border region in the column direction and can overcome the technical problem of great difficulty in narrowing the border of the display substrate.

[0121] Such as Figure 7aAs shown, it is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure. The display substrate may include a display area AA and a first border area B1 located on one side of the display area AA;

[0122] Multiple sub-pixels Pxij, located in the display area AA;

[0123] Multiple data lines DL, located in the display area AA and electrically connected to the multiple sub-pixels Pxij. The multiple data lines DL are configured to provide data signals to the multiple sub-pixels Pxij;

[0124] Multiple data output lines DT, electrically connected to the multiple data lines DL;

[0125] Multiple multiplexing circuits 40, located in the first border area B1. Each multiplexing circuit 40 among the multiple multiplexing circuits 40 is electrically connected to one data output line DT among the multiple data output lines DT and at least two data lines DL among the multiple data lines DL. Each multiplexing circuit 40 is configured to time-divisionally provide the signal provided by one data output line DT to at least two data lines DL;

[0126] Multiple driving pads, located in the first border area B1 and on the side of the multiple multiplexing circuits 40 away from the display area AA. The multiple driving pads include multiple first-type driving pads and multiple second-type driving pads. The multiple second-type driving pads are located between the multiple first-type driving pads;

[0127] Among them, the multiple data output lines DT include multiple first-type data output lines DT and multiple second-type data output lines DT. The multiple multiplexing circuits 40 include multiple first-type multiplexing circuits 40 and multiple second-type multiplexing circuits 40. In the first direction X, the multiple first-type multiplexing circuits 40 are located between the multiple second-type multiplexing circuits 40; The multiple first-type data output lines DT are located in the first border area B1 and extend along the second direction Y. The first direction X and the second direction Y intersect; One end of each first-type data output line DT close to the display area AA is electrically connected to the corresponding first-type multiplexing circuit 40, and the end away from the display area AA is connected to the corresponding first-type driving pad; At least a part of each second-type data output line DT is located in the display area AA. One end of each second-type data output line DT is electrically connected to the corresponding second-type multiplexing circuit 40, and the other end is located in the first border area B1 and is connected to the corresponding second-type driving pad.

[0128] In an exemplary embodiment, in Figure 7aIn the structure shown, the multiplexing circuit 40 electrically connected to the driving circuit 20 may include a first multiplexing circuit 401 to a tenth multiplexing circuit 410. Among them, in the first direction X, the second-type multiplexing circuits 42 located on both sides may include: the first multiplexing circuit 401, the second multiplexing circuit 402, the ninth multiplexing circuit 409, and the tenth multiplexing circuit 410; the first-type multiplexing circuits 41 located in the middle may include the third multiplexing circuit 403 to the eighth multiplexing circuit 408. The second-type data output lines DT may include a first data output line DT1, a second data output line DT2, a ninth data output line DT9, and a tenth data output line DT10. The first-type data output lines DT may include a third data output line DT3 to an eighth data output line DT8. Among them, the first data output line DT1 to the tenth data output line DT10 are electrically connected to the first multiplexing circuit 401 to the tenth multiplexing circuit 410 respectively. Figure 7a The illustration is for convenience of example, taking the number of data output lines DT and multiplexing circuits 40 marked as ten as an example. The actual number of data output lines DT may be more than ten. For example, in the first direction X, multiple first-type data output lines DT may be provided between the fifth data output line DT5 and the sixth data output line DT6, multiple first multiplexing circuits 41 may be provided between the fifth multiplexing circuit 405 and the sixth multiplexing circuit 406, multiple second-type multiplexing circuits 42 may be provided on the side of the first multiplexing circuit 401 away from the second multiplexing circuit 402, and multiple second-type multiplexing circuits 42 may be provided on the side of the tenth multiplexing circuit 410 away from the ninth multiplexing circuit 409.

[0129] In the embodiment of the present disclosure, in the first direction X, the first-type data output lines DT are located in the middle region, and the second-type data output lines DT are located on both sides. The first-type data output lines DT extend along the second direction Y and are electrically connected to the corresponding first-type multiplexing circuits 41. At least part of the line segments of the second-type data output lines DT located on both sides are located in the display area AA. One end is inserted between adjacent first-type data output lines DT and is connected to the corresponding second-type driving pad, and the other end is electrically connected to the corresponding second-type multiplexing circuit 42. In the first border region B1, the first-type data output lines and the second-type data output lines extend along the second direction Y. The first border region B1 saves the routing space of the middle part of the second-type data output lines located in the display area AA and the end part connected to the second-type multiplexing circuit, and can reduce the size of the first border region B1 along the second direction Y.

[0130] In an exemplary embodiment, as Figure 7bAs shown, the display substrate may further include:

[0131] At least two data selection lines MUX: located in the first border area B1; wherein, the multiplexing circuit 40 is electrically connected to at least two data selection lines MUX, and each multiplexing circuit 40 is configured to time-divisionally provide the signal of one data output line DT to the corresponding at least two data lines under the control of the at least two data selection lines.

[0132] In an exemplary embodiment, the number of data lines DL is M, the number of data output lines DT is k, the number of data selection lines MUX is z, k = M / z, both M and k are positive integers, and z is an integer greater than or equal to 2;

[0133] Each multiplexing circuit 40 is electrically connected to the adjacent z data lines DL, and is configured to time-divisionally provide the signal of one data output line DT to the corresponding z data lines DL under the control of the z data selection lines MUX.

[0134] In an exemplary embodiment, as Figures 7a to 9c shown, multiple sub-pixels Pxij may form N columns of sub-pixels, M data lines DL may include N pairs of data lines DL, at least one pair of data lines includes a first data line DL1 and a second data line DL2, k = 2N / z, N is a positive integer, and M = 2N;

[0135] Among the multiple sub-pixels Pxij in the same column of sub-pixels, two adjacent sub-pixels Pxij are respectively electrically connected to the first data line DL1 and the second data line DL2 in a pair of data lines.

[0136] In an exemplary embodiment, as Figures 10a to 11b shown, multiple sub-pixels Pxij may form M columns of sub-pixels, and the multiple sub-pixels Pxij in the same column of sub-pixels are electrically connected to one of the data lines DL.

[0137] The technical solutions of the embodiments of the present disclosure will be described in detail below through specific embodiments:

[0138] As Figures 8a to 8dAs shown, it is a schematic plan view of a display substrate provided by an exemplary embodiment of the present disclosure. In the plane where the display substrate is located, the display substrate may include a display area AA and a border area BB surrounding the display area AA. In the second direction Y, the border area BB may include a first border area B1 and a second border area B2 located on both sides of the display area AA. The display area AA may include N columns of sub-pixels Pxij and N pairs of data lines DL respectively connected to the N columns of sub-pixels Pxij. The first border area B1 may include a multiplexing circuit 400, k data output lines DT, and a driving circuit 20 arranged in sequence along the second direction Y. At least one pair of data lines DL includes a first data line DL1 and a second data line DL2. N and k are positive integers. Among the multiple sub-pixels Pxij in the same column of sub-pixels, two adjacent sub-pixels Pxij are respectively electrically connected to the first data line DL1 and the second data line DL2 in a pair of data lines DL. In the plane where the display substrate is located, multiple data lines DL among the N pairs of data lines DL extend along the second direction Y and are arranged at intervals along the first direction X. The part of the k data output lines DT located in the first border area B1 extends along the second direction Y and is arranged at intervals along the first direction X. The first direction X intersects with the second direction Y.

[0139] Among them, the data lines DL located in the display area AA are electrically connected to the multiplexing circuit 400. The multiplexing circuit 400 may include k multiplexing circuits (which may be referred to as multiplexers) 40. The k multiplexing circuits 40 are respectively electrically connected to the driving circuit (which may be referred to as a driving chip) 20 through the k data output lines DT. The driving circuit 20 may be connected to the first border area B1 in a bonding manner (for example, the driving circuit 20 may be connected to the bonding area in the first border area B1).

[0140] Such as Figure 8a and Figure 8bAs shown, the number of data output lines DT electrically connected to the driving circuit 20 can be ten (for the convenience of illustration, the number of data output lines DT and multiplexing circuits 40 is taken as ten as an example, and the actual number may be more than ten). The driving circuit 20 can be electrically connected to ten multiplexing circuits 40 respectively through ten data output lines DT. The data lines DL in the display area AA are electrically connected to the multiplexing circuit 400 at the position where the display area AA is adjacent to the first border area B1 (for example, at the position where the first border area B1 is adjacent to the display area AA). In the first direction X, among the multiple multiplexing circuits 40 electrically connected to the driving circuit 20, the six first-type multiplexing circuits 41 in the middle can be electrically connected to the driving circuit 20 through the first-type data output lines DT, and the four second-type multiplexing circuits 42 on both sides can be electrically connected to the driving circuit 20 through the second-type data output lines DT. The shape of the first-type data output line DT can be a straight line or a strip extending along the second direction Y, and the shape of the second-type data output line DT can be an "L" shape or a "J" shape. For example, in the first direction X, the first multiplexing circuit 401 to the tenth multiplexing circuit 410 are arranged in sequence. Among the ten data output lines DT electrically connected to the driving circuit 20, the third data output line DT3 to the eighth data output line DT8 respectively connected to the third multiplexing circuit 403 to the eighth multiplexing circuit 408 in the middle can be the first-type data output lines DT in the form of a straight line or a strip extending along the second direction Y. One ends of the six first-type data output lines DT are respectively electrically connected to six driving pads at the middle position (electrically connected to the driving circuit 20 through the driving pads), and the other ends are electrically connected to the corresponding first-type multiplexing circuits 40. The four data output lines DT connected to the first multiplexing circuit 401, the second multiplexing circuit 402, the ninth multiplexing circuit 409, and the tenth multiplexing circuit 410 can be the second-type data output lines DT. The shape of the first data output line DT1 connected to the first multiplexing circuit 401 and the second data output line DT2 connected to the second multiplexing circuit 402 can be an "L" shape rotated 180° clockwise, and the shape of the ninth data output line DT9 connected to the ninth multiplexing circuit 401 and the tenth data output line DT10 connected to the tenth multiplexing circuit 410 can be an "L" shape flipped along the first direction X.

[0141] In an exemplary embodiment, Figures 8a to 8d The double data line structure is shown, where 8a to Figure 8b A schematic structural diagram based on a dual source mux 1:4 is shown. Figures 8c to 8dThe following is a schematic structural diagram based on a dual source mux1:2. In an exemplary embodiment, in Figure 8a and Figure 8c In the shown structure, among the multiple second-type data output lines DT located in the display area AA, there is no intersection; in Figure 8b and Figure 8d In the shown structure, among the multiple second-type data output lines DT located in the display area AA, at least some of them intersect.

[0142] In an exemplary embodiment, in Figure 8a In the shown structure, at one end of the multiple data output lines DT in the first border area B1 connected to the driving circuit 20, the first data output line DT1 electrically connected to the first multiplexing circuit 401 is located between the fourth data output line DT4 and the fifth data output line DT5, and the second data output line DT2 electrically connected to the second multiplexing circuit 402 is located between the fourth data output line DT4 and the third data output line DT3. That is, in the first border area B1, among the multiple first structural parts a1 (as shown in Figure 9a and Figure 9b The first structural part a1 is a partial line segment of the second-type data output line DT electrically connected to the corresponding second-type multiplexing circuit) located on one side of the midline of the driving circuit 20 extending along the second direction Y in the first direction X, in the direction of the border area (the third border area B3 or the fourth border area B4) of the display area AA pointing to this side, the first first structural part a1 to the last first structural part a1 are arranged in sequence. In the display area AA, the orthographic projections of the multiple second-type data output lines DT on the substrate do not overlap. This structure can be called reverse order; in Figure 8b In the shown structure, at one end of the multiple data output lines DT in the first border area B1 connected to the driving circuit 20, the first data output line DT1 electrically connected to the first multiplexing circuit 401 is located between the fourth data output line DT4 and the third data output line DT3, and the second data output line DT2 electrically connected to the second multiplexing circuit 402 is located between the fourth data output line DT4 and the fifth data output line DT5. That is, in the first border area B1, among the multiple first structural parts a1 located on one side of the midline of the driving circuit 20 extending along the second direction Y in the first direction X, in the direction of this side's border area (the third border area B3 or the fourth border area B4) pointing to the display area AA, the first first structural part a1 to the last first structural part a1 are arranged in sequence. In the display area AA, the orthographic projections of the multiple second-type data output lines DT on the substrate overlap. This structure can be called forward order.

[0143] In an exemplary embodiment, as shown in Figure 9aand Figure 9b As shown in Figure 8a is an enlarged structural schematic diagram. The value of z can be 4. Each multiplexing circuit 40 can be electrically connected to four data lines DL in two adjacent pairs of data lines, and is configured to time-divisionally provide the signal of a corresponding data output line DT to the corresponding four data lines DL under the control of four data selection lines. In an exemplary embodiment, Figure 9a In the segment of the second type of data output line DT connected to the driving pad in Figure 9b the segment located in the display area AA and the segment of the part located on the side close to the display area AA in the first border area B1 are located in the same conductive layer;

[0144] In an exemplary embodiment, as in Figure 9a , Figure 9b , Figure 9d , Figure 11b and Figure 11c As shown, the multiplexing circuit 40 may include a first multiplexing sub-circuit 4001 and a second multiplexing sub-circuit 4002. In the same multiplexing circuit 40, the first multiplexing sub-circuit 4001 is electrically connected to one pair of data lines, and the second multiplexing sub-circuit 4002 is electrically connected to another adjacent pair of data lines.

[0145] In an exemplary embodiment, as in Figure 9c shown, is an enlarged structural schematic diagram of Figure 8c The value of z can be 2. Each multiplexing circuit 40 can be electrically connected to two data lines DL in one pair of data lines, and is configured to time-divisionally provide the signal of a corresponding data output line DT to the corresponding two data lines DL under the control of two data selection lines MUX.

[0146] In an exemplary embodiment, as in Figures 10a to 10d shown, multiple sub-pixels can form M columns of sub-pixels, the number of data lines DL is M, the number of data output lines DT is k, the number of data selection lines is z, N, z, and k are all positive integers, k = N / z, and the value of z is greater than or equal to 2; multiple sub-pixels in the same column of sub-pixels are electrically connected to one of the data lines DL.

[0147] In an exemplary embodiment, Figures 10a to 10d shown is a single data line structure, where 10a to Figure 10b shown is a structural schematic diagram based on Single source mux 1:2, Figures 10c to 10dShown is a schematic structural diagram based on a Singlesource mux 1:4. In an exemplary embodiment, in Figure 10a and Figure 10c in the shown structure, there is no crossing among multiple second-type data output lines DT located in the display area AA; in Figure 10b and Figure 10d in the shown structure, among multiple second-type data output lines DT located in the display area AA, at least some have crossings.

[0148] In an exemplary embodiment, as Figure 11a shown, it is an enlarged structural diagram of Figure 10a . The value of z can be 2. Each multiplexing circuit 40 is electrically connected to two adjacent data lines DL, and is configured to time-divisionally provide the signal of a corresponding data output line DT to the corresponding two data lines DL under the control of two data selection lines.

[0149] In an exemplary embodiment, as Figure 11a and Figure 9c shown, when the value of z is 2, the two data selection lines may include a first data selection line MUX1 and a second data selection line MUX2; the multiplexing circuit may include a first multiplexing transistor MT1 and a second multiplexing transistor MT2;

[0150] The first pole c11 of the first multiplexing transistor MT1 and the first pole c12 of the second multiplexing transistor MT2 are electrically connected to one data output line DT. The second pole c21 of the first multiplexing transistor MT1 and the second pole c22 of the second multiplexing transistor MT2 are respectively electrically connected to two adjacent data lines DL located in the display area; the control pole of the first multiplexing transistor MT1 is electrically connected to the first data selection line MUX1, and the control pole of the second multiplexing transistor MT2 is electrically connected to the second data selection line MUX2.

[0151] In an exemplary embodiment, in the structure shown in Figure 9c , the same multiplexing circuit 40 can be electrically connected to two data lines DL in a pair of data lines DL; in the structure shown in Figure 11a , the same multiplexing circuit 40 can be electrically connected to two adjacent data lines DL.

[0152] In an exemplary embodiment, as Figure 11b shown, it is an enlarged structural diagram of the R1 position in Figure 10c , and as Figure 11c shown, it is Figure 10cAnother enlarged structural schematic diagram of the position of R1, where the value of z can be 4. Each multiplexing circuit 40 can be electrically connected to four adjacent data lines DL, and is configured to provide the corresponding one of the data output lines DT to the corresponding four data lines DL under the control of four data selection lines in a time-sharing manner.

[0153] In an exemplary embodiment, as Figure 11b and Figure 11c shown, the multiplexing circuit 40 can include a first multiplexing sub-circuit 4001 and a second multiplexing sub-circuit 4002. In the same multiplexing circuit 40, the first multiplexing sub-circuit is electrically connected to two adjacent data lines DL among the four adjacent data lines DL, and the second multiplexing sub-circuit is electrically connected to the other two adjacent data lines DL among the four adjacent data lines DL.

[0154] In an exemplary embodiment, as Figure 9a 、 Figure 9b and Figure 11b shown, the four data selection lines can include a first data selection line MUX1, a second data selection line MUX2, a third data selection line MUX3, and a fourth data selection line MUX4. At least some of the multiplexing circuits 40 can include a first multiplexing transistor MT1, a second multiplexing transistor MT2, a third multiplexing transistor MT3, a fourth multiplexing transistor MT4, a fifth multiplexing transistor MT5, and a sixth multiplexing transistor MT6. The first multiplexing sub-circuit 4001 can include the first multiplexing transistor MT1, the third multiplexing transistor MT3, and the fifth multiplexing transistor MT5, and the second multiplexing sub-circuit 4002 can include the second multiplexing transistor MT2, the fourth multiplexing transistor MT4, and the sixth multiplexing transistor MT6. In an exemplary embodiment, the first pole of the first multiplexing transistor MT1 and the first pole of the second multiplexing transistor MT2 are electrically connected to one of the data output lines DT. The second pole of the first multiplexing transistor MT1 is electrically connected to the first pole of the third multiplexing transistor MT3 and the first pole of the fifth multiplexing transistor MT5. The second pole of the second multiplexing transistor MT2 is electrically connected to the first pole of the fourth multiplexing transistor MT4 and the first pole of the sixth multiplexing transistor MT6. The second poles of the third multiplexing transistor MT3, the fourth multiplexing transistor MT4, the fifth multiplexing transistor MT5, and the sixth multiplexing transistor MT6 are electrically connected to four adjacent data lines DL in the display area AA. The control pole of the first multiplexing transistor MT1 is electrically connected to the first data selection line MUX1. The control pole of the second multiplexing transistor MT2 is electrically connected to the second data selection line MUX2. The control poles of the third multiplexing transistor MT3 and the fourth multiplexing transistor MT4 are electrically connected to the third data selection line MUX3. The control poles of the fifth multiplexing transistor MT5 and the sixth multiplexing transistor MT6 are electrically connected to the fourth data selection line MUX4.

[0155] In an exemplary embodiment, as Figure 9c , Figure 11c shown, the four data selection lines may include a first data selection line MUX1, a second data selection line MUX2, a third data selection line MUX3, and a fourth data selection line MUX4. At least a part of the multiplexing circuit 40 may include a first multiplexing transistor MT1, a second multiplexing transistor MT2, a third multiplexing transistor MT3, and a fourth multiplexing transistor MT4. The first multiplexing sub-circuit 4001 may include the first multiplexing transistor MT1 and the second multiplexing transistor MT2, and the second multiplexing sub-circuit 4002 may include the third multiplexing transistor MT3 and the fourth multiplexing transistor MT4. In an exemplary embodiment, the first poles of the first multiplexing transistor MT1 to the fourth multiplexing transistor MT4 are connected to each other and electrically connected to one of the data output lines DT, and the second poles of the first multiplexing transistor MT1 to the fourth multiplexing transistor MT2 are respectively electrically connected to four adjacent data lines DL; the control pole of the first multiplexing transistor MT1 is electrically connected to the first data selection line MUX1, the control pole of the second multiplexing transistor MT2 is electrically connected to the second data selection line MUX2, the control pole of the third multiplexing transistor MT3 is electrically connected to the third data selection line MUX3, and the control pole of the fourth multiplexing transistor MT4 is electrically connected to the fourth data selection line MUX4.

[0156] In an exemplary embodiment, as Figures 9a to 9c , Figure 11a and Figure 11b shown, the second type of data output line DT may include a first structural portion a1, a second structural portion a2, and a third structural portion a3 that are electrically connected in sequence, and the second structural portion a2 is located between the first structural portion a1 and the third structural portion a3;

[0157] The first structural portion a1 extends along the second direction Y and extends from the first border region B1 to the display region AA, and is located at one end of the first border region B1 away from the display region AA and is located between two adjacent first-type data output lines in the first direction X and is connected to the corresponding second-type driving pad, and is electrically connected to the second structural portion a2 at one end of the display region AA away from the first border region B1;

[0158] The second structural portion a2 is located in the display region AA and extends along the first direction X, and both ends of the second structural portion a2 are electrically connected to the first structural portion a1 and the third structural portion a3 respectively;

[0159] The third structural part a3 extends along the second direction Y and extends from the first border area B1 to the display area AA, and is connected to the second structural part a2 at one end of the display area AA away from the first border area B1, and is electrically connected to the corresponding second-type multiplexing circuit 42 at one end of the first border area B1 away from the display area AA.

[0160] In an exemplary embodiment, in the first direction X, one end of the second-type data output line DT connected to the driving circuit 20 may be located between two adjacent first-type data output lines DT. Figure 8a As shown in the figure, the second-type data output lines DT are inserted between two adjacent first-type data output lines DT in the first direction X in a reverse order, and there is no overlap between the plurality of second-type data output lines DT. For example, in the first border area B1, in the first direction X, the first data output line DT1 may be located between the fourth data output line DT4 and the fifth data output line DT5; the second data output line DT2 may be located between the third data output line DT3 and the fourth data output line DT4; the ninth data output line DT9 may be located between the seventh data output line DT7 and the eighth data output line DT8; the tenth data output line DT10 may be located between the sixth data output line DT6 and the seventh data output line DT7.

[0161] In an exemplary embodiment, as Figure 11a and Figure 12 shown, a bonding area 14 is provided on the side of the first border area B1 away from the display area AA. The first border area B1 may be referred to as a data pad DP (full English name: Data Pad, abbreviated as DP), and the second border area B2 may be referred to as a data pad opposite DPO (full English name: Data Pad Opposite, abbreviated as DPO).

[0162] In an exemplary embodiment, the display area AA may further include a plurality of scan signal lines GL extending along the first direction X and arranged at intervals along the second direction Y. N columns of sub-pixels Pxij form multiple rows, and the scan signal lines GL are connected to at least some of the sub-pixels in one row of sub-pixels Pxij, and are configured to provide a scan signal to the sub-pixels Pxij connected thereto.

[0163] In an exemplary embodiment, in Figure 9a , Figure 9b and Figure 11bIn the structure shown, the multiplexing circuit 40 may further include a first connection electrode c31, a second connection electrode c32, and a third connection electrode c33. The first poles c11 of the first multiplexing transistor MT1 and the first poles c12 of the second multiplexing transistor MT2 in the same multiplexing circuit 40 are electrically connected to the first connection electrode c31, and the first connection electrode c31 is electrically connected to the corresponding data output line DT. The first poles c13 of the third multiplexing transistor MT3 and the first poles c15 of the fifth multiplexing transistor MT5 are electrically connected to the second connection electrode c32, and the second connection electrode c32 is electrically connected to the second pole c21 of the first multiplexing transistor MT1. The first poles c14 of the fourth multiplexing transistor MT4 and the first poles c16 of the sixth multiplexing transistor MT6 are electrically connected to the third connection electrode c33, and the third connection electrode c33 is electrically connected to the second pole c22 of the second multiplexing transistor MT2.

[0164] In an exemplary embodiment, in Figure 9a , Figure 9b and Figure 11b In the structure shown, the multiple multiplexing circuits 40 in the multiplexing circuit 400 may be arranged in sequence along the first direction X; in the same multiplexing circuit 40, the second poles c26 of the sixth multiplexing transistor MT6, the second poles c24 of the fourth multiplexing transistor MT4, the second poles c25 of the fifth multiplexing transistor MT5, and the second poles c23 of the third multiplexing transistor MT3 may be arranged in sequence along the first direction X and are respectively electrically connected to four data lines DL in two adjacent pairs of data lines in the display area AA.

[0165] In an exemplary embodiment, in Figure 9a , Figure 9b and Figure 11bIn the structure shown, the second poles of the third to sixth multiplexing transistors MT3 to MT6 in the same multiplexing circuit 40 can be electrically connected to four adjacent data lines DL in the display area AA through four first vias V1. Among them, the third multiplexing transistor MT3 and the fifth multiplexing transistor MT5 in the first multiplexing sub-circuit are respectively electrically connected to two data lines DL in a pair of data lines DL, and the fourth multiplexing transistor MT4 and the sixth multiplexing transistor MT6 in the second multiplexing sub-circuit are respectively electrically connected to two data lines DL in a pair of data lines DL. For example, the four adjacent data lines DL electrically connected to the same multiplexing circuit 40 are two adjacent pairs of data lines. The third multiplexing transistor MT3 is electrically connected to the second data line DL2 in one pair of data lines DL, and the fifth multiplexing transistor MT5 is electrically connected to the first data line DL1 in this pair of data lines DL; the fourth multiplexing transistor MT4 is electrically connected to the second data line DL2 in the other pair of data lines DL, and the sixth multiplexing transistor MT6 is electrically connected to the first data line DL1 in this pair of data lines DL. In an exemplary embodiment, in the first direction X, the sixth multiplexing transistor MT6, the fourth multiplexing transistor MT4, the fifth multiplexing transistor MT5, and the third multiplexing transistor MT3 in the same multiplexing circuit 40 are sequentially electrically connected to four data lines DL in two adjacent pairs of data lines DL.

[0166] In an exemplary embodiment, when the second poles c26 of the sixth multiplexing transistor MT6, the second poles c24 of the fourth multiplexing transistor MT4, the second poles c25 of the fifth multiplexing transistor MT5, and the second poles c23 of the third multiplexing transistor MT3 are in the same conductive layer as the data lines DL, the second poles c26 of the sixth multiplexing transistor MT6, the second poles c24 of the fourth multiplexing transistor MT4, the second poles c25 of the fifth multiplexing transistor MT5, and the second poles c23 of the third multiplexing transistor MT3 can be an integrally formed structure with the corresponding data lines DL and do not need to be electrically connected through the first vias V1. In an exemplary embodiment, when the second poles c26 of the sixth multiplexing transistor MT6, the second poles c24 of the fourth multiplexing transistor MT4, the second poles c25 of the fifth multiplexing transistor MT5, and the second poles c23 of the third multiplexing transistor MT3 are not in the same conductive layer as the data lines DL, the second poles c26 of the sixth multiplexing transistor MT6, the second poles c24 of the fourth multiplexing transistor MT4, the second poles c25 of the fifth multiplexing transistor MT5, and the second poles c23 of the third multiplexing transistor MT3 can be electrically connected to the corresponding data lines DL through the first vias V1.

[0167] In an exemplary embodiment, in Figure 9a 、 Figure 9b and Figure 11bIn the structure shown, the first data selection line MUX1 can be electrically connected to the control electrodes of multiple first multiplexing transistors MT1 in the multiplexing circuit 400, the second data selection line MUX2 can be electrically connected to the control electrodes of multiple second multiplexing transistors MT2 in the multiplexing circuit 400, the third data selection line MUX3 can be electrically connected to the control electrodes of multiple third multiplexing transistors MT3 and multiple fourth multiplexing transistors MT4 in the multiplexing circuit 400, and the fourth data selection line MUX4 can be electrically connected to the control electrodes of multiple fifth multiplexing transistors MT5 and multiple sixth multiplexing transistors MT6 in the multiplexing circuit 400.

[0168] In an exemplary embodiment, as Figures 8a to 11b shown, the multiplexing circuit 400 can be located at a position adjacent to the first border region B1 and the display region AA. The data line DL is electrically connected to the corresponding multiplexing circuit 40 when it exits the display region AA, which can reduce the space occupied by the data line DL in the first border region B1 and reduce the size of the first border region B1 along the second direction Y.

[0169] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the second structural portion a2 and the data line DL are located in different conductive layers to avoid short circuits caused by the second structural portion a2 and the data line DL.

[0170] In an exemplary embodiment, the first structural portion a1 located in the display region, the third structural portion a3 located in the display region, and the data line DL can be located in the same conductive layer or in different conductive layers.

[0171] In an exemplary embodiment, the display substrate may include a substrate. In a direction Z perpendicular to the plane of the display substrate, multiple sub-pixels are disposed on one side of the substrate. At least one of the multiple sub-pixels includes a thin-film transistor, a planarization layer, and a light-emitting element. The planarization layer is located on the side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on the side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via hole. The thin-film transistor includes an active layer on the substrate, a gate on the side of the active layer away from the substrate, a source electrode and a drain electrode on the side of the gate away from the substrate, and a transfer electrode on the side of the source electrode and the drain electrode away from the substrate. One of the source electrode and the drain electrode is electrically connected to the transfer electrode through a via hole, and the transfer electrode is electrically connected to the light-emitting element through the first planarization layer via hole;

[0172] The second structural portion a2 can be disposed on the same layer as the source electrode and the drain electrode, and the data line DL can be disposed on the same layer as the transfer electrode. Alternatively, the second structural portion a2 can be disposed on the same layer as the transfer electrode, and the data line DL can be disposed on the same layer as the source electrode and the drain electrode.

[0173] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the display substrate may include a substrate, and an active layer, a first conductive layer (Gate1 layer, which may be referred to as a first gate conductive layer or a first gate metal layer), a second conductive layer (Gate2 layer, which may be referred to as a second gate conductive layer or a second gate metal layer), a third conductive layer (SD1 layer, which may be referred to as a first source-drain conductive layer or a first source-drain metal layer), and a fourth conductive layer (SD2 layer, which may be referred to as a second source-drain conductive layer or a second source-drain metal layer) disposed on the substrate.

[0174] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, a third gate conductive layer (Gate3 layer, which may be referred to as a third gate metal layer) may be disposed between the second conductive layer and the third conductive layer. In an exemplary embodiment, the active layer of the thin film transistor may be located at the active layer, the gate of the thin film transistor may be located at the first gate metal layer or at the third gate metal layer, the source and drain of the thin film transistor may be located at the first source-drain metal layer, and the transfer electrode of the thin film transistor may be located at the second source-drain metal layer.

[0175] In an exemplary embodiment, in Figures 8a to 11b the structure shown, the data selection line may be located at the first conductive layer, and the scan signal line GL may be located at the first conductive layer (Gate1 layer) or the second conductive layer (Gate2 layer).

[0176] In an exemplary embodiment, in Figures 8a to 11b the structure shown, the second structural portion a2 may be located at the third conductive layer, the data line DL may be located at the fourth conductive layer, or the second structural portion a2 may be located at the fourth conductive layer and the data line DL may be located at the third conductive layer.

[0177] In an exemplary embodiment, in a structure where the second structural portion a2 is disposed on the same layer as the source and drain, and the data line DL is disposed on the same layer as the transfer electrode: the first structural portion a1 located in the display area AA and the third structural portion a3 located in the display area AA may be disposed on the same layer as the source and drain and connected to the second structural portion a2; or the first structural portion a1 located in the display area AA and the third structural portion a3 located in the display area AA may be disposed on the same layer as the transfer electrode and connected to the second structural portion a2 through vias.

[0178] In an exemplary embodiment, in a structure in which the second structure portion a2 is arranged on the same layer as the switching electrode and the data line DL is arranged on the same layer as the source and drain: the first structure portion a1 located in the display area AA and the third structure portion a3 located in the display area AA may be arranged on the same layer as the switching electrode and connected to the second structure portion a2; or, the first structure portion a1 located in the display area AA and the third structure portion a3 located in the display area AA may be arranged on the same layer as the source and drain and connected to the second structure portion a2 through a via.

[0179] In an exemplary embodiment, the second structure portion a2 and the data line DL are located in different conductive layers, wherein the second structure portion a2, the third structure portion a3 located in the display area AA, and the first structure portion a1 located in the display area AA may be located in the same conductive layer and located in a different conductive layer from the data line DL; or the third structure portion a3 located in the display area AA and the first structure portion a1 located in the display area AA may be located in the same conductive layer, and the second structure portion a2 is located in another conductive layer. In an exemplary embodiment, the second structure portion a2 of the second type of data output line DT, the third structure portion a3 located in the display area AA, and the first structure portion a1 located in the display area AA may be located in the third conductive layer, and the data line DL may be located in the fourth conductive layer; or the data line DL, the third structure portion a3 located in the display area AA, and the first structure portion a1 located in the display area AA may be located in the fourth conductive layer, and the second structure portion a2 is located in the third conductive layer. In the structure in which the third structure portion a3 located in the display area AA and the first structure portion a1 located in the display area AA are located in the fourth conductive layer, as shown in FIG. 10, in the same first structure portion a1, the portion located in the display area and the portion located in the first border area B1 may be electrically connected through the fourth via hole V4; in the same third structure portion a3, the portion located in the display area and the portion located in the first border area B1 may be electrically connected through the fifth via hole V5.

[0180] In an exemplary embodiment, Figures 9a to 9c , Figure 11a and Figure 11bAs shown, the first frame area B1 may include a bending area; the first type of data output line DT and the second type of data output line DT located in the first frame area B1, in the same data output line DT, may include a first part b1, a second part b2 and a third part b3 electrically connected in sequence, wherein, in the plane where the display substrate is located, in the second direction Y, the second part b2 may be located in the bending area 12, the first part b1 may be located on the side of the bending area 12 close to the display area AA, and the third part b3 may be located on the side of the bending area 12 away from the display area AA. That is, the first structural portion a1 in the second type of data output line may include a first part b1, a second part b2 and a third part b3 electrically connected in sequence, and the first type of data output line may include a first part b1, a second part b2 and a third part b3 electrically connected in sequence.

[0181] In an exemplary embodiment, the first part b1 can be set in the same layer as the source and the drain, the second part b2 can be set in the same layer as the transfer electrode, and the third part b3 can be set in the same layer as the gate or in the same layer as the source and the drain; in the same data output line DT, the second part b2 can be electrically connected to the first part b1 through the second via V2, and the second part b2 can be electrically connected to the third part b3 through the third via V3.

[0182] In an exemplary embodiment, if Figure 11a As shown, from the direction of the display area AA to the first frame area B1, the first frame area B1 may include a multiplexing circuit area 15, a bending area 12, and a binding area 14 arranged in sequence; multiple multiplexing circuits 40 may be located in the multiplexing circuit area, and multiple driving pads 2001 are located in the binding area 14. The first part b1 extends from the multiplexing circuit area 15 to the bending area 12, and the third part b3 extends from the bending area 12 to the binding area 14 and is connected to the corresponding driving pad 2001. Figure 6 Compared with the structure shown in FIG. 1 , the first frame area B1 in FIG. 11a saves space for the first fan-out area 11 and the second fan-out area 13 , reduces the size of the first frame area B1 along the second direction Y (ie, reduces the width of the first frame area B1 ), and reduces the frame of the display substrate.

[0183] In an exemplary embodiment, the display substrate may include a substrate. A plurality of data lines DL and data selection lines MUX may be located on one side of the substrate. At least two data selection lines MUX may extend along a first direction X and be arranged at intervals along a second direction Y. A third structural portion a3 may be in a different conductive layer from the data selection lines MUX, and there is an overlap between the third structural portion a3 and the positive projections of at least two data selection lines MUX on the substrate. In an exemplary embodiment, when the value of z is 4, the first data selection line MUX1 to the fourth data selection line MUX4 may be located in the first conductive layer; when the value of z is 2, the first data selection line MUX1 to the second data selection line MUX2 may be located in the first conductive layer.

[0184] In an exemplary embodiment, in the structure where the value of z is 4, the first poles and second poles of the first multiplexing transistor MT1 to the sixth multiplexing transistor MT6, and the first connection electrode c31 to the third connection electrode c33 may be located in one of the third conductive layer, the fourth conductive layer, and the third gate conductive layer. In an exemplary embodiment, as Figure 12 shown, in the first direction X, the display substrate may include a third border region B3 and a fourth border region B4 located on both sides of the display region. The third border region B3 and the fourth border region B4 may include a first power supply line VDD and a plurality of gate driving circuits 50. The gate driving circuits 50 generally adopt a Gate Driver on Array (GOA) circuit. In the first direction X, in the border region (the third border region B3 or the fourth border region B4) on one side of the display region AA, the first power supply line VDD may be located between the gate driving circuit 50 and the display region AA, and the first power supply line VDD may extend along the extension direction of the border region where it is located. The plurality of gate driving circuits 50 may be arranged in sequence along the extension direction of the border region where they are located. In an exemplary embodiment, the gate driving circuit 50 may be electrically connected to at least one scanning signal line GL and be configured to provide a scanning signal to the scanning signal line GL electrically connected thereto.

[0185] In an exemplary embodiment, as Figure 12 shown, at least part of the gate driving circuits 50 may be arranged in the first border region B1 and the second border region B2. The first power supply line VDD may extend to the first border region B1 and the second border region B2. In the first border region B1, in the plane of the display substrate, in the second direction Y, the first power supply line VDD may be located between the display region AA and the bonding region 14. In the direction perpendicular to the plane of the display substrate, the positive projection of the first power supply line VDD on the substrate at least partially overlaps with the positive projection of the multiplexing circuit 400 on the substrate.

[0186] In an exemplary embodiment, asFigure 12 As shown, the first border region B1 may further include a second power supply line VSS. In the plane of the display substrate, in the second direction Y, the first power supply line VDD may be located between the display region AA and the bonding region 14. In the direction perpendicular to the plane of the display substrate, the positive projection of the first power supply line VDD on the substrate at least partially overlaps with the positive projection of the multiplexing circuit 400 on the substrate; in the first border region B1, in the first direction X, the second power supply line VSS may be located between two first power supply lines VDD.

[0187] In an exemplary embodiment, both the first power supply line VDD and the second power supply line VSS are electrically connected to the driving circuit 20. For example, both the first power supply line VDD and the second power supply line VSS being electrically connected to the driving circuit 20 may be electrically connected to the driving circuit 20 through the bonding region 14. In an exemplary embodiment, the first power supply line VDD and the second power supply line VSS may be located in the fourth conductive layer.

[0188] In an exemplary embodiment, the first poles of the first multiplexing transistor MT1 and the second multiplexing transistor MT2 may be electrically connected through the active layer. As Figure 13a and Figure 13b shown, Figure 13a is a schematic plan view of the second type of multiplexing circuit 42, Figure 13b is a schematic plan view of the first type of multiplexing circuit 41, and the active layers of the first multiplexing transistor MT1 to the sixth multiplexing transistor MT6 may be interconnected.

[0189] In an exemplary embodiment, as Figure 14a and Figure 14b shown, is a schematic cross-sectional view of the first border region B1, Figure 14a is Figure 13a a schematic cross-sectional view taken along the position A1 - A1 in Figure 14b is Figure 13a a schematic cross-sectional view taken along the position W1 - W2 in , where 101 is the substrate, 102 is the active layer, 103 is the first conductive layer, 104 is the third conductive layer, 105 is the fourth conductive layer, M1 is the first insulating layer, M2 is the second insulating layer, M3 is the third insulating layer and the first planarization layer.

[0190] In an exemplary embodiment, as Figures 7a to 12 shown, the second structural part a2 may be located on the side of the display region AA close to the first border region B1, minimizing the occlusion of the data output line DT on the display region AA and improving the transmittance of the display substrate.

[0191] In an exemplary embodiment, as Figures 7a to 12As shown, a plurality of sub-pixels Pxij form multiple rows, and the second structural part a2 may be located in at least one sub-pixel row on the side of the display area AA close to the first border area B1; or the second structural part a2 is located in at least one first spacer area on the side of the display area AA close to the first border area B1, and the first spacer area is the area between adjacent two rows of sub-pixels.

[0192] In an exemplary embodiment, as Figures 7a to 12 shown, in the first direction X, the second type multiplexing circuit 42 may be located on both sides of the first type multiplexing circuit 41. On the same side of the first median line O-O in the first direction X, the second type multiplexing circuit 42 is located on the side away from the first median line O-O of the first type multiplexing circuit 41, and the first median line O-O is the median line of the display area AA extending along the second direction Y.

[0193] In an exemplary embodiment, as Figure 8b 、 Figure 8d 、 Figure 10b and Figure 10d shown, on the same side of the first median line O-O in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the first structural parts a1 corresponding to the first to the last second type multiplexing circuits 42 are arranged in sequence, and the third structural parts a3 corresponding to the first to the last second type multiplexing circuits 42 are arranged in sequence.

[0194] In an exemplary embodiment, as Figure 8b 、 Figure 8d 、 Figure 10b and Figure 10d shown, on the same side of the first median line O-O in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the second structural parts a2 corresponding to the first to the last second type multiplexing circuits 42 are arranged in sequence along the direction from the first border area B1 to the display area AA, or are arranged in sequence along the direction from the display area AA to the first border area B1;

[0195] On the same side of the first median line O-O in the first direction X, in the direction from the display area AA to the first border area B1, the third structural part a3 corresponding to the second structural part a2 away from the first border area B1 at least partially overlaps with the positive projection of the second structural part a2 close to the first border area B1 on the substrate, and the second structural part a2 and the third structural part a3 are located in different conductive layers.

[0196] In an exemplary embodiment, as Figure 7a 、Figure 7b , Figure 8a , Figure 8c , Figure 10a and Figure 10c As shown in Figure 7b , Figure 8a , Figure 8c , Figure 10a and Figure 10c , on the same side of the first median line O-O in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the first structural parts a1 corresponding to the last second type multiplexing circuit 42 to the first structural parts a1 corresponding to the first second type multiplexing circuit 42 are arranged in sequence, and the third structural parts a3 corresponding to the first second type multiplexing circuit 42 to the third structural parts a3 corresponding to the last second type multiplexing circuit 42 are arranged in sequence.

[0197] In an exemplary embodiment, as Figure 7a , Figure 7b , Figure 8a , Figure 8c , Figure 10a and Figure 10c As shown in Figure 7a , Figure 7b , Figure 8a , Figure 8c , Figure 10a and Figure 10c , on the same side of the first median line O-O in the first direction X, in the direction from the second type multiplexing circuit 42 to the first type multiplexing circuit 41, the second structural parts a2 corresponding to the last to the first second type multiplexing circuit 42 are arranged in sequence along the direction from the first border region B1 to the display region AA;

[0198] On the same side of the first median line O-O in the first direction X, in the direction from the display region AA to the first border region B1, the third structural part a3 corresponding to the second structural part a2 far from the first border region B1 does not overlap with the positive projection of the second structural part a2 close to the first border region B1 on the substrate, and the second structural part a2 and the third structural part a3 are located in different conductive layers or the same conductive layer.

[0199] In an exemplary embodiment, as Figure 8a and Figure 8b As shown in Figure 8a and Figure 8b , there are two schematic structural diagrams based on dual source mux 1:4. Among them, Figure 8a The second type of data output line DT is inserted in reverse order, Figure 8b As shown in Figure 8b , the second type of data output line DT is inserted in forward order. In an exemplary embodiment, as Figure 8c and Figure 8d As shown in Figure 8c and Figure 8d , there are two schematic structural diagrams based on dual source mux 1:2. Among them, Figure 8c The second type of data output line DT is inserted in reverse order, Figure 8d As shown in Figure 8d , the second type of data output line DT is inserted in forward order.

[0200] In an exemplary embodiment, as Figures 10a to 10bAs shown, there are schematic diagrams of two structures based on Single source MUX 1:2. Among them, Figure 10a The second type of data output line DT is inserted in the reverse order. Figure 10b As shown, the second type of data output line DT is inserted in the forward order. In the single data line structure, multiple sub-pixels in a column of sub-pixels are electrically connected to one of the data lines DL. In an exemplary embodiment, as Figures 10c to 10d As shown, there are schematic diagrams of two structures based on Single source MUX 1:4. Among them, Figure 10c The second type of data output line DT is inserted in the reverse order. Figure 10d As shown, the second type of data output line DT is inserted in the forward order. In the single data line structure, multiple sub-pixels in a column of sub-pixels are electrically connected to one of the data lines DL.

[0201] In an exemplary embodiment, as Figure 9a , Figure 9b , Figure 11a and Figure 11b As shown, the data line DL is electrically connected to the corresponding multiplexing circuit 40 when it exits the display area AA. Compared with the structure shown in Figure 6 , the size of the first fan-out area 11 in the second direction Y is reduced; the lines of the first part b1 pass through the second part b2 and are connected to the corresponding third part b3. The first part b1 and the third part b3 are basically straight lines extending along the second direction Y, which can further reduce the size of the first border area B1 in the second direction Y; in addition, compared with Figure 6 , the third part b3 is basically a straight line pulled down to the bonding area (the area bonded to the driving circuit 20), and there is no need to set a second fan-out area 13 with too large a size as shown in Figure 6 , saving the space of the second fan-out area 13. That is, compared with Figure 6 , Figure 9a , Figure 9b , Figure 11a and Figure 11b In the shown structure, the sizes of the first fan-out area 11 and the second fan-out area 13 in the second direction Y are reduced a lot, greatly reducing the size of the first border area B1 in the second direction Y and reducing the width of the first border area B1.

[0202] In an exemplary embodiment, as Figure 15 As shown, there is a cross-sectional structure diagram of the position of the second structural part a2 in the display area AA. In the direction Z perpendicular to the plane of the display substrate, a second planar layer M4 and a pixel definition layer PDL are further provided on the side of the fourth conductive layer 105 away from the substrate 101. The pixel definition layer PDL is located on the side of the second planar layer M4 away from the fourth conductive layer 105. In Figure 15In the structure shown, the data line DL is located in the fourth conductive layer 105, the second structural part a2 is located in the third conductive layer 104, and the first structural part a1 and the third structural part a3 in the display area AA are located in the third conductive layer 104.

[0203] In an exemplary embodiment, as Figure 16 shown, it is another cross-sectional structure diagram of the position of the second structural part a2 in the display area AA. Figure 16 Compared with Figure 15 the difference is that: in the structure shown in Figure 16 in the display area AA, the third structural part a3 and the first structural part a1 are located in the fourth conductive layer 105, and the third structural part a3 and the first structural part a1 can be electrically connected to the corresponding second structural part a2 in the third conductive layer 104 through vias.

[0204] In an exemplary embodiment, as Figure 17 shown, it is another cross-sectional structure diagram of the position of the second structural part a2 in the display area AA. Figure 17 Compared with Figure 15 the difference is that: in the structure shown in Figure 17 in the display area AA, the second structural part a2, the third structural part a3, and the first structural part a1 are located in the fourth conductive layer 105, and the data line DL is located in the third conductive layer 104.

[0205] In an exemplary embodiment, as Figure 18 shown, it is another cross-sectional structure diagram of the position of the second structural part a2 in the display area AA. Figure 18 Compared with Figure 17 the difference is that: in the structure shown in Figure 18 in the display area AA, the third structural part a3 and the first structural part a1 are located in the third conductive layer 104, and the third structural part a3 and the first structural part a1 are electrically connected to the corresponding second structural part a2 through vias.

[0206] In an exemplary embodiment, as Figures 19a to 19d shown, Figures 19a to 19c it is Figure 9d and Figure 11c a schematic plan view of the second type of multiplexing circuit 42 in Figure 19d it is Figure 9d and Figure 11c a schematic plan view of the first type of multiplexing circuit 41 in. In the structure shown in Figures 19c to 19d among the first to fourth multiplexing transistors MT1 to MT4, each transistor is composed of two transistors in parallel, which can increase the output capacity and improve the output stability. In Figure 19aAmong them, AT1 is the active layer of the first multiplexing transistor MT1, AT2 is the active layer of the second multiplexing transistor MT2, AT3 is the active layer of the third multiplexing transistor MT3, and AT4 is the active layer of the fourth multiplexing transistor MT4.

[0207] In an exemplary embodiment, as Figure 20 shown, it is a partial cross-sectional schematic diagram of the display area of the display panel of at least one embodiment of the present disclosure. Figure 20 In this example, the structure of a sub-pixel in the display area is taken as an example for illustration. In this example, it is assumed that the types of multiple transistors in the pixel circuit are the same. For example, multiple transistors in the pixel circuit can all use low-temperature polysilicon thin-film transistors or all use oxide thin-film transistors. In some other examples, multiple transistors in the pixel circuit can use low-temperature polysilicon thin-film transistors and oxide thin-film transistors. Additionally, in this example, the display panel can integrate a mutual capacitance touch structure to form an FMLOC structure.

[0208] In some examples, as Figure 20 shown, in the direction perpendicular to the display panel, the display area of the display panel can include: a substrate 101 (which can be referred to as a base), and a circuit structure layer 200, a light-emitting structure layer 300, a packaging structure layer 400, a touch structure layer 500, and a color filter layer 600 that are sequentially disposed on the substrate 101. Among them, the display structure layer can at least include the circuit structure layer 200 and the light-emitting structure layer 300. The circuit structure layer 200 can at least include: pixel circuits of multiple sub-pixels, and the pixel circuit of each sub-pixel can include multiple transistors and at least one capacitor. The light-emitting structure layer 300 can at least include: light-emitting elements of multiple sub-pixels.

[0209] In some examples, Figure 20Taking an example that each sub-pixel includes a thin film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 200 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 101. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first insulating layer M1 (which can be called the first gate insulating layer) may be disposed between the semiconductor layer and the first gate metal layer, a second gate insulating layer M02 may be disposed between the first gate metal layer and the second gate metal layer, an interlayer insulating layer M2 (which can be called the above-mentioned second insulating layer) may be disposed between the second gate metal layer and the first source-drain metal layer, a passivation layer M31 (which can be called the third insulating layer) and a first planarization layer M32 may be disposed between the first source-drain metal layer and the second source-drain metal layer, a second planarization layer M4 may be disposed between the second source-drain metal layer and the third source-drain metal layer, and a third planarization layer M5 may be disposed on the side of the third source-drain metal layer away from the substrate 101. Among them, the first insulating layer M1 (which can be called the first gate insulating layer), the second gate insulating layer M02, the interlayer insulating layer M2, and the passivation layer M31 may be inorganic insulating layers, and the first planarization layer M32, the second planarization layer M4, and the third planarization layer M5 may be organic insulating layers. However, this embodiment is not limited thereto. In some other examples, a buffer layer may also be disposed on the side of the semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the inside of the display panel and can also increase the adhesion of the film layers in the display panel to the substrate. In some other examples, a bottom shielding metal layer (BSM, Bottom Shielding Metal) may be disposed on the side of the buffer layer close to the substrate. The bottom shielding metal layer may be configured to at least partially cover the active layer of the thin film transistor of the pixel circuit to avoid the influence of external light on the performance of the thin film transistor. In some other examples, the passivation layer may be omitted between the first source-drain metal layer and the second source-drain metal layer, and only the first planarization layer may be disposed between the first source-drain metal layer and the second source-drain metal layer.

[0210] In some examples, such as Figure 20As shown, the semiconductor layer of the display region may at least include: the active layer 210 of the thin film transistor 21. The active layer 210 of the thin film transistor 21 may include: a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may at least include: the gate 213 of the thin film transistor 21, and the first electrode plate 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin film transistor 21 on the substrate 101 may cover the orthographic projection of the channel region 2100 of the active layer 210 on the substrate 101. The second gate metal layer may at least include: the second electrode plate 222 of the capacitor 22. The orthographic projections of the second electrode plate 222 and the first electrode plate 221 of the capacitor 22 on the substrate 101 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may at least include: the source 211 and the drain 212 of the thin film transistor 21. The interlayer insulating layer M2 may be provided with a plurality of vias (for example, including a first pixel via and a second pixel via) in the display region. The interlayer insulating layer M2, the second gate insulating layer M02, and the first gate insulating layer M1 in the first pixel via may be removed to expose at least a part of the surface of the first region 2101 of the active layer 210; the interlayer insulating layer M2, the second gate insulating layer M02, and the first gate insulating layer M1 in the second pixel via may be removed to expose at least a part of the surface of the second region 2102 of the active layer 210. The source 211 of the thin film transistor 21 may be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 may be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may at least include: a first transfer electrode 231. The first transfer electrode 231 may be electrically connected to the drain 212 of the thin film transistor 21 of the pixel circuit through a third pixel via opened by the passivation layer M31 and the first planarization layer M32. The third source-drain metal layer may at least include: a second transfer electrode 232 (the transfer electrodes described above may include the first transfer electrode 231 and the second transfer electrode 232). The second transfer electrode 232 may be electrically connected to the first transfer electrode 231 located in the second source-drain metal layer through a fourth pixel via opened by the second planarization layer M4. The second transfer electrode 232 may be electrically connected to the first electrode 301 (for example, the anode) of the light-emitting element through a fifth pixel via opened by the third planarization layer M5. In this example, the electrical connection between the pixel circuit and the light-emitting element may be realized through the first transfer electrode 231 and the second transfer electrode 232.

[0211] In some examples, the gate lines of the display area may be located in the first gate metal layer, for example. The data lines of the display area may be located in the second source-drain metal layer or the third source-drain metal layer, for example. The high-potential power supply line (which may be the first power supply line VDD, for example) of the display area may be located in at least one of the second source-drain metal layer and the third source-drain metal layer. This embodiment is not limited thereto. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging a large number of traces in a single source-drain metal layer, thereby facilitating the implementation of a narrow border structure.

[0212] In some examples, as Figure 20 shown, the light-emitting structure layer 300 may include: a pixel definition layer 304 and a plurality of light-emitting elements. For example, each light-emitting element may include: a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element may be an anode. The first electrode 301 may be disposed on the third planar layer 107 and is electrically connected to the second transfer electrode 232 through a fifth pixel via formed in the third planar layer M5. The pixel definition layer 304 is disposed on the first electrode 301 and the third planar layer M5. The pixel definition layer 304 may be provided with a plurality of pixel openings, and at least a part of the surface of a corresponding first electrode 301 may be exposed through one pixel opening. At least a part of the organic light-emitting layer 302 may be disposed in one pixel opening and is connected to the corresponding first electrode 301. The second electrode 303 may be disposed on the organic light-emitting layer 302 and is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation column layer may also be disposed on the side of the pixel definition layer 304 away from the substrate 101, and the isolation column layer may include a plurality of isolation columns (PS).

[0213] In some examples, the organic light-emitting layer 302 of the light-emitting element may include a light-emitting layer (EML, Emitting Layer), and one or more film layers including a hole injection layer (HIL, Hole Injection Layer), a hole transport layer (HTL, Hole Transport Layer), a hole block layer (HBL, Hole Block Layer), an electron block layer (EBL, Electron Block Layer), an electron injection layer (EIL, Electron Injection Layer), and an electron transport layer (ETL, Electron Transport Layer). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting characteristics of the organic material can be used to emit light according to the required gray level.

[0214] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce the process difficulty and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may use a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may use a common layer. In some examples, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer may be fabricated by a single process (a single evaporation process or a single inkjet printing process), and isolation may be achieved by the surface step difference of the formed film layer or by means such as surface treatment. For example, any one or more of the hole injection layer, the hole transport layer, the electron injection layer, and the electron transport layer corresponding to adjacent sub-pixels may be isolated. In some examples, the organic light-emitting layer may be formed by evaporation using a fine metal mask (FMM) or an open mask, or formed by an inkjet process.

[0215] In some examples, as shown in FIG. 19, the encapsulation structure layer 400 may include a stacked first encapsulation layer 4001, a second encapsulation layer 4002, and a third encapsulation layer 4003. Among them, the first encapsulation layer 4001 and the third encapsulation layer 4003 may use inorganic materials, the second encapsulation layer 4002 may use an organic material, and the second encapsulation layer 4002 may be disposed between the first encapsulation layer 4001 and the third encapsulation layer 4003 to ensure that external moisture cannot enter the light-emitting element. However, this embodiment is not limited thereto. For example, the encapsulation structure layer may adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0216] Embodiments of the present disclosure also provide a display device, as Figure 21 shown, the display device may include: a display substrate.

[0217] The display substrate is the display substrate provided in any of the foregoing embodiments, and the implementation principle and implementation effect are similar, and will not be described in detail herein.

[0218] In an exemplary embodiment, the display device may be a liquid crystal display device (LCD for short), an organic light emitting diode (OLED for short), or a light emitting diode (LED for short) display device. The display device may be any product or component with a display function, such as a liquid crystal panel, an electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED for short) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0219] The display substrate and the display device provided by the embodiments of the present disclosure. The display substrate includes a display area and a first border area located on one side of the display area. The display area includes a plurality of sub-pixels and a plurality of data lines. The first border area includes a plurality of multiplexing circuits and a plurality of driving pads. The display substrate further includes a plurality of data output lines. Among them, the plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines. The plurality of multiplexing circuits include a plurality of first-type multiplexing circuits and a plurality of second-type multiplexing circuits. In a first direction, the plurality of first-type multiplexing circuits are located between the plurality of second-type multiplexing circuits; the plurality of first-type data output lines are located in the first border area and extend along a second direction; one end of each first-type data output line close to the display area is electrically connected to the corresponding first-type multiplexing circuit, and the other end far from the display area is connected to the corresponding first-type driving pad; at least a partial segment of each second-type data output line is located in the display area, one end of each second-type data output line is electrically connected to the corresponding second-type multiplexing circuit, and the other end is located in the first border area and is connected to the corresponding second-type driving pad. The display substrate provided by the embodiments of the present disclosure can reduce the size of the first border area in the column direction and can overcome the technical problem of great difficulty in narrowing the border of the display substrate.

[0220] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0221] Without conflict, the features in the embodiments of the present disclosure, i.e., the embodiments, can be combined with each other to obtain new embodiments.

[0222] Although the embodiments disclosed in the present disclosure are as described above, the content described is only an embodiment adopted for the convenience of understanding the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art within the field to which the present disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the present disclosure. However, the scope of patent protection of the present disclosure shall still be subject to the scope defined by the appended claims.

Claims

1. A display substrate, characterized in that, It includes a display area and a first border area located on one side of the display area; A plurality of sub-pixels, located in the display area; A plurality of data lines, located in the display area and electrically connected to the plurality of sub-pixels, and the plurality of data lines are configured to provide data signals to the plurality of sub-pixels; A plurality of data output lines, electrically connected to the plurality of data lines; A plurality of multiplexing circuits, located in the first border area, each of the plurality of multiplexing circuits is electrically connected to one of the plurality of data output lines and at least two of the plurality of data lines, and each of the multiplexing circuits is configured to time-divisionally provide the signal provided by the one data output line to the at least two data lines; A plurality of driving pads, located in the first border area and on the side of the plurality of multiplexing circuits away from the display area, the plurality of driving pads include a plurality of first-type driving pads and a plurality of second-type driving pads, and the plurality of second-type driving pads are located between the plurality of first-type driving pads; Wherein, the plurality of data output lines include a plurality of first-type data output lines and a plurality of second-type data output lines, the plurality of multiplexing circuits include a plurality of first-type multiplexing circuits and a plurality of second-type multiplexing circuits, in a first direction, the plurality of first-type multiplexing circuits are located between the plurality of second-type multiplexing circuits; the plurality of first-type data output lines are located in the first border area and extend along a second direction, and the first direction and the second direction intersect; one end of each of the first-type data output lines close to the display area is electrically connected to the corresponding first-type multiplexing circuit, and the end away from the display area is connected to the corresponding first-type driving pad; at least a partial segment of each of the second-type data output lines is located in the display area, one end of each of the second-type data output lines is electrically connected to the corresponding second-type multiplexing circuit, and the other end is located in the first border area and is connected to the corresponding second-type driving pad.

2. The display substrate according to claim 1, wherein The second-type data output line includes a first structural portion, a second structural portion and a third structural portion that are electrically connected in sequence, and the second structural portion is located between the first structural portion and the third structural portion; The first structural portion extends along the second direction and extends from the first border area to the display area, and one end of the first structural portion located in the display area away from the first border area is electrically connected to the second structural portion, and one end of the first structural portion located in the first border area away from the display area is located between two adjacent first-type data output lines in the first direction; The second structural portion is located in the display area and extends along the first direction, and both ends of the second structural portion are electrically connected to the first structural portion and the third structural portion respectively; The third structural part extends along the second direction and extends from the first border region to the display region. It is connected to the second structural part at one end of the display region away from the first border region, and is electrically connected to the corresponding second-type multiplexing circuit at one end of the first border region away from the display region.

3. The display substrate according to claim 2, wherein In a direction perpendicular to the plane of the display substrate, the second structural part and the data line are located in different conductive layers.

4. The display substrate according to claim 3, wherein The first structural part located in the display region, the third structural part located in the display region, and the data line are located in the same conductive layer or in different conductive layers.

5. The display substrate according to claim 4, wherein The display substrate includes a substrate. In a direction perpendicular to the plane of the display substrate, the plurality of sub-pixels are disposed on one side of the substrate. At least one of the plurality of sub-pixels includes a thin-film transistor, a planarization layer, and a light-emitting element. The planarization layer is located on a side of the thin-film transistor away from the substrate to cover the thin-film transistor. The light-emitting element is located on a side of the planarization layer away from the substrate. The planarization layer includes a first planarization layer via. The thin-film transistor includes an active layer on the substrate, a gate on a side of the active layer away from the substrate, a source electrode and a drain electrode on a side of the gate away from the substrate, and a transfer electrode on a side of the source electrode and the drain electrode away from the substrate. One of the source electrode and the drain electrode is electrically connected to the transfer electrode through a via, and the transfer electrode is electrically connected to the light-emitting element through the first planarization layer via. The second structural part is provided on the same layer as the source electrode and the drain electrode, and the data line is provided on the same layer as the transfer electrode, or the second structural part is provided on the same layer as the transfer electrode, and the data line is provided on the same layer as the source electrode and the drain electrode.

6. The display substrate according to claim 5, wherein In the structure where the second structural part is provided on the same layer as the source electrode and the drain electrode, and the data line is provided on the same layer as the transfer electrode: the first structural part located in the display region, the third structural part located in the display region are provided on the same layer as the source electrode and the drain electrode and are connected to the second structural part; or the first structural part located in the display region, the third structural part located in the display region are provided on the same layer as the transfer electrode and are connected to the second structural part through a via.

7. The display substrate according to claim 5, wherein In the structure where the second structural part is provided on the same layer as the transfer electrode, and the data line is provided on the same layer as the source electrode and the drain electrode: the first structural part located in the display region, the third structural part located in the display region are provided on the same layer as the transfer electrode and are connected to the second structural part; or the first structural part located in the display region, the third structural part located in the display region are provided on the same layer as the source electrode and the drain electrode and are connected to the second structural part through a via.

8. The display substrate according to claim 5, characterized in that, The first border region includes a bending area; Among the first structural part and the data output lines of the first type located in the first border area, in the same data output line, it includes a first part, a second part, and a third part that are electrically connected in sequence. Among them, in the plane where the display substrate is located, in the second direction, the second part is located in the bending area, the first part is located on the side of the bending area close to the display area, and the third part is located on the side of the bending area far from the display area.

9. The display substrate according to claim 8, wherein The first part is arranged on the same layer as the source electrode and the drain electrode, the second part is arranged on the same layer as the transfer electrode, and the third part is arranged on the same layer as the gate electrode or on the same layer as the source electrode and the drain electrode; In the same data output line, the second part is electrically connected to the first part through a second via, and the second part is electrically connected to the third part through a third via.

10. The display substrate according to claim 8, wherein In the direction from the display area to the first border area, the first border area includes a multiplexing circuit area, the bending area, and a bonding area arranged in sequence; the plurality of multiplexing circuits are located in the multiplexing circuit area, and the plurality of driving pads are located in the bonding area; the first part extends from the multiplexing circuit area to the bending area, and the third part extends from the bending area to the bonding area.

11. The display substrate according to claim 2, wherein The second structural part is located on the side of the display area close to the first border area; the display substrate includes a substrate, and in the direction perpendicular to the plane where the display substrate is located, the second structural part is arranged on one side of the substrate.

12. The display substrate according to claim 11, wherein The plurality of sub-pixels form multiple rows, and the second structural part is located in at least one sub-pixel row on the side of the display area close to the first border area; or the second structural part is located in at least one first interval area on the side of the display area close to the first border area, and the first interval area is the area between adjacent two rows of sub-pixels.

13. The display substrate according to claim 12, wherein, On the same side of the first median line in the first direction, the second type of multiplexing circuit is located on the side far from the first median line of the first type of multiplexing circuit, and the first median line is the median line along which the display area extends in the second direction.

14. The display substrate according to claim 13, wherein On the same side of the first median line in the first direction, in the direction from the second type of multiplexing circuit to the first type of multiplexing circuit, the first structural parts corresponding to the first second type of multiplexing circuit to the last second type of multiplexing circuit are arranged in sequence, and the third structural parts corresponding to the first second type of multiplexing circuit to the last second type of multiplexing circuit are arranged in sequence.

15. The display substrate according to claim 14, wherein On the same side of the first median line in the first direction, in the direction from the second type of multiplexing circuit to the first type of multiplexing circuit, the second structural parts corresponding to the first to last second type of multiplexing circuit are arranged in sequence along the direction from the first border area to the display area, or arranged in sequence along the direction from the display area to the first border area; On the same side of the first median line in the first direction, in the direction pointing from the display area to the first border area, the third structural part corresponding to the second structural part far from the first border area and the second structural part close to the first border area have at least partial overlap in the orthographic projection on the substrate, and the second structural part and the third structural part are located in different conductive layers.

16. The display substrate according to claim 13, wherein On the same side of the first median line in the first direction, in the direction pointing from the second type of multiplexing circuit to the first type of multiplexing circuit, the first structural parts corresponding to the last second type of multiplexing circuit to the first structural parts corresponding to the first second type of multiplexing circuit are arranged in sequence, and the third structural parts corresponding to the first second type of multiplexing circuit to the third structural parts corresponding to the last second type of multiplexing circuit are arranged in sequence.

17. The display substrate according to claim 16, wherein On the same side of the first median line in the first direction, in the direction pointing from the second type of multiplexing circuit to the first type of multiplexing circuit, the second structural parts corresponding to the last to the first second type of multiplexing circuit are arranged in sequence along the direction pointing from the first border area to the display area; On the same side of the first median line in the first direction, in the direction pointing from the display area to the first border area, the third structural part corresponding to the second structural part far from the first border area and the second structural part close to the first border area do not overlap in the orthographic projection on the substrate, and the second structural part and the third structural part are located in different conductive layers or the same conductive layer.

18. The display substrate according to any one of claims 2 to 17, characterized in that, Further comprising: At least two data selection lines: located in the first border area; Wherein, the multiplexing circuit is electrically connected to the at least two data selection lines, and each multiplexing circuit is configured to provide the signal of one data output line to the at least two data lines in a time-division manner under the control of the at least two data selection lines.

19. The display substrate according to claim 18, wherein The display substrate includes a substrate, the plurality of data lines and the data selection lines are located on one side of the substrate, and the at least two data selection lines extend along the first direction and are arranged at intervals along the second direction; The third structural part and the data selection line are located in different conductive layers, and there is an overlap between the third structural part and the orthographic projection of the at least two data selection lines on the substrate.

20. The display substrate according to claim 18, wherein The number of the data lines is M, the number of the data output lines is k, the number of the data selection lines is z, k = M / z, both M and k are positive integers, and z is an integer greater than or equal to 2; Each multiplexing circuit is electrically connected to adjacent z data lines and is configured to provide the signal of the one data output line to the corresponding z data lines in a time-division manner under the control of z data selection lines.

21. The display substrate according to claim 20, wherein The plurality of sub-pixels form N columns of sub-pixels, the M data lines include N pairs of data lines, at least one pair of data lines includes a first data line and a second data line, k = 2N / z, N is a positive integer, and M = 2N; Among multiple sub-pixels located in the same column of sub-pixels, two adjacent sub-pixels are electrically connected to the first data line and the second data line in a pair of data lines respectively.

22. The display substrate according to claim 21, wherein The value of z is 4, and each of the multiplexing circuits is electrically connected to four data lines in two adjacent pairs of data lines, and is configured to provide the signal of the one data output line to the corresponding four data lines in a time-division manner under the control of four data selection lines.

23. The display substrate according to claim 22, wherein The multiplexing circuit includes a first multiplexing sub-circuit and a second multiplexing sub-circuit; in the same multiplexing circuit, the first multiplexing sub-circuit is electrically connected to one pair of data lines, and the second multiplexing sub-circuit is electrically connected to another adjacent pair of data lines.

24. The display substrate according to claim 23, wherein The four data selection lines include a first data selection line, a second data selection line, a third data selection line, and a fourth data selection line. The first multiplexing sub-circuit includes a first multiplexing transistor, a third multiplexing transistor, and a fifth multiplexing transistor. The second multiplexing sub-circuit includes a second multiplexing transistor, a fourth multiplexing transistor, and a sixth multiplexing transistor; The first pole of the first multiplexing transistor and the first pole of the second multiplexing transistor are electrically connected to one of the data output lines. The second pole of the first multiplexing transistor is electrically connected to the first pole of the third multiplexing transistor and the first pole of the fifth multiplexing transistor. The second pole of the second multiplexing transistor is electrically connected to the first pole of the fourth multiplexing transistor and the first pole of the sixth multiplexing transistor. The second poles of the third multiplexing transistor, the fourth multiplexing transistor, the fifth multiplexing transistor, and the sixth multiplexing transistor are electrically connected to four adjacent data lines in the display area. The control pole of the first multiplexing transistor is electrically connected to the first data selection line. The control pole of the second multiplexing transistor is electrically connected to the second data selection line. The control poles of the third multiplexing transistor and the fourth multiplexing transistor are electrically connected to the third data selection line. The control poles of the fifth multiplexing transistor and the sixth multiplexing transistor are electrically connected to the fourth data selection line.

25. The display substrate according to claim 21, wherein The value of z is 2, and each of the multiplexing circuits is electrically connected to two data lines in one pair of data lines, and is configured to provide the signal of the one data output line to the corresponding two data lines in a time-division manner under the control of two data selection lines.

26. The display substrate according to claim 20, wherein The multiple sub-pixels form M columns of sub-pixels, and the multiple sub-pixels located in the same column of sub-pixels are electrically connected to one of the data lines.

27. The display substrate according to claim 26, wherein The value of z is 2, and each of the multiplexing circuits is electrically connected to two adjacent data lines, and is configured to provide the signal of the one data output line to the corresponding two data lines in a time-division manner under the control of two data selection lines.

28. The display substrate according to claim 26 or 27, characterized in that, The two data selection lines include a first data selection line and a second data selection line, and the multiplexing circuit includes a first multiplexing transistor and a second multiplexing transistor; The first pole of the first multiplexing transistor and the first pole of the second multiplexing transistor are electrically connected to one of the data output lines, and the second pole of the first multiplexing transistor and the second pole of the second multiplexing transistor are respectively electrically connected to two adjacent data lines in the display area; the control pole of the first multiplexing transistor is electrically connected to the first data selection line, and the control pole of the second multiplexing transistor is electrically connected to the second data selection line.

29. A display device, characterized in that, A display substrate including the display substrate according to any one of claims 1 to 28.

Images