Array substrate and liquid crystal display device
By setting a slotted area on the common electrode layer to reduce parasitic capacitance, the display abnormalities and uneven problems caused by parasitic capacitance inside the array substrate are solved, and a more uniform display effect is achieved and light leakage is avoided.
Patent Information
- Application Number
- CN202422515172.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-17
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-10-17
AI Technical Summary
The parasitic capacitance inside the array substrate causes color display abnormalities and poor problems such as Mura on the LCD panel.
The first set of slotted regions are formed on the common electrode layer to reduce parasitic capacitance between the common electrode layer and the SD layer, and an electric field is formed between the common electrode layer and the pixel electrode layer to promote liquid crystal flip, by providing the first and second sets of slotted regions are covered by the black matrix layer and the pixel electrode layer, respectively.
Effectively reduce parasitic capacitance, reduce load, improve display unevenness, and avoid light leakage.
Smart Images
Figure CN223139999U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of film layer structures of display panels, and particularly relates to an array substrate and a liquid crystal display device. Background Art
[0002] With the development of liquid crystal display technology, narrow-bezel display screens have become the main trend in the development of high-quality display screens due to their advantages such as simplicity, beauty, and large visible area for the same size. A liquid crystal display panel mainly drives the deflection of liquid crystal molecules by forming a voltage difference between a pixel electrode and a common electrode on an array substrate, thereby emitting light of different brightnesses for image display.
[0003] However, there are many parasitic capacitances inside the array substrate. Parasitic capacitances exist between the data line and the liquid crystal, between the data lines, and between the data line and the scan line. This causes the data voltage to be affected by the parasitic capacitance when controlling the deflection of the liquid crystal, resulting in the emitted brightness being different from the preset brightness and affecting the normal display of the display panel. For example, an excessive parasitic capacitance may cause problems such as abnormal color display and Mura during the display process of the panel.
[0004] In order to effectively improve and avoid some abnormal display images, it is necessary to control the magnitude of the parasitic capacitance inside the array substrate. Summary of the Utility Model
[0005] In the existing liquid crystal display panel, the parasitic capacitance inside the array substrate may cause problems such as abnormal color display and Mura in the display panel.
[0006] To address the above problems, an array substrate and a liquid crystal display device are proposed. By forming a first set of slotted areas on the common electrode layer, the parasitic capacitance between the common electrode layer and the SD layer can be effectively reduced, the load can be decreased, and the problem of uneven display caused by the parasitic capacitance can be improved. Moreover, the first set of slotted areas and the second set of slotted areas are respectively covered by the corresponding black matrix layer and pixel electrode layer to avoid light leakage.
[0007] An array substrate includes:
[0008] A common electrode layer;
[0009] The common electrode layer includes:
[0010] A first set of slotted areas;
[0011] A second set of slotted areas;
[0012] The first set of slotted areas is used to reduce the parasitic capacitance between the common electrode layer and the SD layer;
[0013] The second set of slotted areas is used to form an electric field between the common electrode layer and the pixel electrode layer to flip the liquid crystal;
[0014] The first set of slotted areas and the second set of slotted areas are formed on the common electrode layer at intervals.
[0015] Combined with the array substrate described in the first aspect of the present invention, in the first possible implementation manner, the first set of slotted areas includes:
[0016] Multiple square holes;
[0017] The multiple square holes are arranged vertically and aligned in sequence;
[0018] The vertical height of the first set of slotted areas is less than or equal to the vertical height of the second set of slotted areas.
[0019] Combined with the first possible implementation manner of the first aspect of the present invention, in the second possible implementation manner, the second set of slotted areas includes:
[0020] Multiple strip holes;
[0021] The multiple strip holes are arranged horizontally and aligned in sequence.
[0022] Combined with the second possible implementation manner of the first aspect of the present invention, in the third possible implementation manner, the array substrate further includes:
[0023] Buffer layer;
[0024] Insulating layer;
[0025] Flat layer;
[0026] Passivation layer;
[0027] The insulating layer is fabricated on the buffer layer, the flat layer is fabricated on the insulating layer, and the passivation layer is fabricated on the flat layer.
[0028] Combined with the third possible implementation manner of the first aspect of the present invention, in the fourth possible implementation manner, the array substrate further includes:
[0029] SD layer;
[0030] Pixel electrode layer;
[0031] Black matrix layer;
[0032] The SD layer is formed in the flat layer, the common electrode layer is formed in the passivation layer, the pixel electrode layer is formed on the passivation layer, and the black matrix layer is formed on the pixel electrode layer.
[0033] Combined with the fourth possible implementation manner of the first aspect of the present utility model, in the fifth possible implementation manner, the first set of slotted areas respectively correspond to the source electrode traces of the SD layer and the border of the black matrix layer. The square holes have the same shape and are arranged vertically one above the other in sequence, and the width and height of the square holes are smaller than the width and height of the border of the black matrix layer.
[0034] Combined with the fifth possible implementation manner of the first aspect of the present utility model, in the sixth possible implementation manner, the second set of slotted areas includes:
[0035] Two strip-shaped holes;
[0036] The two strip-shaped holes are aligned left and right in sequence, and the width and height of the formed second set of slotted areas are smaller than the width and height of the pixel electrode traces of the pixel electrode layer.
[0037] Combined with the sixth possible implementation manner of the first aspect of the present utility model, in the seventh possible implementation manner, the number of the first set of slotted areas is 3, and the number of the second set of slotted areas is 3.
[0038] In the second aspect, a liquid crystal display device includes the array substrate described in the first aspect.
[0039] Implementing the array substrate and the liquid crystal display device of the present utility model, by forming the first set of slotted areas on the common electrode layer, the parasitic capacitance between the common electrode layer and the SD layer can be effectively reduced, the load can be reduced, the problem of uneven display caused by the parasitic capacitance can be improved, and the first set of slotted areas and the second set of slotted areas provided are respectively covered by the corresponding black matrix layer and pixel electrode layer, avoiding light leakage. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0041] Figure 1 It is a schematic diagram of the film layer structure of the gate layer of the array substrate in the present utility model;
[0042] Figure 2 It is a schematic diagram of the film layer structure of the ISLAND layer of the array substrate in the present utility model;
[0043] Figure 3 It is a schematic diagram of the film layer structure of the SD layer of the array substrate in the present utility model;
[0044] Figure 4 Schematic diagram of the film layer structure of the common electrode layer of the array substrate in the present utility model;
[0045] Figure 5 Schematic diagram of the film layer structure of the pixel electrode layer of the array substrate in the present utility model;
[0046] Figure 6 Schematic diagram of the film layer structure of the black matrix layer of the array substrate in the present utility model;
[0047] Figure 7 Schematic diagram of the film forming structure of the array substrate in the present utility model. Detailed implementation manners
[0048] Next, the technical solutions in the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments in the present utility model, other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.
[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present utility model belongs. The terms used in the description of the present utility model in this specification are only for the purpose of describing specific embodiments, and are not intended to limit the present utility model. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0050] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.
[0051] It should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.
[0052] In addition, the terms "first" and "second" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this application, "a plurality of" means two or more unless otherwise specifically defined.
[0053] In the existing liquid crystal display panel, parasitic capacitance inside the array substrate can cause problems such as abnormal color display and Mura in the display panel.
[0054] To address the above problems, an array substrate and a liquid crystal display device are proposed.
[0055] An array substrate includes a common electrode layer 400 (VITO); as Figure 4 , Figure 4 is a schematic diagram of the film layer structure of the common electrode layer 400 (VITO) of the array substrate in the present utility model; the common electrode layer 400 (VITO) includes a first set of slotted areas 410 and a second set of slotted areas 420; the first set of slotted areas 410 is used to reduce the parasitic capacitance between the common electrode layer 400 (VITO) and the SD layer 300; the second set of slotted areas 420 is used to form an electric field between the common electrode layer 400 (VITO) and the pixel electrode layer 500 to flip the liquid crystal; the first set of slotted areas 410 and the second set of slotted areas 420 are formed at intervals on the common electrode layer 400 (VITO). By forming the first set of slotted areas 410 on the common electrode layer 400 (VITO), the parasitic capacitance between the common electrode layer 400 (VITO) and the SD layer 300 can be effectively reduced, the load can be decreased, and the problem of uneven display caused by parasitic capacitance can be improved.
[0056] In the design of a display panel, the design of pixels determines the display quality of the display panel. The design of pixels needs to consider the driving ability of the IC. If the parasitic capacitance between each trace is too large, resulting in an excessive pixel Loading, the IC may not be able to drive all the pixels, leading to problems such as abnormal color display, light leakage, and Mura.
[0057] In this embodiment, the first set of slotted areas 410 can effectively reduce the parasitic capacitance between the common electrode layer 400 (VITO) and the SD layer 300. It should be noted that, under the condition of meeting the functional requirements, multiple slotted areas can also be set to reduce the parasitic capacitance.
[0058] In the embodiment of this application, as Figures 1-6 , Figure 1 is a schematic diagram of the film layer structure of the gate layer 100 (gate) of the array substrate in the present utility model, Figure 2Schematic diagram of the film layer structure of the ISLAND layer 200 of the array substrate in the present utility model. Figure 3 Schematic diagram of the film layer structure of the SD layer 300 of the array substrate in the present utility model. Figure 5 Schematic diagram of the film layer structure of the pixel electrode layer 500 (PITO) of the array substrate in the present utility model. Figure 6 Schematic diagram of the film layer structure of the black matrix 600 (BM) layer of the array substrate in the present utility model; the array substrate further includes a buffer layer, an insulating layer, a planarizing layer, and a passivation layer; the insulating layer is fabricated on the buffer layer, the planarizing layer is fabricated on the insulating layer, and the passivation layer is fabricated on the planarizing layer. The array substrate further includes an SD layer 300, a pixel electrode layer 500 (PITO), and a black matrix 600 (BM) layer; the SD layer 300 is formed in the planarizing layer, the common electrode layer 400 (VITO) is formed in the passivation layer, the pixel electrode layer 500 (PITO) is formed on the passivation layer, and the black matrix 600 (BM) layer is formed on the pixel electrode layer 500 (PITO).
[0059] The film formation sequence is, from bottom to top, the gate layer 100 (gate), the ISLAND layer 200, the SD layer 300, the common electrode layer 400 (VITO), the pixel electrode layer 500 (PITO), and the black matrix 600 (BM) layer.
[0060] The SD layer 300 includes a source data trace 310 and a drain data trace 320. By setting the first set of slotted areas 410, the parasitic capacitance between the common electrode layer 400 (VITO) and the source data trace 310 of the SD layer 300 is effectively reduced, the load is lowered, and uneven display of the display device is avoided.
[0061] Such as Figure 4 , the first set of slotted areas 410 includes a plurality of square holes; the plurality of square holes are arranged vertically and aligned in sequence; the vertical height of the first set of slotted areas 410 is less than or equal to the vertical height of the second set of slotted areas 420.
[0062] In this embodiment, in order to avoid light leakage, the first set of slotted areas 410 respectively correspond to the source trace of the SD layer 300 and the frame 610 of the black matrix 600 (BM) layer. The square holes have the same shape, are arranged vertically in sequence, and the width and height of the square holes are less than the width and height of the frame 610 of the black matrix 600 (BM) layer. The first set of slotted areas 410 and the second set of slotted areas 420 provided are respectively covered by the corresponding black matrix 600 (BM) layer and pixel electrode layer 500 (PITO), avoiding light leakage.
[0063] It should be noted that, when the functional requirements are met, the openings of the first set of slotted areas 410 can be of various shapes and are arranged vertically.
[0064] Such asFigure 4 The second set of slotted areas 420 includes: a plurality of strip-shaped holes; the plurality of strip-shaped holes are aligned in sequence from left to right. Specifically, the second set of slotted areas 420 includes: two strip-shaped holes; the two strip-shaped holes are aligned in sequence from left to right, and the width and height of the formed second set of slotted areas 420 are smaller than the width and height of the pixel electrode traces of the pixel electrode layer 500 (PITO).
[0065] It should be noted that, when the functional requirements are met, the number of strip-shaped holes can be set according to the molding requirements.
[0066] For the second set of slotted areas 420, when voltages are applied to the two poles of the pixel electrode layer 500 (PTIO) and the common electrode layer 400 (VITO), an electric field is formed between the pixel electrode layer 500 (PTIO) and the common electrode layer 400 (VITO), causing the liquid crystal to flip, so that the display panel can display normally.
[0067] Specifically, the number of the first set of slotted areas 410 is 3, and the number of the second set of slotted areas 420 is 3.
[0068] In a second aspect, a liquid crystal display device includes the array substrate of the first aspect.
[0069] Implementing the array substrate and the liquid crystal display device of the present utility model, by forming the first set of slotted areas 410 in the common electrode layer 400 (VITO), the parasitic capacitance between the common electrode layer 400 (VITO) and the SD layer 300 can be effectively reduced, the load can be reduced, and the problem of uneven display caused by the parasitic capacitance can be improved. Moreover, the first set of slotted areas 410 and the second set of slotted areas 420 are respectively covered by the corresponding black matrix 600 (BM) layer and the pixel electrode layer 500 (PITO), avoiding light leakage.
[0070] The above are only the preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. An array substrate, characterized in that it comprises: A common electrode layer; The common electrode layer comprises: A first group of slotted areas; A second group of slotted areas; The first group of slotted areas is used to reduce the parasitic capacitance between the common electrode layer and the SD layer; The second group of slotted areas is used to form an electric field between the common electrode layer and the pixel electrode layer to flip the liquid crystal; The first group of slotted areas and the second group of slotted areas are formed on the common electrode layer at intervals.
2. The array substrate according to claim 1, wherein The first group of slotted areas comprises: A plurality of square holes; The plurality of square holes are arranged vertically and aligned in sequence; The vertical height of the first group of slotted areas is less than or equal to the vertical height of the second group of slotted areas.
3. The array substrate according to claim 2, wherein The second group of slotted areas comprises: A plurality of strip holes; The plurality of strip holes are arranged horizontally and aligned in sequence.
4. The array substrate according to claim 3, characterized in that The array substrate further comprises: A buffer layer; An insulating layer; A planarization layer; A passivation layer; The insulating layer is formed on the buffer layer, the planarization layer is formed on the insulating layer, and the passivation layer is formed on the planarization layer.
5. The array substrate according to claim 4, characterized in that The array substrate further comprises: An SD layer; A pixel electrode layer; A black matrix layer; The SD layer is formed in the planarization layer, the common electrode layer is formed in the passivation layer, the pixel electrode layer is formed on the passivation layer, and the black matrix layer is formed on the pixel electrode layer.
6. The array substrate according to claim 5, wherein The first group of slotted areas corresponds to the source traces of the SD layer and the borders of the black matrix layer respectively. The square holes have the same shape and are arranged vertically in sequence, and the width and height of the square holes are less than the width and height of the borders of the black matrix layer.
7. The array substrate according to claim 6, wherein The second group of slotted areas comprises: Two strip holes; The two strip holes are arranged horizontally and aligned in sequence, and the width and height of the formed second group of slotted areas are less than the width and height of the pixel electrode traces of the pixel electrode layer.
8. The array substrate according to any one of claims 1-7, characterized in that, The number of the first group of slotted areas is 3, and the number of the second group of slotted areas is 3.
9. A liquid crystal display device, characterized in that, An array substrate according to claim 8.