Current limiting circuit, low dropout voltage stabilizing circuit and radio frequency module
Through the current detection and control module in the current limiting circuit, combined with the hysteresis comparator and operational amplifier, the precise current limit of the low dropout voltage stabilization circuit is achieved, solving the problem of power tube burning in the RF chip/module, and improving the response accuracy and stability.
Patent Information
- Application Number
- CN202422572280.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-10-23
AI Technical Summary
In RF chips/modules, existing low dropout linear voltage regulators are prone to burning the power tube due to excessive load current or short-circuit output, causing irreversible damage, and lacking effective current limit protection.
Design a current limiting circuit, including a current detection module, a current limiting control module and an operational amplifier, and replicate the power tube current proportionally by detecting transistors, control the current limit using a hysteresis comparator and an on-off transistor, and combine it with a negative feedback loop to achieve accurate current limiting and stability protection.
It effectively limits the output overcurrent of the low dropout voltage regulator circuit, avoids avalanche breakdown and heating of power tubes, improves the response accuracy and stability of the current limit circuit, and protects the RF chip/module from damage.
Smart Images
Figure CN223140084U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technologies, and particularly to a current limiting circuit, a low dropout voltage regulation circuit, and a radio frequency module. Background Art
[0002] A low dropout regulator (LDO) is a voltage regulation power supply circuit with characteristics such as low operating voltage, small output ripple, good transient response ability, and low cost. It is usually used in the voltage bias circuit of a radio frequency chip / module to provide a DC operating voltage for the radio frequency chip / module.
[0003] However, in the actual use process of a radio frequency chip / module, its complex application environment often leads to large current operating conditions. At this time, if the load current of the LDO is too large or the output is short-circuited, it may cause devices such as power transistors on the LDO output link to burn out. For example, the gate-source voltage difference of the power transistor is too large, the current flowing through the power transistor is too large, avalanche breakdown and device burnout occur, resulting in irreversible damage to the radio frequency chip / module.
[0004] Therefore, it is necessary to introduce a current limiting protection circuit to limit the output current of the LDO and reduce the heat generation of the chip. Summary of the Utility Model
[0005] In view of this, embodiments of this application provide a current limiting circuit, a low dropout voltage regulation circuit, and a radio frequency module to solve at least one problem in the background art.
[0006] In a first aspect, embodiments of this application provide a current limiting circuit, which includes:
[0007] A current detection module configured to scale and copy the current flowing through the power transistor of the low dropout voltage regulation circuit using a detection transistor to obtain a detection current, and determine a detection voltage based on the detection current;
[0008] A current limiting control module configured to obtain the detection voltage, and output a current limiting control signal to the control end of the power transistor when the detection voltage exceeds a second reference voltage to limit the current flowing through the power transistor; and when the current flowing through the power transistor drops and the detection voltage is lower than a recovery threshold voltage, turn off the output of the current limiting control signal to enable the low dropout voltage regulation circuit to resume normal output; wherein the recovery threshold voltage is less than or equal to the second reference voltage;
[0009] The operational amplifier has its non-inverting input terminal configured to obtain an output voltage determined according to the current flowing through the power transistor, and its inverting input terminal configured to obtain the detection voltage. The output terminal is connected to the control terminal of the power transistor and is used to make the output voltage and the detection voltage consistent based on the clamping effect of the operational amplifier;
[0010] Wherein, at least a negative feedback loop is formed based on the operational amplifier and the power transistor; at least a positive feedback loop is formed based on the operational amplifier and the detection transistor; and the net feedback of the negative feedback loop and the positive feedback loop is negative feedback.
[0011] Combined with the first aspect, in an alternative embodiment, the current limiting control module includes:
[0012] A hysteresis comparator configured to output a turn-off control signal at a first level when the detection voltage exceeds the current limiting threshold voltage; and output a turn-off control signal at a second level when the detection voltage is lower than the recovery threshold voltage; wherein, the current limiting threshold voltage is greater than the second reference voltage, and the recovery threshold voltage is less than the second reference voltage;
[0013] A turn-off transistor configured to conduct under the control of the turn-off control signal at the first level to output the current limiting control signal; and turn off under the control of the turn-off control signal at the second level to turn off the output of the current limiting control signal.
[0014] Combined with the first aspect, in an alternative embodiment, the power transistor is a PMOS transistor;
[0015] The turn-off transistor is a PMOS transistor;
[0016] The inverting input terminal of the hysteresis comparator is configured to obtain the detection voltage, the non-inverting input terminal of the hysteresis comparator is configured to obtain the second reference voltage, and the output terminal of the hysteresis comparator is connected to the gate of the turn-off transistor; the source of the turn-off transistor is connected to the first power supply terminal, and the drain of the turn-off transistor is connected to the gate of the power transistor.
[0017] Combined with the first aspect, in an alternative embodiment, the current detection module includes a detection transistor and a detection resistor;
[0018] The detection transistor is a PMOS transistor;
[0019] The gate of the detection transistor is connected to the gate of the power transistor, the source of the detection transistor is connected to the first power supply terminal, the drain of the detection transistor is connected to the first end of the detection resistor and is configured to provide the detection voltage; the second end of the detection resistor is connected to the second power supply terminal.
[0020] In combination with the first aspect, in an optional embodiment, the hysteresis comparator includes a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second PMOS transistor, a twenty-third NMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth PMOS transistor, a thirtieth NMOS transistor, a thirty-first PMOS transistor, a thirty-second NMOS transistor, a thirty-third PMOS transistor, and a thirty-fourth NMOS transistor;
[0021] The gate of the twentieth NMOS transistor is configured as the inverting input terminal of the hysteresis comparator; the gate of the twenty-first NMOS transistor is configured as the non-inverting input terminal of the hysteresis comparator;
[0022] The drain of the twentieth NMOS transistor is respectively connected to the gate of the twenty-second PMOS transistor, the drain of the twenty-fourth PMOS transistor, the gate of the twenty-fourth PMOS transistor, the gate of the twenty-fifth PMOS transistor, and the drain of the twenty-sixth PMOS transistor. The drain of the twenty-first NMOS transistor is respectively connected to the gate of the twenty-ninth PMOS transistor, the drain of the twenty-seventh PMOS transistor, the gate of the twenty-seventh PMOS transistor, the gate of the twenty-sixth PMOS transistor, and the drain of the twenty-fifth PMOS transistor. The sources of the twentieth NMOS transistor and the twenty-first NMOS transistor are respectively connected to the drain of the twenty-eighth NMOS transistor. The source of the twenty-eighth NMOS transistor is connected to the second power supply terminal, and the gate of the twenty-eighth NMOS transistor is configured to obtain a first low bias signal;
[0023] The sources of the twenty-fourth PMOS transistor, the twenty-fifth PMOS transistor, the twenty-sixth PMOS transistor, and the twenty-seventh PMOS transistor are respectively connected to the first power supply terminal;
[0024] The sources of the twenty-second PMOS transistor and the twenty-ninth PMOS transistor are respectively connected to the first power supply terminal. The drain of the twenty-second PMOS transistor is respectively connected to the drain of the twenty-third NMOS transistor, the gate of the twenty-third NMOS transistor, and the gate of the thirtieth NMOS transistor. The sources of the twenty-third NMOS transistor and the thirtieth NMOS transistor are respectively connected to the second power supply terminal. The drain of the twenty-ninth PMOS transistor is respectively connected to the drain of the thirtieth NMOS transistor, the gate of the thirty-first PMOS transistor, and the gate of the thirty-second NMOS transistor;
[0025] The drain of the thirty-first PMOS transistor is respectively connected to the drain of the thirty-second NMOS transistor, the gate of the thirty-third PMOS transistor, and the gate of the thirty-fourth NMOS transistor. The drain of the thirty-third PMOS transistor is connected to the drain of the thirty-fourth NMOS transistor and configured as the output terminal of the hysteresis comparator;
[0026] The sources of the thirty-first PMOS transistor and the thirty-third PMOS transistor are respectively connected to the first power supply terminal, and the sources of the thirty-second NMOS transistor and the thirty-fourth NMOS transistor are respectively connected to the second power supply terminal.
[0027] Combined with the first aspect, in an alternative embodiment, the operational amplifier includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth PMOS transistor;
[0028] The gate of the eleventh PMOS transistor is configured as the non-inverting input terminal of the operational amplifier; the gate of the twelfth PMOS transistor is configured as the inverting input terminal of the operational amplifier;
[0029] The sources of the eleventh PMOS transistor and the twelfth PMOS transistor are respectively connected to the drain of the thirteenth PMOS transistor. The source of the thirteenth PMOS transistor is connected to the first power supply terminal, and the gate of the thirteenth PMOS transistor is configured to obtain a third bias signal;
[0030] The drain of the eleventh PMOS transistor is respectively connected to the drain of the fourteenth NMOS transistor and the source of the fifteenth NMOS transistor. The drain of the twelfth PMOS transistor is respectively connected to the drain of the seventeenth NMOS transistor and the source of the eighteenth NMOS transistor;
[0031] The sources of the fourteenth NMOS transistor and the seventeenth NMOS transistor are respectively connected to the second power supply terminal. The gates of the fourteenth NMOS transistor and the seventeenth NMOS transistor are respectively configured to obtain a second bias signal;
[0032] The drain of the fifteenth NMOS transistor is respectively connected to the drain of the sixteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the nineteenth PMOS transistor. The gates of the fifteenth NMOS transistor and the eighteenth NMOS transistor are respectively configured to obtain a first bias signal. The drain of the eighteenth NMOS transistor is connected to the drain of the nineteenth PMOS transistor and configured as the output terminal of the operational amplifier;
[0033] The source of the sixteenth PMOS transistor and the source of the nineteenth PMOS transistor are respectively connected to the first power supply terminal.
[0034] In a second aspect, an embodiment of the present application provides a low dropout regulator circuit, where the low dropout regulator circuit includes an error amplifier, a power transistor, a voltage feedback circuit, and a current limiting circuit as described in the first aspect;
[0035] The inverting input terminal of the error amplifier is configured to obtain a first reference voltage. The non-inverting input terminal of the error amplifier is connected to the output terminal of the voltage feedback circuit, and the output terminal of the error amplifier is connected to the control terminal of the power transistor; the first signal terminal of the power transistor is connected to the first power supply terminal, and the second signal terminal of the power transistor is connected to the input terminal of the voltage feedback circuit and is configured to provide the output voltage of the low dropout regulator circuit;
[0036] Wherein, the second signal terminal of the power transistor is connected to the non-inverting input terminal of the operational amplifier of the current limiting circuit, and the control terminal of the power transistor is connected to the output terminal of the operational amplifier, so that the output voltage is kept consistent with the detection voltage at the inverting input terminal of the operational amplifier based on the clamping effect of the operational amplifier.
[0037] In combination with the second aspect, in an optional embodiment, the error amplifier includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a thirty-fifth PMOS transistor, and a compensation capacitor;
[0038] The gate of the first PMOS transistor is configured as the inverting input terminal of the error amplifier; the gate of the second PMOS transistor is configured as the non-inverting input terminal of the error amplifier;
[0039] The drain of the first PMOS transistor is respectively connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor, and the gate of the fifth NMOS transistor. The drain of the second PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the sixth NMOS transistor; the drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor, and the drain of the sixth NMOS transistor is connected to the source of the eighth NMOS transistor; the drain of the seventh NMOS transistor is respectively connected to the drain of the ninth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor, and the drain of the eighth NMOS transistor is connected to the drain of the tenth PMOS transistor and is configured as the output terminal of the error amplifier;
[0040] The gates of the seventh NMOS transistor and the eighth NMOS transistor are respectively configured to obtain the second lowest bias signal; the sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are respectively connected to the second power supply terminal; the sources of the first PMOS transistor and the second PMOS transistor are respectively connected to the drain of the thirty-fifth PMOS transistor, and the gate of the thirty-fifth PMOS transistor is configured to obtain the first highest bias signal; the source of the thirty-fifth PMOS transistor, the source of the ninth PMOS transistor, and the source of the tenth PMOS transistor are respectively connected to the first power supply terminal;
[0041] The first end of the compensation capacitor is respectively connected to the drain of the sixth NMOS transistor and the source of the eighth NMOS transistor, and the second end of the compensation capacitor is connected to the output terminal of the low dropout regulator circuit.
[0042] Combined with the second aspect, in an alternative embodiment, the voltage feedback circuit includes a first resistor and a second resistor;
[0043] The non-inverting input terminal of the error amplifier is respectively connected to the second end of the first resistor and the first end of the second resistor. The first end of the first resistor is respectively connected to the second signal terminal of the power transistor and the non-inverting input terminal of the operational amplifier of the current limiting circuit; the second end of the second resistor is connected to the second power supply terminal.
[0044] In a third aspect, an embodiment of the present application provides a radio frequency module, and the radio frequency module includes the low dropout regulator circuit as described in the second aspect.
[0045] The beneficial effects brought by the technical solutions provided by the embodiments of the present application include: through the current detection module and the current limiting control module, the output overcurrent of the low dropout regulator circuit is restricted, and it is possible to avoid the large current flowing through the power transistor and causing avalanche breakdown, heating, and device burnout when the low dropout regulator circuit operates with a large load current or output short circuit. And through the operational amplifier, using its clamping effect, it is possible to avoid the channel length modulation effect of the detection transistor and the power transistor, so that the detection transistor can accurately replicate the current flowing through the power transistor in proportion, realizing high-precision current replication and improving the response accuracy of the current limiting circuit. And by setting the recovery threshold voltage, when the recovery threshold voltage is less than the second reference voltage, the low dropout regulator circuit can start working again only after the current flowing through the power transistor drops back to a certain current capacity, improving the response stability of the current limiting circuit. And by making the net feedback a negative feedback, the stability of the low dropout regulator circuit is improved.
[0046] The additional aspects and advantages of the embodiments of the present application will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the embodiments of the present application. Brief Description of the Drawings
[0047] The drawings described herein are provided to further understand the present application and form a part of the present application. Among them, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of local features. The schematic embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:
[0048] Figure 1 is a circuit schematic diagram of a specific example of an LDO circuit with a current limiting function in the related art;
[0049] Figure 2 is a circuit schematic diagram of a specific example of the current limiting circuit in the embodiment of the present application;
[0050] Figure 3 is a circuit schematic diagram of a specific example of the hysteresis comparator in the embodiment of the present application;
[0051] Figure 4 is a circuit schematic diagram of a specific example of the operational amplifier in the embodiment of the present application;
[0052] Figure 5 is a circuit schematic diagram of a specific example of the low dropout regulator circuit in the embodiment of the present application;
[0053] Figure 6 is a circuit schematic diagram of a specific example of the error amplifier in the embodiment of the present application. Detailed Description of the Embodiments
[0054] To make the technical solutions and beneficial effects of the present utility model more obvious and understandable, the following will be described in detail by listing specific embodiments. Among them, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of local features; unless otherwise defined, the technical and scientific terms used herein have the same meaning as those in the technical field to which the present application belongs.
[0055] The embodiments of the present application are not exhaustive, but only schematic of some embodiments and do not constitute a specific limitation to the protection scope of the present application. Without contradiction, each step in an embodiment can be implemented as an independent embodiment, and the steps can be combined arbitrarily. For example, the solution after removing some steps in an embodiment can also be implemented as an independent embodiment, and the order of the steps in an embodiment can be arbitrarily exchanged. In addition, the optional implementation manners in an embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined. For example, some or all of the steps of different embodiments can be arbitrarily combined, and an embodiment can be arbitrarily combined with the optional implementation manners of other embodiments.
[0056] In each embodiment of the present application, if there is no special description or logical conflict, the terms and / or descriptions between the embodiments are consistent and can be cited from each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.
[0057] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application.
[0058] In the embodiments of the present application, unless otherwise specified, elements expressed in the singular form, such as "a", "an", "the", "above-mentioned", "said", "aforementioned", "this", etc., can mean "one and only one", or can also mean "one or more", "at least one", etc. For example, in the case of using articles such as "a", "an", "the" in English translation, the noun after the article can be understood as a singular expression form or a plural expression form.
[0059] In the embodiments of the present application, "a plurality of" means two or more.
[0060] In some embodiments, terms such as "at least one (at least one of, at least one item, at least one)", "one or more", "a plurality of", "multiple", etc. can be replaced with each other.
[0061] The prefix words such as "first", "second", etc. in the embodiments of the present application are only used to distinguish different described objects, and do not constitute restrictions on the position, order, priority, numerical value or content, etc. of the described objects. The statement of the described objects refers to the description in the claims or the context of the embodiments, and should not constitute redundant restrictions due to the use of prefix words. For example, the numerical value of the described object is not restricted by the ordinal number and can be one or more. Taking "the first device" as an example, the numerical value of "device" can be one or more. In addition, the objects modified by different prefix words can be the same or different. For example, if the described object is "device", then "the first device" and "the second device" can be the same device or different devices, and their types can be the same or different.
[0062] In some embodiments, the term "connection" can mean that there is a transmission of electrical signals or data between the connected end and the connected-to end, and can be understood as "electrically connected", "communicatively connected", etc. "Connection" can be a direct connection between two components, or an indirect connection established through other components, or a connection inside two components, or any other possible connection form.
[0063] In the process of implementing the present utility model, the inventor found the following problems in the related art:
[0064] Figure 1 The circuit schematic diagram of a specific example of an LDO circuit with a current limiting function in the related art is shown. As shown in the figure, the overall architecture of the LDO circuit with a current limiting function includes two parts: the main structure of the LDO circuit composed of an error amplifier EA01, a power transistor MP01, and a feedback circuit; and a current limiting circuit composed of a detection transistor MS01, a detection resistor RS01, a comparator COM01, and a switching transistor MC01.
[0065] The inverting input terminal of the error amplifier EA01 is configured to obtain a first reference voltage vref01. The output terminal of the error amplifier EA01 is connected to the control terminal of the power transistor MP01. The first terminal of the power transistor MP01 is configured to obtain an input power supply vin. The second terminal of the power transistor MP01 is configured to provide an output voltage vout and is connected to the non-inverting input terminal of the error amplifier EA01 through a feedback circuit. The feedback circuit may include a first resistor R01 and a second resistor R02 connected in series between the second terminal of the power transistor MP01 and the ground terminal. The connection node between the first resistor R01 and the second resistor R02 is connected to the non-inverting input terminal of the error amplifier EA01.
[0066] The control terminal of the detection transistor MS01 is connected to the control terminal of the power transistor MP01. The first terminal of the detection transistor MS01 is configured to obtain an input power supply vin. The second terminal of the detection transistor MS01 is respectively connected to the inverting input terminal of the comparator COM01 and the first terminal of the detection resistor RS01. The second terminal of the detection resistor RS01 is connected to the ground terminal. The non-inverting input terminal of the comparator COM01 is configured to obtain a second reference voltage vref02. The output terminal of the comparator COM01 is connected to the control terminal of the switching transistor MC01. The first terminal of the switching transistor MC01 is configured to obtain an input power supply vin. The second terminal of the switching transistor MC01 is connected to the control terminal of the power transistor MP01.
[0067] Among them, the current limiting circuit is an external circuit of the main structure of the LDO circuit, so it will not cause stability problems of the LDO circuit.
[0068] The aspect ratio of the power transistor MP01 to the detection transistor MS01 is N:1 (N is much greater than 1). When there is a situation such as an excessive load current or an output short circuit in the LDO circuit, a large current (exceeding the rated current) flows through the power transistor MP01. At this time, the current flowing through the detection transistor MS01 also increases, the voltage drop across the detection resistor RS01 increases, the voltage at the inverting input terminal of the comparator COM01 increases, so the comparator COM01 outputs a low level, the switching transistor MC01 conducts, and then the gate terminal (control terminal) of the power transistor MP01 is pulled high to reduce the current flowing through the power transistor MP01. For example, the LDO circuit can be turned off, thus playing a role in current limiting.
[0069] When the load current of the LDO circuit drops, the current flowing through the power transistor MP01 decreases, and at the same time, the current of the detection transistor MS01 also decreases. When the current flowing through the power transistor MP01 returns to be lower than the rated current, the voltage at the inverting input terminal of the comparator COM01 is less than the voltage at the non-inverting input terminal, and the comparator COM01 outputs a high level, so that the switching transistor MC01 is cut off, and the LDO circuit resumes the output in the normal working state.
[0070] In this application, the LDO circuit can have different names, such as LDO, low dropout regulator circuit, low dropout voltage regulator, low dropout linear regulator circuit, etc. The names are not restricted here. The high level and the low level can be relative values, not limited to absolute values. The input power supply vin can be provided by the circuit power supply terminal, and the ground terminal can be grounded to 0V.
[0071] As Figure 1 shown, the potentials of the output node A and the detection node B may not be the same, which is caused by the channel length modulation effect of the transistor and is an obvious defect of this LDO circuit. Therefore, the detection transistor MS01 cannot accurately replicate the current flowing through the power transistor MP01 in proportion, so that the current limiting circuit cannot respond accurately.
[0072] Therefore, the embodiment of this application provides a current limiting circuit. Figure 2 The circuit schematic diagram of a specific example of the current limiting circuit in the embodiment of this application is shown. As shown in the figure, the current limiting circuit includes:
[0073] A current detection module 20, configured to scale down and replicate the current flowing through the power transistor MP of the low dropout regulator circuit by using the detection transistor MS to obtain a detection current, and determine a detection voltage v- according to the detection current;
[0074] The current limiting control module 30 is configured to obtain the detected voltage v-, and output a current limiting control signal to the control end of the power transistor MP when the detected voltage v- exceeds the second reference voltage vref2, so as to limit the current flowing through the power transistor MP; and when the current flowing through the power transistor MP drops and the detected voltage v- is lower than the recovery threshold voltage, the output of the current limiting control signal is turned off, so that the low dropout regulator circuit resumes normal output; wherein, the recovery threshold voltage is less than or equal to the second reference voltage;
[0075] The operational amplifier OP has its non-inverting input terminal configured to obtain the output voltage vout determined according to the current flowing through the power transistor MP, its inverting input terminal configured to obtain the detected voltage v-, and its output terminal connected to the control end of the power transistor MP, and is used to make the output voltage vout and the detected voltage v- consistent based on the clamping effect of the operational amplifier OP;
[0076] Wherein, at least a negative feedback loop is formed based on the operational amplifier OP and the power transistor MP; at least a positive feedback loop is formed based on the operational amplifier OP and the detection transistor MS; and the net feedback of the negative feedback loop and the positive feedback loop is negative feedback.
[0077] In this way, in the embodiment of the present application, the current detection module and the current limiting control module are used to limit the output overcurrent of the low dropout regulator circuit, and can avoid the large current flowing through the power transistor and causing avalanche breakdown, heating and device burnout when the low dropout regulator circuit works with a large load current or output short circuit. And through the operational amplifier, using its clamping effect, the channel length modulation effects of the detection transistor and the power transistor can be avoided, so that the detection transistor can accurately copy the current flowing through the power transistor in proportion, realizing high-precision current replication and improving the response accuracy of the current limiting circuit. And by setting the recovery threshold voltage, when the recovery threshold voltage is less than the second reference voltage, the low dropout regulator circuit can start working again only after the current flowing through the power transistor drops a certain current capacity, improving the response stability of the current limiting circuit. And by having the net feedback as negative feedback, the stability of the low dropout regulator circuit is improved.
[0078] In the embodiment of the present application, the power transistor MP can be a single transistor; or it can be a series and / or parallel combination of multiple transistors, having a control end, a first signal end and a second signal end corresponding to a single transistor.
[0079] Similarly, the detection transistor MS can be a single transistor; or it can be a series and / or parallel combination of multiple transistors, having a control end, a first signal end and a second signal end corresponding to a single transistor.
[0080] The power transistor MP and the detection transistor MS may include at least one of the following: MOSFET (Metal Oxide Semiconductor Field Effect Transistor, simply referred to as MOS transistor); BJT (Bipolar Junction Transistor, simply referred to as triode); IGBT (Insulated Gate Bipolar Transistor); GTO (Gate Turn-Off Thyristor); SCR (Silicon Controlled Rectifier); MCT (MOS Controlled Thyristor); IGCT (Integrated Gate Commutated Thyristor); IEGT (Injection Enhanced Gate Transistor).
[0081] Exemplarily, the power transistor MP may be a PMOS transistor. Correspondingly, the detection transistor MS may be a PMOS transistor. Or the power transistor MP may also be an NMOS transistor. Correspondingly, the detection transistor MS may be an NMOS transistor.
[0082] In the embodiments of the present application, the scaled-down replicated current may be a detection current obtained by replicating the current flowing through the power transistor MP at a reduced ratio. Exemplarily, the ratio of the width-to-length ratio of the power transistor MP and the detection transistor MS may be N∶1 (N is much greater than 1), so as to achieve the scaled-down replicated current.
[0083] In some possible implementation manners, the manner of determining the detection voltage v- according to the detection current in the current detection module 20 may include at least one of the following: using a resistor; using a current-voltage converter; using a transimpedance amplifier.
[0084] In some possible implementation manners, the manner of performing voltage comparison in the current limiting control module 30, such as comparing the detection voltage v- and the second reference voltage vref2, or comparing the detection voltage v- and the recovery threshold voltage, may include at least one of the following: using one or more voltage comparators; directly implementing a comparison circuit using different logic operations (AND, OR, NOT, etc.) of a gate circuit.
[0085] Exemplarily, when the low dropout regulator circuit has a situation such as an excessive load current or an output short circuit, the current flowing through the power transistor MP exceeds the rated current. At this time, the detection current obtained by scaled-down replication using the detection transistor MS also increases, so that the detection voltage v- increases and exceeds the second reference voltage vref2 (if it is a hysteresis comparator, at this time the detection voltage v- exceeds the current limiting threshold voltage, and the current limiting threshold voltage is greater than the second reference voltage vref2). The current limiting control module 30 outputs a current limiting control signal to the control end of the power transistor MP to reduce the current flowing through the power transistor MP01, so that the low dropout regulator circuit is turned off, thereby playing a role in current limiting. And by using the clamping effect of the operational amplifier OP, the potentials of point A and point B are made consistent, thereby avoiding the channel length modulation effect, so that the detection transistor MS can accurately replicate the current flowing through the power transistor MP in proportion, and improving the response accuracy of the current limiting circuit.
[0086] When the load current of the low-dropout regulator circuit drops, the current flowing through the power transistor MP decreases, and at the same time, the current flowing through the detection transistor MS also decreases. When the drop in the current flowing through the power transistor MP causes the detection voltage v- to be lower than the recovery threshold voltage, the output of the current limiting control signal can be turned off, so that the low-dropout regulator circuit can be started again. When the recovery threshold voltage is less than the second reference voltage vref2, the low-dropout regulator circuit can be restarted after the current flowing through the power transistor MP drops by a certain current capacity.
[0087] Exemplarily, if a comparator is used for voltage comparison in the current limiting control module 30, that is, in the case where the recovery threshold voltage is equal to the second reference voltage, when the detection voltage v- is greater than the second reference voltage vref2, a current limiting control signal can be output; when the detection voltage v- is less than the second reference voltage vref2, the output of the current limiting control signal can be turned off.
[0088] In some possible implementation manners, the high-level or low-level voltage value of the current limiting control signal can be determined according to actual requirements to implement control of the current flowing through the power transistor, such as implementing on / off control of the power transistor. For example, if the power transistor is a PMOS transistor, when the current limiting control signal is at a high level, it can control the power transistor to turn off to turn off the low-dropout regulator circuit, and this high level can be determined according to the power supply voltage.
[0089] In an alternative embodiment, the current limiting control module 30 includes:
[0090] A hysteresis comparator COM configured to output an on / off control signal of a first level when the detection voltage v- exceeds a current limiting threshold voltage; and output an on / off control signal of a second level when the detection voltage v- is lower than a recovery threshold voltage; wherein, the current limiting threshold voltage is greater than the second reference voltage vref2, and the recovery threshold voltage is less than the second reference voltage vref2;
[0091] An on / off transistor MC configured to conduct under the control of the on / off control signal of the first level to output the current limiting control signal; and turn off under the control of the on / off control signal of the second level to turn off the output of the current limiting control signal.
[0092] In the embodiments of the present application, the on / off transistor MC can be a single transistor; or it can be a plurality of transistors connected in series and / or in parallel, having a control terminal, a first signal terminal, and a second signal terminal corresponding to a single transistor.
[0093] The switching transistor MC may include at least one of the following: MOSFET (Metal Oxide Semiconductor Field Effect Transistor, simply referred to as MOS transistor); BJT (Bipolar Junction Transistor, simply referred to as triode); IGBT (Insulated Gate Bipolar Transistor); GTO (Gate Turn-Off Thyristor); SCR (Silicon Controlled Rectifier); MCT (MOS Controlled Thyristor); IGCT (Integrated Gate Commutated Thyristor); IEGT (Injection Enhanced Gate Transistor).
[0094] Exemplarily, the switching transistor MC may be a PMOS transistor, or may also be an NMOS transistor.
[0095] In some possible implementation manners, the detection voltage v- may be input from the inverting input terminal of the hysteresis comparator COM. Thus, when the detection voltage v- exceeds the current limiting threshold voltage, the hysteresis comparator COM may output a low-level switching control signal, which can control the switching transistor MC of the PMOS to conduct and output a current limiting control signal. On the contrary, when the detection voltage v- is lower than the recovery threshold voltage, the hysteresis comparator COM may output a high-level switching control signal, which can control the switching transistor MC of the PMOS to cut off and turn off the output of the current limiting control signal.
[0096] Certainly, the detection voltage v- may also be input from the non-inverting input terminal of the hysteresis comparator COM. Thus, when the detection voltage v- exceeds the current limiting threshold voltage, the hysteresis comparator COM may output a high-level switching control signal, and a switching transistor MC adapted to the high-level switching control signal may be set to achieve the control of outputting a current limiting control signal. The specific control principle can be obtained by referring to the above for change and will not be elaborated here.
[0097] In this way, through the hysteresis comparator and the switching transistor in the embodiment of the present application, it is realized that current limiting is only performed when the current flowing through the power transistor exceeds a certain current limiting capacity, so as to avoid interfering with the self-regulation ability of the low-dropout regulator circuit; and after the current flowing through the power transistor drops to a certain current capacity, the low-dropout regulator circuit can start working again, improving the response stability of the current limiting circuit.
[0098] In an alternative implementation manner, the power transistor MP is a PMOS transistor;
[0099] The switching transistor MC is a PMOS transistor;
[0100] The inverting input terminal of the hysteresis comparator COM is configured to obtain the detection voltage v-, the non-inverting input terminal of the hysteresis comparator COM is configured to obtain the second reference voltage vref2, and the output terminal of the hysteresis comparator COM is connected to the gate of the switching transistor MC; the source of the switching transistor MC is connected to the first power supply terminal vdda, and the drain of the switching transistor MC is connected to the gate of the power transistor MP.
[0101] In an alternative embodiment, the current detection module 20 includes a detection transistor MS and a detection resistor RS;
[0102] The detection transistor MS is a PMOS transistor;
[0103] The gate of the detection transistor MS is connected to the gate of the power transistor MP, the source of the detection transistor MS is connected to the first power supply terminal vdda, and the drain of the detection transistor MS is connected to the first end of the detection resistor RS and configured to provide the detection voltage v-; the second end of the detection resistor RS is connected to the second power supply terminal vssa.
[0104] In the embodiment of the present application, the first power supply terminal vdda can provide a power supply voltage, and the second power supply terminal vssa can be grounded.
[0105] The detection resistor RS can be a single resistor, or a series and / or parallel combination of multiple resistors, or a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.
[0106] When the current flowing through the power transistor MP increases, the detection current also increases accordingly, so that the detection voltage v- increases accordingly and when it exceeds the current limiting threshold voltage, the hysteresis comparator COM outputs a low-level switching control signal to control the switching transistor MC to conduct. The drain of the switching transistor MC becomes high level, pulling up the gate of the power transistor MP, so that the low dropout regulator circuit is turned off, thus playing a role in current limiting. And by using the clamping effect of the operational amplifier OP, the potentials of point A and point B are made consistent, so that the detection transistor MS accurately replicates the current flowing through the power transistor MP, improving the response accuracy of the current limiting circuit.
[0107] Since the load current of the low dropout regulator circuit drops, the current flowing through the power transistor MP decreases, and the detection current also decreases accordingly. Thus, the detection voltage v- decreases accordingly and when it is lower than the recovery threshold voltage, the hysteresis comparator COM outputs a high-level switching control signal to control the switching transistor MC to cut off. The drain of the switching transistor MC becomes low level, so that after the low dropout regulator circuit drops a certain current capacity, it can start working again.
[0108] Figure 3The circuit schematic diagram of a specific example of the hysteresis comparator in the embodiment of the present application is shown. Among them, the specific circuit structure of the hysteresis comparator can be set according to actual needs and is not limited thereto. In an alternative embodiment, the hysteresis comparator includes a twentieth NMOS transistor M20, a twenty-first NMOS transistor M21, a twenty-second PMOS transistor M22, a twenty-third NMOS transistor M23, a twenty-fourth PMOS transistor M24, a twenty-fifth PMOS transistor M25, a twenty-sixth PMOS transistor M26, a twenty-seventh PMOS transistor M27, a twenty-eighth NMOS transistor M28, a twenty-ninth PMOS transistor M29, a thirtieth NMOS transistor M30, a thirty-first PMOS transistor M31, a thirty-second NMOS transistor M32, a thirty-third PMOS transistor M33, and a thirty-fourth NMOS transistor M34;
[0109] The gate of the twentieth NMOS transistor M20 is configured as the inverting input terminal of the hysteresis comparator COM; the gate of the twenty-first NMOS transistor M21 is configured as the non-inverting input terminal of the hysteresis comparator COM;
[0110] The drain of the twentieth NMOS transistor M20 is respectively connected to the gate of the twenty-second PMOS transistor M22, the drain of the twenty-fourth PMOS transistor M24, the gate of the twenty-fourth PMOS transistor M24, the gate of the twenty-fifth PMOS transistor M25, and the drain of the twenty-sixth PMOS transistor M26. The drain of the twenty-first NMOS transistor M21 is respectively connected to the gate of the twenty-ninth PMOS transistor M29, the drain of the twenty-seventh PMOS transistor M27, the gate of the twenty-seventh PMOS transistor M27, the gate of the twenty-sixth PMOS transistor M26, and the drain of the twenty-fifth PMOS transistor M25. The sources of the twentieth NMOS transistor M20 and the twenty-first NMOS transistor M21 are respectively connected to the drain of the twenty-eighth NMOS transistor M28. The source of the twenty-eighth NMOS transistor M28 is connected to the second power supply terminal vssa, and the gate of the twenty-eighth NMOS transistor M28 is configured to obtain a first low bias signal vbn1;
[0111] The sources of the twenty-fourth PMOS transistor M24, the twenty-fifth PMOS transistor M25, the twenty-sixth PMOS transistor M26, and the twenty-seventh PMOS transistor M27 are respectively connected to the first power supply terminal vdda;
[0112] The sources of the twenty-second PMOS transistor M22 and the twenty-ninth PMOS transistor M29 are respectively connected to the first power supply terminal Vdda. The drain of the twenty-second PMOS transistor M22 is respectively connected to the drain of the twenty-third NMOS transistor M23, the gate of the twenty-third NMOS transistor M23, and the gate of the thirtieth NMOS transistor M30. The sources of the twenty-third NMOS transistor M23 and the thirtieth NMOS transistor M30 are respectively connected to the second power supply terminal Vssa. The drain of the twenty-ninth PMOS transistor M29 is respectively connected to the drain of the thirtieth NMOS transistor M30, the gate of the thirty-first PMOS transistor M31, and the gate of the thirty-second NMOS transistor M32.
[0113] The drain of the thirty-first PMOS transistor M31 is respectively connected to the drain of the thirty-second NMOS transistor M32, the gate of the thirty-third PMOS transistor M33, and the gate of the thirty-fourth NMOS transistor M34. The drain of the thirty-third PMOS transistor M33 is connected to the drain of the thirty-fourth NMOS transistor M34 and configured as the output terminal COMout of the hysteresis comparator.
[0114] The sources of the thirty-first PMOS transistor M31 and the thirty-third PMOS transistor M33 are respectively connected to the first power supply terminal Vdda. The sources of the thirty-second NMOS transistor M32 and the thirty-fourth NMOS transistor M34 are respectively connected to the second power supply terminal Vssa.
[0115] In the embodiment of the present application, the main structure of the hysteresis comparator is formed by the twentieth NMOS transistor M20, the twenty-first NMOS transistor M21, the twenty-second PMOS transistor M22, the twenty-third NMOS transistor M23, the twenty-fourth PMOS transistor M24, the twenty-fifth PMOS transistor M25, the twenty-sixth PMOS transistor M26, the twenty-seventh PMOS transistor M27, the twenty-eighth NMOS transistor M28, the twenty-ninth PMOS transistor M29, and the thirtieth NMOS transistor M30. The thirty-first PMOS transistor and the thirty-second NMOS transistor form a first inverter, and the thirty-third PMOS transistor and the thirty-fourth NMOS transistor form a second inverter, realizing waveform shaping and localizing the output signal of the hysteresis comparator, thereby improving the output stability.
[0116] Figure 4The circuit schematic diagram of a specific example of the operational amplifier in the embodiments of the present application is shown. Among them, the specific circuit structure of the operational amplifier can be set according to actual needs and is not limited thereto. In an alternative embodiment, the operational amplifier OP includes an eleventh PMOS transistor M11, a twelfth PMOS transistor M12, a thirteenth PMOS transistor M13, a fourteenth NMOS transistor M14, a fifteenth NMOS transistor M15, a sixteenth PMOS transistor M16, a seventeenth NMOS transistor M17, an eighteenth NMOS transistor M18, and a nineteenth PMOS transistor M19;
[0117] The gate of the eleventh PMOS transistor M11 is configured as the non-inverting input terminal In+ of the operational amplifier OP; the gate of the twelfth PMOS transistor M12 is configured as the inverting input terminal In- of the operational amplifier OP;
[0118] The sources of the eleventh PMOS transistor M11 and the twelfth PMOS transistor M12 are respectively connected to the drain of the thirteenth PMOS transistor M13. The source of the thirteenth PMOS transistor M13 is connected to the first power supply terminal vdda, and the gate of the thirteenth PMOS transistor M13 is configured to obtain a third bias signal Vp;
[0119] The drain of the eleventh PMOS transistor M11 is respectively connected to the drain of the fourteenth NMOS transistor M14 and the source of the fifteenth NMOS transistor M15. The drain of the twelfth PMOS transistor M12 is respectively connected to the drain of the seventeenth NMOS transistor M17 and the source of the eighteenth NMOS transistor M18;
[0120] The sources of the fourteenth NMOS transistor M14 and the seventeenth NMOS transistor M17 are respectively connected to the second power supply terminal vssa. The gates of the fourteenth NMOS transistor M14 and the seventeenth NMOS transistor M17 are respectively configured to obtain a second bias signal Vb2;
[0121] The drain of the fifteenth NMOS transistor M15 is respectively connected to the drain of the sixteenth PMOS transistor M16, the gate of the sixteenth PMOS transistor M16, and the gate of the nineteenth PMOS transistor M19. The gates of the fifteenth NMOS transistor M15 and the eighteenth NMOS transistor M18 are respectively configured to obtain a first bias signal Vb1. The drain of the eighteenth NMOS transistor M18 is connected to the drain of the nineteenth PMOS transistor M19 and is configured as the output terminal OPout of the operational amplifier;
[0122] The sources of the sixteenth PMOS transistor M16 and the nineteenth PMOS transistor M19 are respectively connected to the first power supply terminal vdda.
[0123] The embodiment of the present application also provides a low dropout regulator circuit. Figure 5 Figure 5 shows a schematic circuit diagram of a specific example of the low dropout regulator circuit in the embodiment of the present application. As shown in the figure, the low dropout regulator circuit includes an error amplifier EA, a power transistor MP, a voltage feedback circuit 10, and a current limiting circuit as described in the above embodiment.
[0124] The inverting input terminal of the error amplifier EA is configured to obtain a first reference voltage vref1. The non-inverting input terminal of the error amplifier EA is connected to the output terminal of the voltage feedback circuit 10, and the output terminal of the error amplifier EA is connected to the control terminal of the power transistor MP. The first signal terminal of the power transistor MP is connected to a first power supply terminal vdda, and the second signal terminal of the power transistor MP is connected to the input terminal of the voltage feedback circuit 10 and is configured to provide the output voltage vout of the low dropout regulator circuit.
[0125] Wherein, the second signal terminal of the power transistor MP is connected to the non-inverting input terminal of the operational amplifier OP of the current limiting circuit, and the control terminal of the power transistor MP is connected to the output terminal of the operational amplifier OP, so that the output voltage vout and the detection voltage v- at the non-inverting input terminal of the operational amplifier OP are kept consistent based on the clamping effect of the operational amplifier OP.
[0126] In the embodiment of the present application, the power transistor MP can be referred to the above, and will not be elaborated here.
[0127] Figure 6 Figure 6 shows a schematic circuit diagram of a specific example of the error amplifier in the embodiment of the present application. Among them, the specific circuit structure of the error amplifier can be set according to actual needs and is not limited thereto. In an optional embodiment, the error amplifier EA includes a first PMOS transistor M1, a second PMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a fifth NMOS transistor M5, a sixth NMOS transistor M6, a seventh NMOS transistor M7, an eighth NMOS transistor M8, a ninth PMOS transistor M9, a tenth PMOS transistor M10, a thirty-fifth PMOS transistor M35, and a compensation capacitor Cc.
[0128] The gate of the first PMOS transistor M1 is configured as the inverting input terminal of the error amplifier EA; the gate of the second PMOS transistor M2 is configured as the non-inverting input terminal of the error amplifier EA.
[0129] The drain of the first PMOS transistor M1 is connected to the drains of the third NMOS transistor M3, the gate of the third NMOS transistor M3, and the gate of the fifth NMOS transistor M5 respectively. The drain of the second PMOS transistor M2 is connected to the drains of the fourth NMOS transistor M4, the gate of the fourth NMOS transistor M4, and the gate of the sixth NMOS transistor M6 respectively. The drain of the fifth NMOS transistor M5 is connected to the source of the seventh NMOS transistor M7. The drain of the sixth NMOS transistor M6 is connected to the source of the eighth NMOS transistor M8. The drain of the seventh NMOS transistor M7 is connected to the drains of the ninth PMOS transistor M9, the gate of the ninth PMOS transistor M9, and the gate of the tenth PMOS transistor M10 respectively. The drain of the eighth NMOS transistor M8 is connected to the drain of the tenth PMOS transistor M10 and configured as the output terminal of the error amplifier EA.
[0130] The gates of the seventh NMOS transistor M7 and the eighth NMOS transistor M8 are respectively configured to obtain the second low bias signal vbn2. The sources of the third NMOS transistor M3, the fourth NMOS transistor M4, the fifth NMOS transistor M5, and the sixth NMOS transistor M6 are respectively connected to the second power supply terminal vssa. The sources of the first PMOS transistor M1 and the second PMOS transistor M2 are respectively connected to the drain of the thirty-fifth PMOS transistor M35. The gate of the thirty-fifth PMOS transistor M35 is configured to obtain the first high bias signal vbp1. The sources of the thirty-fifth PMOS transistor M35, the ninth PMOS transistor M9, and the tenth PMOS transistor M10 are respectively connected to the first power supply terminal vdda.
[0131] The first end of the compensation capacitor Cc is connected to the drain of the sixth NMOS transistor M6 and the source of the eighth NMOS transistor M8 respectively. The second end of the compensation capacitor Cc is connected to the output terminal of the low dropout regulator circuit.
[0132] In the embodiment of the present application, the gate of the first PMOS transistor M1 can be configured to receive the reference voltage signal Vref. The gate of the second PMOS transistor M2 can be configured to obtain the feedback signal vfb and can be connected to the connection node between the first resistor R1 and the second resistor R2. The gate of the power transistor MP can be connected to the drain of the eighth NMOS transistor M8. The output terminal of the low dropout regulator circuit is used to output the output voltage vout of the low dropout regulator circuit.
[0133] In the embodiments of the present application, the compensation capacitor Cc can be a single capacitor, or a series and / or parallel combination of multiple capacitors. It can also be a passive capacitor network or an active capacitor network including resistors, capacitors, inductors, etc. Through the compensation capacitor Cc, the function of the Miller compensation capacitor is provided, which can improve the stability of the output voltage vout.
[0134] In this way, due to the high-precision response accuracy of the current limiting circuit in the low dropout regulator circuit of the embodiments of the present application, the channel length modulation effect can be avoided, enabling the low dropout regulator circuit to accurately respond to output overcurrent and determine restart based on a certain current capacity, thereby more precisely improving safety.
[0135] In the embodiments of the present application, the specific circuit structure of the voltage feedback circuit 10 can be set according to actual needs and is not limited to Figure 5 the shown structure. In an alternative embodiment, the voltage feedback circuit 10 includes a first resistor R1 and a second resistor R2;
[0136] The non-inverting input terminal of the error amplifier EA is respectively connected to the second terminal of the first resistor R1 and the first terminal of the second resistor R2. The first terminal of the first resistor R1 is respectively connected to the second signal terminal of the power transistor MP and the non-inverting input terminal of the operational amplifier OP of the current limiting circuit; the second terminal of the second resistor R2 is connected to the second power supply terminal vssa.
[0137] In the embodiments of the present application, both the first resistor R1 and the second resistor R2 can be a single resistor, or a series and / or parallel combination of multiple resistors. They can also be a passive resistor network or an active resistor network including resistors, capacitors, inductors, etc.
[0138] In the embodiments of the present application, the first bias signal Vb1, the second bias signal Vb2, the third bias signal Vp, the first low-level bias signal vbn1, the second low-level bias signal vbn2, and the first high-level bias signal vbp1 can all be provided by an external bias circuit, and these bias circuits can be controlled by a logic control circuit. These are not the inventive points of the utility model, and the bias circuit and the logic control circuit are both prior arts, and the present utility model will not be introduced in detail.
[0139] The transistors in the embodiments of the present application can be single or a series and / or parallel combination of multiple ones.
[0140] The embodiments of the present application also provide a radio frequency module, which includes the low dropout regulator circuit as described in the above embodiments, thereby being able to precisely improve the safety of the radio frequency module and more effectively reduce module / chip heating, burning, etc.
[0141] It should be understood that the above embodiments are all exemplary and do not cover all possible implementation manners included in the claims. Without departing from the scope of the present disclosure, various deformations and changes can also be made on the basis of the above embodiments. Similarly, the technical features of the above embodiments can also be arbitrarily combined to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only represent several implementation manners of the present application and do not limit the protection scope of the patent of the present application.
Claims
1. A current limiting circuit, characterized in that, The current limiting circuit includes: A current detection module configured to obtain a detection current by proportionally replicating the current flowing through the power transistor of the low dropout regulator circuit using a detection transistor, and determine a detection voltage based on the detection current; A current limiting control module configured to obtain the detection voltage, and output a current limiting control signal to the control terminal of the power transistor when the detection voltage exceeds a second reference voltage to limit the current flowing through the power transistor; and when the current flowing through the power transistor drops such that the detection voltage is lower than a recovery threshold voltage, turn off the output of the current limiting control signal to enable the low dropout regulator circuit to resume normal output; wherein the recovery threshold voltage is less than or equal to the second reference voltage; An operational amplifier, the non-inverting input terminal of which is configured to obtain an output voltage determined based on the current flowing through the power transistor, the inverting input terminal of which is configured to obtain the detection voltage, and the output terminal of which is connected to the control terminal of the power transistor, and is used to make the output voltage and the detection voltage consistent based on the clamping effect of the operational amplifier; Wherein, at least a negative feedback loop is formed based on the operational amplifier and the power transistor; at least a positive feedback loop is formed based on the operational amplifier and the detection transistor; and the net feedback of the negative feedback loop and the positive feedback loop is negative feedback.
2. The current-limiting circuit according to claim 1, wherein The current limiting control module includes: A hysteresis comparator configured to output a switching control signal of a first level when the detection voltage exceeds a current limiting threshold voltage; and output a switching control signal of a second level when the detection voltage is lower than a recovery threshold voltage; wherein the current limiting threshold voltage is greater than the second reference voltage, and the recovery threshold voltage is less than the second reference voltage; A switching transistor configured to conduct under the control of the switching control signal of the first level to output the current limiting control signal; and turn off under the control of the switching control signal of the second level to turn off the output of the current limiting control signal.
3. The current limiting circuit according to claim 2, wherein, The power transistor is a PMOS transistor; The switching transistor is a PMOS transistor; The inverting input terminal of the hysteresis comparator is configured to obtain the detection voltage, the non-inverting input terminal of the hysteresis comparator is configured to obtain the second reference voltage, and the output terminal of the hysteresis comparator is connected to the gate of the switching transistor; the source of the switching transistor is connected to a first power supply terminal, and the drain of the switching transistor is connected to the gate of the power transistor.
4. The current-limiting circuit according to claim 3, characterized in that, The current detection module includes a detection transistor and a detection resistor; The detection transistor is a PMOS transistor; The gate of the detection transistor is connected to the gate of the power transistor, the source of the detection transistor is connected to a first power supply terminal, the drain of the detection transistor is connected to the first end of the detection resistor and is configured to provide the detection voltage; the second end of the detection resistor is connected to a second power supply terminal.
5. The current limiting circuit according to claim 4, characterized in that, The hysteresis comparator includes a twentieth NMOS transistor, a twenty-first NMOS transistor, a twenty-second PMOS transistor, a twenty-third NMOS transistor, a twenty-fourth PMOS transistor, a twenty-fifth PMOS transistor, a twenty-sixth PMOS transistor, a twenty-seventh PMOS transistor, a twenty-eighth NMOS transistor, a twenty-ninth PMOS transistor, a thirtieth NMOS transistor, a thirty-first PMOS transistor, a thirty-second NMOS transistor, a thirty-third PMOS transistor, and a thirty-fourth NMOS transistor; The gate of the twentieth NMOS transistor is configured as the inverting input terminal of the hysteresis comparator; the gate of the twenty-first NMOS transistor is configured as the non-inverting input terminal of the hysteresis comparator; The drain of the twentieth NMOS transistor is respectively connected to the gate of the twenty-second PMOS transistor, the drain of the twenty-fourth PMOS transistor, the gate of the twenty-fourth PMOS transistor, the gate of the twenty-fifth PMOS transistor, and the drain of the twenty-sixth PMOS transistor. The drain of the twenty-first NMOS transistor is respectively connected to the gate of the twenty-ninth PMOS transistor, the drain of the twenty-seventh PMOS transistor, the gate of the twenty-seventh PMOS transistor, the gate of the twenty-sixth PMOS transistor, and the drain of the twenty-fifth PMOS transistor. The sources of the twentieth NMOS transistor and the twenty-first NMOS transistor are respectively connected to the drain of the twenty-eighth NMOS transistor. The source of the twenty-eighth NMOS transistor is connected to the second power supply terminal, and the gate of the twenty-eighth NMOS transistor is configured to obtain a first low bias signal; The sources of the twenty-fourth PMOS transistor, the twenty-fifth PMOS transistor, the twenty-sixth PMOS transistor, and the twenty-seventh PMOS transistor are respectively connected to the first power supply terminal; The sources of the twenty-second PMOS transistor and the twenty-ninth PMOS transistor are respectively connected to the first power supply terminal. The drain of the twenty-second PMOS transistor is respectively connected to the drain of the twenty-third NMOS transistor, the gate of the twenty-third NMOS transistor, and the gate of the thirtieth NMOS transistor. The sources of the twenty-third NMOS transistor and the thirtieth NMOS transistor are respectively connected to the second power supply terminal. The drain of the twenty-ninth PMOS transistor is respectively connected to the drain of the thirtieth NMOS transistor, the gate of the thirty-first PMOS transistor, and the gate of the thirty-second NMOS transistor; The drain of the thirty-first PMOS transistor is respectively connected to the drain of the thirty-second NMOS transistor, the gate of the thirty-third PMOS transistor, and the gate of the thirty-fourth NMOS transistor. The drain of the thirty-third PMOS transistor is connected to the drain of the thirty-fourth NMOS transistor and is configured as the output terminal of the hysteresis comparator; The sources of the thirty-first PMOS transistor and the thirty-third PMOS transistor are respectively connected to the first power supply terminal. The sources of the thirty-second NMOS transistor and the thirty-fourth NMOS transistor are respectively connected to the second power supply terminal.
6. The current limiting circuit according to any one of claims 1-5, characterized in that The operational amplifier includes an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth PMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, and a nineteenth PMOS transistor; The gate of the eleventh PMOS transistor is configured as the non-inverting input terminal of the operational amplifier; the gate of the twelfth PMOS transistor is configured as the inverting input terminal of the operational amplifier; The source of the eleventh PMOS transistor and the source of the twelfth PMOS transistor are respectively connected to the drain of the thirteenth PMOS transistor. The source of the thirteenth PMOS transistor is connected to the first power supply terminal, and the gate of the thirteenth PMOS transistor is configured to obtain a third bias signal; The drain of the eleventh PMOS transistor is respectively connected to the drain of the fourteenth NMOS transistor and the source of the fifteenth NMOS transistor. The drain of the twelfth PMOS transistor is respectively connected to the drain of the seventeenth NMOS transistor and the source of the eighteenth NMOS transistor; The source of the fourteenth NMOS transistor and the source of the seventeenth NMOS transistor are respectively connected to the second power supply terminal. The gate of the fourteenth NMOS transistor and the gate of the seventeenth NMOS transistor are respectively configured to obtain a second bias signal; The drain of the fifteenth NMOS transistor is respectively connected to the drain of the sixteenth PMOS transistor, the gate of the sixteenth PMOS transistor, and the gate of the nineteenth PMOS transistor. The gate of the fifteenth NMOS transistor and the gate of the eighteenth NMOS transistor are respectively configured to obtain a first bias signal. The drain of the eighteenth NMOS transistor is connected to the drain of the nineteenth PMOS transistor and is configured as the output terminal of the operational amplifier; The source of the sixteenth PMOS transistor and the source of the nineteenth PMOS transistor are respectively connected to the first power supply terminal.
7. A low dropout voltage regulator circuit, characterized in that, The low dropout voltage regulator circuit includes an error amplifier, a power transistor, a voltage feedback circuit, and the current limiting circuit according to any one of claims 1-6; The inverting input terminal of the error amplifier is configured to obtain a first reference voltage. The non-inverting input terminal of the error amplifier is connected to the output terminal of the voltage feedback circuit, and the output terminal of the error amplifier is connected to the control terminal of the power transistor; The first signal terminal of the power transistor is connected to the first power supply terminal. The second signal terminal of the power transistor is connected to the input terminal of the voltage feedback circuit and is configured to provide the output voltage of the low dropout voltage regulator circuit; Wherein, the second signal terminal of the power transistor is connected to the non-inverting input terminal of the operational amplifier of the current limiting circuit, and the control terminal of the power transistor is connected to the output terminal of the operational amplifier, so that the output voltage is kept consistent with the detection voltage at the inverting input terminal of the operational amplifier based on the clamping effect of the operational amplifier.
8. The low dropout voltage regulator circuit according to claim 7, wherein The error amplifier includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a thirty-fifth PMOS transistor, and a compensation capacitor; The gate of the first PMOS transistor is configured as the inverting input terminal of the error amplifier; the gate of the second PMOS transistor is configured as the non-inverting input terminal of the error amplifier; The drain of the first PMOS transistor is respectively connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor, and the gate of the fifth NMOS transistor. The drain of the second PMOS transistor is respectively connected to the drain of the fourth NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the sixth NMOS transistor. The drain of the fifth NMOS transistor is connected to the source of the seventh NMOS transistor. The drain of the sixth NMOS transistor is connected to the source of the eighth NMOS transistor. The drain of the seventh NMOS transistor is respectively connected to the drain of the ninth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor. The drain of the eighth NMOS transistor is connected to the drain of the tenth PMOS transistor and is configured as the output terminal of the error amplifier; The gates of the seventh NMOS transistor and the eighth NMOS transistor are respectively configured to obtain the second low bias signal; The sources of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the sixth NMOS transistor are respectively connected to the second power supply terminal. The sources of the first PMOS transistor and the second PMOS transistor are respectively connected to the drain of the thirty-fifth PMOS transistor. The gate of the thirty-fifth PMOS transistor is configured to obtain the first high bias signal. The sources of the thirty-fifth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are respectively connected to the first power supply terminal; The first end of the compensation capacitor is respectively connected to the drain of the sixth NMOS transistor and the source of the eighth NMOS transistor. The second end of the compensation capacitor is connected to the output terminal of the low dropout regulator circuit.
9. The low dropout voltage regulator circuit according to claim 7 or 8, characterized in that The voltage feedback circuit includes a first resistor and a second resistor; The non-inverting input terminal of the error amplifier is respectively connected to the second end of the first resistor and the first end of the second resistor. The first end of the first resistor is respectively connected to the second signal terminal of the power transistor and the non-inverting input terminal of the operational amplifier of the current limiting circuit. The second end of the second resistor is connected to the second power supply terminal.
10. A radio frequency module, characterized in that, The RF module includes the low dropout regulator circuit according to any one of claims 7-9.