Chip packaging structure and circuit system structure

Abstract

The utility model provides a chip packaging structure and a circuit system structure. The chip packaging structure comprises a bare chip, wherein the bare chip is provided with a top surface and a bottom surface which face opposite directions; the first pin is positioned on one side, close to the top surface of the bare chip, of the chip packaging structure; the second pin is positioned on one side, close to the bottom surface of the bare chip, of the chip packaging structure; a plurality of bonding wires, wherein each bonding wire is connected with the bare chip and the first pin or is connected with the bare chip and the second pin; wherein the first pin and the second pin are respectively provided with a first section close to the bare chip and a second section far away from the bare chip, and the second section of the first pin and the second section of the second pin are elongated in different planes. Therefore, the number of the pins of the chip packaging structure can be increased, more I / O connections are supported, and the flexibility of pin design of the chip packaging structure is improved. The circuit system structure comprises the chip packaging structure and a PCB electrically connected with the chip packaging structure.

Description

Technical Field

[0001] The utility model relates to the field of packaging technology, and particularly relates to a chip packaging structure and a circuit system structure. Background Art

[0002] With the rapid development of electronic technology, the packaging requirements for integrated circuit (IC) chips are getting higher and higher, especially the increasing demands for miniaturization, thinness, and high performance. The traditional single-layer pin packaging method has been difficult to meet these requirements because they usually have problems such as limited pin numbers, signal transmission delay, and insufficient thermal management.

[0003] The pins of the current chip packaging structure are only on the same plane, so the pins of the chip can only be pulled out for wiring on the same plane. All the wirings are concentrated on the same plane of the PCB board, which may lead to a decrease in signal quality due to mutual interference between the lines. Wiring on the same layer will also limit the flexibility of the wiring layout because the placement of components and signal flow need to be considered, which makes the design of the circuit board more complex, especially when arranging large components or components that need to be debugged in a limited space. In addition, since the pins of the chip packaging structure are on the same horizontal plane, in order to change the layer for wiring, it is inevitable to punch holes in the circuit board, which will bring some challenges to the electromagnetic compatibility and impedance matching of the PCB product. Additionally, the chip usually requires decoupling capacitors to be placed close to the power pins. If all the chip pins are on the same plane, placing the power decoupling capacitors nearby will make the wiring of the remaining IO pins difficult. Summary of the Utility Model

[0004] One of the purposes of the utility model is to increase the number of pins of the chip packaging structure, so as to support a larger number of I / O connections and improve the flexibility of the pin design of the chip packaging structure.

[0005] To achieve the above purpose, the utility model provides a chip packaging structure. The chip packaging structure includes: a die, the die having a top surface and a bottom surface facing opposite directions; at least one first pin, the first pin being located on one side of the chip packaging structure close to the top surface, the first pin having a first section close to the die and a second section away from the die; at least one second pin, the second pin being located on one side of the chip packaging structure close to the bottom surface, the second pin having a first section close to the die and a second section away from the die; and a plurality of bonding wires, each bonding wire connecting the die and the first pin or connecting the die and the second pin; wherein, the second sections of the first pins and the second sections of the second pins extend in different planes.

[0006] Optionally, the chip packaging structure includes a plurality of the first pins and a plurality of the second pins; the second segments of the plurality of the first pins extend in the same plane; the first segments of the plurality of the first pins extend in the same plane; the second segments of the plurality of the second pins extend in the same plane; the first segments of the plurality of the second pins extend in the same plane.

[0007] Optionally, the plurality of the second pins include power pins and ground pins, or the plurality of the first pins include power pins and ground pins.

[0008] Optionally, both the first pins and the second pins are connected to the top surface of the die through the bonding wires.

[0009] Optionally, the first pins are straight or bent; the second pins are straight or bent.

[0010] Optionally, the chip packaging structure further includes: a plastic package; the plastic package wraps the die and the bonding wires, at least a part of the first segment of the first pins is embedded in the plastic package and the second segment of the first pins exposes from the plastic package, at least a part of the first segment of the second pins is embedded in the plastic package and the second segment of the second pins exposes from the plastic package.

[0011] Optionally, a heat dissipation structure is provided on the top surface of the plastic package, and / or a heat dissipation structure is provided on the bottom surface of the plastic package.

[0012] Optionally, the die and the heat dissipation structure at least partially overlap in the thickness direction of the chip packaging structure.

[0013] The present utility model further provides a circuit system structure. The circuit system structure includes a PCB board and the above-mentioned chip packaging structure. The PCB board has a cavity penetrating through the PCB board. The chip packaging structure is installed in the cavity. The first pins are connected to the top surface pads of the PCB board, and the second pins are connected to the bottom surface pads of the PCB board.

[0014] Optionally, there is a gap between the side wall of the plastic package of the chip packaging structure and the side wall of the cavity.

[0015] Optionally, the circuit system structure further includes a plurality of electronic components other than the die, and the plurality of electronic components are installed on the PCB board.

[0016] Optionally, the plurality of electronic components include decoupling capacitors, and the decoupling capacitors are arranged close to the power pins of the chip packaging structure.

[0017] In the chip packaging structure and the circuit system structure provided by the present utility model, one side of the chip packaging structure close to the top surface of the bare die has a first pin. The first pin has a first section close to the bare die and a second section far from the bare die. One side of the chip packaging structure close to the bottom surface of the bare die has a second pin. The second pin has a first section close to the bare die and a second section far from the bare die. The second sections of the first pin and the second pin extend in different planes, that is, the chip packaging structure has a double-layer pin with soldering ends on different horizontal planes. Through the double-layer pin design of the chip packaging structure, the number of pins of the chip packaging structure can be increased, more I / O connections can be supported, the pin density of the packaging can be improved, the signal transmission efficiency can be improved, and the layout of the two-layer pins can be adjusted according to application requirements and pin characteristics, improving the flexibility of pin arrangement.

[0018] Furthermore, since the chip packaging structure has two layers of pins, the PCB board for mounting the chip packaging structure can correspondingly arrange two layers of pads. One layer of pins is connected to one layer of pads. Compared with all the pins of the chip packaging structure being connected to one layer of pads on the PCB board, the pressure on the routing layout of the PCB board can be reduced, providing room for improving the routing layout of the PCB board, facilitating reducing mutual interference between lines, improving the quality of signal transmission, and also facilitating the installation and arrangement of other electronic components on the PCB board, reducing the via interconnection in the PCB board, and improving the electromagnetic compatibility and impedance matching of the product. Description of the Drawings

[0019] Figure 1 It is a schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present utility model.

[0020] Figure 2 It is a schematic cross-sectional view of a circuit system structure provided by an embodiment of the present utility model.

[0021] Figure 3 It is a schematic structural view of a PCB board in an embodiment of the present utility model.

[0022] Description of the Reference Numerals: 10 - chip packaging structure; 100 - bare die; 101 - first pin; 102 - second pin; 103 - bonding wire; 104 - plastic package; 105 - heat dissipation structure; 106 - chip pad; 20 - PCB board; 201 - top surface pad; 202 - bottom surface pad; 203 - cavity. Detailed Embodiment

[0023] In order to increase the number of pins of the chip packaging structure, so as to support more I / O connections, improve the flexibility of the pin design of the chip packaging structure and the flexibility of the routing design of the PCB board connected to the pins of the chip packaging structure, the present application provides a chip packaging structure and a circuit system structure.

[0024] The following further elaborates on the chip packaging structure and circuit system structure proposed by the present utility model in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present utility model will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present utility model.

[0025] The terms used in the present utility model are only for the purpose of describing specific embodiments and are not intended to limit the present utility model. Unless otherwise defined in this application document, the technical terms or scientific terms used in the present utility model should have the ordinary meaning understood by those with ordinary skills in the field to which the present utility model belongs. The "first", "second" and similar terms used in the present utility model do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not indicate a quantity limitation, but indicate that there is at least one. "Multiple" or "several" means two or more. Unless otherwise specified, terms such as "upper" and / or "lower" are only for convenience of description and are not limited to a single position or a spatial orientation. The terms "including" or "comprising" and the like are intended to mean that the elements or structures appearing before "including" or "comprising" cover the elements or structures listed after "including" or "comprising" and their equivalents, and do not exclude other elements or structures.

[0026] Figure 1 It is a schematic cross-sectional view of the chip packaging structure provided for an embodiment of the present utility model. As Figure 1 shown, the chip packaging structure 10 includes a die 100, at least one first pin 101, at least one second pin 102, and a plurality of bonding wires 103. The die 100 has a top surface and a bottom surface facing opposite directions. The first pin 101 is located on one side of the chip packaging structure close to the top surface of the die 100, and the first pin 101 has a first section close to the die 100 and a second section far from the die 100. The second pin 102 is located on one side of the chip packaging structure close to the bottom surface of the die 100, and the second pin 102 has a first section close to the die 100 and a second section far from the die 100. Each bonding wire 103 connects the die 100 and the first pin 101 or connects the die 100 and the second pin 102. Among them, the second sections of the first pin 101 and the second pin 102 extend in different planes.

[0027] Specifically, the material of the die 100 includes silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other group III / V compounds, etc. The die 100 can be a chip particle obtained by directly cutting a wafer.

[0028] In this embodiment, the top surface of the die 100 has chip pins, and the die 100 can be electrically connected to the pins on the side of the die 100 through the chip pins.

[0029] The chip packaging structure may include a lead frame, and the lead frame may include a first pin 101, a second pin 102, and a chip pad 106. The die 100 is mounted on the chip pad 106. Exemplarily, the bottom surface of the die 100 is mounted on the chip pad 106. The first pin 101 is located above the top surface of the die 100. The second pin 102 is located below the bottom surface of the die 100.

[0030] In this embodiment, the lead frame includes a plurality of first pins 101 and a plurality of second pins 102. The plurality of first pins 101 are arranged around the periphery of the die 100, and the plurality of second pins 102 are also arranged around the periphery of the die 100. Each first pin 101 has a first segment close to the die 100 and a second segment far from the die 100, and each second pin 102 has a first segment close to the die 100 and a second segment far from the die 100. Among them, the second segments of the first pins 101 and the second pins 102 are both welding ends for welding to an external circuit (such as a PCB board).

[0031] Reference Figure 1 As shown, the first segments of the plurality of first pins 101 extend in the same plane, for example, extend in the first plane S1. The second segments of the plurality of first pins 101 extend in the same plane, for example, extend in the second plane S2. The first segments of the plurality of second pins 102 extend in the same plane, for example, extend in the fourth plane S4. The second segments of the plurality of second pins 102 extend in the same plane, for example, extend in the third plane S3. Among them, the second plane S2 and the third plane S3 are different planes.

[0032] In this embodiment, both the first pin 101 and the second pin 102 are curved strip-shaped pins. Both the first pin 101 and the second pin 102 include a third section connecting a first section and a second section. The third section of the first pin 101 spans from the first plane S1 to the second plane S2 to connect the first section and the second section of the first pin 101. The third section of the second pin 102 spans from the fourth plane S4 to the third plane S3 to connect the first section and the second section of the second pin 102. In this embodiment, the position of the plane where the second sections of the first pin 101 and the second pin 102 are located can be adjusted by adjusting the bending radians of the first pin 101 and the second pin 102. The position of the plane where the second sections of the first pin 101 and the second pin 102 are located determines the distance between the second sections of the two, and the distance between the second sections of the first pin 101 and the second pin 102 in the thickness direction of the die can be adjusted according to the thickness of the PCB board that cooperates with the chip packaging structure.

[0033] In other embodiments, both the first pin 101 and the second pin 102 can be straight strip-shaped pins, or one of the first pin 101 and the second pin 102 is straight strip-shaped and the other is curved. When both the first pin 101 and the second pin 102 are straight strip-shaped, the first section and the second section of the same pin are in the same plane, and the first pin 101 and the second pin 102 are in different planes.

[0034] In this embodiment, the pin densities of the multiple first pins 101 and the multiple second pins 102 around the die 100 can be selected according to the actual circuit design requirements.

[0035] In this embodiment, the first pin 101 is a top-layer pin and the second pin 102 is a bottom-layer pin, and the numbers of both the top-layer pins and the bottom-layer pins can be multiple. The placement of the two layers of pins can be arranged according to different characteristics of the pins. Or rather, according to the characteristics of the pins, the pins with matching characteristics are arranged on the same layer, and the pins with non-matching characteristics are arranged on different layers. In this way, the flexibility of the pin placement is relatively high, and it helps to improve the electrical performance of the chip packaging structure. Exemplarily, the power pins and the ground pins are arranged on the same layer, and they can be all arranged on the top layer or all arranged on the bottom layer; that is to say, the multiple second pins 102 include power pins and ground pins, or the multiple first pins 101 include power pins and ground pins.

[0036] In this application, the chip packaging structure includes two layers of pins; in other embodiments, if required by actual applications and for convenient connection, an intermediate pin can also be provided between the first pin 101 and the second pin 102 in the thickness direction of the chip packaging structure, and the plane where the intermediate pin is located is different from the planes where the first pin 101 and the second pin 102 are located.

[0037] Exemplarily, the materials of the first pin 101 and the second pin 102 can both be metals. In a specific embodiment, the materials of the first pin 101 and the second pin 102 can be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni.

[0038] The material of the chip pad 106 can be the same as or different from that of the pins. In some embodiments, the material of the chip pad 106 is a metal or an insulating material. The metal can be one or more of W, Al, Cu, Ti, Ag, Au, Pt, and Ni. The insulating material can be an inorganic insulating material or an organic insulating material. The inorganic insulating material can be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbide. The organic insulating material can be epoxy resin, polyimide resin, benzocyclobutene resin, or polybenzoxazole resin, or the organic insulating material can also be polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.

[0039] Continuing to refer Figure 1 As shown, the chip package structure includes a plurality of bonding wires 103. Both the first pin 101 and the second pin 102 are electrically connected to the chip pins on the surface of the die 100 through the bonding wires 103. Among them, one bonding wire 103 connects the die 100 and the first pin 101 or connects the die 100 and the second pin 102. More specifically, one end of the bonding wire 103 is bonded to the surface of the die 100, and the other end is bonded to the first section of the first pin 101 or the first section of the second pin 102.

[0040] In this embodiment, both the first pin 101 and the second pin 102 are connected to the top surface of the die 100 through the bonding wires 103, but it is not limited thereto. In other embodiments, the first pin 101 can be connected to the top surface of the die 100, and the second pin 102 can be connected to the bottom surface of the die 100.

[0041] The chip package structure further includes a molding compound 104. The molding compound 104 encapsulates the die 100 and the plurality of bonding wires 103. At least a part of the first section of the first pin 101 is embedded in the molding compound 104 and the second section of the first pin 101 is exposed from the molding compound 104. At least a part of the first section of the second pin 102 is embedded in the molding compound 104 and the second section of the second pin 102 is exposed from the molding compound 104. Exemplarily, the material of the molding compound 104 includes but is not limited to epoxy molding compound (EMC), ceramic, or metal alloy.

[0042] Refer Figure 1As shown, in this embodiment, the chip package structure has opposite first and second surfaces. The first section of the first pin 101 and the top surface of the encapsulant 104 can both be located within the first surface of the chip package structure, and the first section of the second pin 102 and the bottom surface of the encapsulant 104 can both be located within the second surface of the chip package structure, but it is not limited thereto.

[0043] Refer to Figure 1 As shown, the chip package structure may further include a heat dissipation structure 105.

[0044] In this embodiment, a heat dissipation structure 105 is provided on the top surface of the encapsulant 104, and a heat dissipation structure 105 is also provided on the bottom surface of the encapsulant 104. Thus, providing the heat dissipation structure 105 on the surface of the encapsulant 104 helps to enhance the heat dissipation capacity of the chip package structure, and heat dissipation structures are provided on both sides of the encapsulant, so that the chip package structure has multiple heat dissipation channels, which can further improve the heat dissipation effect. In other embodiments, the heat dissipation structure 105 may be provided only on the top surface or the bottom surface of the encapsulant 104. In other embodiments, the heat dissipation structure 105 may be provided inside the encapsulant 104, and multiple heat dissipation structures may also be provided on one side of the top surface or the bottom surface of the die 100.

[0045] In this embodiment, the heat dissipation structure 105 can be in the shape of a sheet, or in other shapes that are helpful for heat dissipation. The materials of the heat dissipation structure 105 include but are not limited to thermal grease, thermal gel, thermal conductive adhesive, or metal, etc.

[0046] To ensure the heat dissipation effect of the heat dissipation structure 105, the die 100 and the heat dissipation structure 105 at least partially overlap in the thickness direction of the chip package structure.

[0047] This embodiment also provides a circuit system structure. Figure 2 It is a cross-sectional schematic diagram of the circuit system structure provided by an embodiment of the present utility model. Figure 3 It is a structural schematic diagram of the PCB board in an embodiment of the present utility model. Refer to Figure 2 And Figure 3 As shown, the circuit system structure includes a PCB board 20 and the above-mentioned chip package structure 10. The PCB board 20 has a cavity 203 penetrating through the PCB board. The chip package structure 10 is installed in the cavity 203. The first pin 101 is connected to the top surface pad 201 of the PCB board, and the second pin 102 is connected to the bottom surface pad 202 of the PCB board.

[0048] Specifically, the PCB board 20 can be a printed circuit board or a ceramic PCB board, etc.

[0049] Refer toFigure 3 As shown, the top surface of the PCB board 20 has a plurality of top surface pads 201 corresponding to the first pins 101, and the bottom surface of the PCB board 20 has a plurality of bottom surface pads 202 corresponding to the second pins 102. The plurality of top surface pads 201 and the plurality of bottom surface pads 202 are arranged around the cavity 203.

[0050] The PCB board 20 may include a top circuit layer and a bottom circuit layer. The top circuit layer may include a plurality of the top surface pads 201, and the top surface pads 201 are connected to the circuits of the top circuit layer. The bottom circuit layer may include a plurality of bottom surface pads 202, and the bottom surface pads 202 are connected to the circuits of the bottom circuit layer. The top circuit layer and the bottom circuit layer may be interconnected through vias. In some embodiments of the present application, the PCB board 20 may further include an intermediate circuit layer, and the intermediate circuit layer, the top circuit layer, and the bottom circuit layer may be interconnected through vias.

[0051] Reference Figure 2 As shown, the plastic package 104 of the chip package structure may be embedded in the cavity 203 of the PCB board 20. The first pins 101 may extend to the top surface of the PCB board 20 and be soldered to the corresponding top surface pads 201, and the second pins 102 may extend to the bottom surface of the PCB board 20 and be soldered to the corresponding bottom surface pads 202.

[0052] Reference Figure 2 As shown, there may be a gap between the side wall of the plastic package 104 of the chip package structure and the side wall of the cavity 203, which is beneficial to the heat dissipation of the chip package structure and improves the thermal stability of the chip operation.

[0053] In this embodiment, the circuit system structure further includes a plurality of electronic components other than the bare die 100, and the plurality of electronic components are mounted on the PCB board 20. The plurality of electronic components may include decoupling capacitors, and the decoupling capacitors are arranged close to the power pins of the chip package structure 10.

[0054] It should be noted that since the chip package structure of this embodiment includes two layers of pins, and the two layers of pins are respectively connected to the two layers of pads of the PCB board 20, a plurality of electronic components may not be concentratedly mounted on one side of the PCB board 20. The installation layout flexibility of the electronic components is relatively high, and it also provides convenience for the installation layout of the electronic components that need to be arranged close to the corresponding pins (such as the decoupling capacitors that need to be placed close to the power pins), which is beneficial to shortening the signal transmission path between the corresponding pins and the electronic components, reducing the signal delay, improving the signal transmission efficiency, avoiding excessive drilling in the PCB board, and facilitating the arrangement of other traces around the electronic components.

[0055] In the chip packaging structure and circuit system structure provided by the present utility model, one side of the chip packaging structure close to the top surface of the bare die 100 has a first pin 101. The first pin 101 has a first section close to the bare die 100 and a second section far from the bare die 100. One side of the chip packaging structure close to the bottom surface of the bare die 100 has a second pin 102. The second pin 102 has a first section close to the bare die and a second section far from the bare die. The second sections of the first pin 101 and the second pin 102 extend in different planes, that is, the chip packaging structure has a double-layer pin with soldering ends on different horizontal planes. Through the double-layer pin design of the chip packaging structure, the number of pins of the chip packaging structure can be increased, more I / O connections can be supported, the pin density of the packaging can be improved, the signal transmission efficiency can be improved, and the layout of the two-layer pins can be adjusted according to application requirements and pin characteristics, improving the flexibility of pin arrangement.

[0056] Furthermore, since the chip packaging structure has two layers of pins, the PCB board 20 for mounting the chip packaging structure can correspondingly arrange two layers of pads. One layer of pins is connected to one layer of pads. Compared with all the pins of the chip packaging structure being connected to one layer of pads on the PCB board, the pressure on the routing layout of the PCB board 20 can be reduced, providing room for improving the routing layout of the PCB board 20, facilitating reducing the mutual interference between lines, improving the quality of signal transmission, and also facilitating the installation and arrangement of other electronic components on the PCB board, reducing the through-hole interconnection in the PCB board, and improving the electromagnetic compatibility and impedance matching of the product.

[0057] It should be noted that this specification is described in a progressive manner. The parts described later mainly focus on the differences from the parts described earlier. For the same and similar parts between each part, reference can be made to each other.

[0058] The above description is only a description of the preferred embodiments of the present utility model, and does not limit any scope of the rights of the present utility model. Any person skilled in the art can make possible changes and modifications to the technical solution of the present utility model by using the methods and technical contents disclosed above without departing from the spirit and scope of the present utility model. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present utility model without departing from the content of the technical solution of the present utility model all belong to the protection scope of the technical solution of the present utility model.

Claims

1. A chip packaging structure, characterized in that, Comprising: A die having a top surface and a bottom surface facing opposite directions; At least one first pin located on a side of the chip package structure close to the top surface, the first pin having a first section close to the die and a second section away from the die; At least one second pin located on a side of the chip package structure close to the bottom surface, the second pin having a first section close to the die and a second section away from the die; And A plurality of bonding wires, each bonding wire connecting the die and the first pin or connecting the die and the second pin; Wherein, the second sections of the first pins and the second sections of the second pins extend in different planes.

2. The chip packaging structure according to claim 1, wherein, The chip package structure includes a plurality of the first pins and a plurality of the second pins; the second sections of the plurality of first pins extend in the same plane; the first sections of the plurality of first pins extend in the same plane; The second sections of the plurality of second pins extend in the same plane; the first sections of the plurality of second pins extend in the same plane.

3. The chip packaging structure according to claim 2, wherein The plurality of second pins include power pins and ground pins, or, the plurality of first pins include power pins and ground pins.

4. The chip packaging structure according to claim 1, characterized in that, Both the first pin and the second pin are connected to the top surface of the die through the bonding wire.

5. The chip packaging structure according to claim 1, wherein, The first pin is straight or bent; the second pin is straight or bent.

6. The chip packaging structure according to claim 1, wherein It further includes a plastic package body; the plastic package body wraps the die and the bonding wires, at least a part of the first section of the first pin is embedded in the plastic package body and the second section of the first pin exposes out of the plastic package body, at least a part of the first section of the second pin is embedded in the plastic package body and the second section of the second pin exposes out of the plastic package body.

7. The chip package structure according to claim 6, wherein A heat dissipation structure is provided on the top surface of the plastic package body, and / or, a heat dissipation structure is provided on the bottom surface of the plastic package body.

8. The chip packaging structure according to claim 7, wherein The die and the heat dissipation structure at least partially overlap in the thickness direction of the chip package structure.

9. A circuit system structure, characterized in that, Including a PCB board and the chip package structure according to any one of claims 1 to 8, the PCB board has a cavity penetrating through the PCB board, the chip package structure is installed in the cavity, the first pin is connected to a top surface pad of the PCB board, and the second pin is connected to a bottom surface pad of the PCB board.

10. The circuit system structure according to claim 9, characterized in that, There is a gap between the side wall of the plastic package body of the chip package structure and the side wall of the cavity.

11. The circuit system structure according to claim 9, wherein, The circuit system structure further includes a plurality of electronic components other than the chip package structure, and the plurality of electronic components are installed on the PCB board.

12. The circuit system structure according to claim 11, wherein, The plurality of electronic components include decoupling capacitors, and the decoupling capacitors are arranged close to the power pins of the chip package structure.

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